Digital And Logic

Design
SEQUENTIAL CIRCUITS

 A Sequential Circuit is a combinational logic circuit to which memory

elements are connected to form a feedback path. Memory elements
are devices capable of storing binary information within them. Binary
information in memory elements at any given time defines the state
of sequential
SEQUENTIAL CIRCUITS CONTD...

 A combinational logic circuit produces an output based on present

input values but a sequential logic circuit produces an output based
on current input and also previous input values.
 The latches and the flip flops are the building blocks of the sequential
circuits. One latch or flip flop can store one bit of information.
 There are basically four main types of latches and flip flops: SR,D,JK
and T.
 MEMORY ELEMENTS:
 Sequential circuits include memory elements that are capable of
storing binary information. The basic memory element in sequential
logic circuits is
TYPES OF SEQUENTIAL CIRCUITS

 There are two main types of sequential circuits. Their classification

depends on the timing of their signals.
 Synchronous sequential circuit is a system whose behavior can
be defined by the knowledge of signals at discrete instant of time.
 Asynchronous sequential circuit is a system whose behavior
depends upon the order in which its input signals change and can be
affected at any instant of time.
 Memory element used in asynchronous sequential circuit are time
delay device. Memory capability of time delay devices due to finite
time it takes for the signal to propagate through the device.
Clock Pulse
TYPES OF SEQUENTIAL CIRCUITS
Contd…
 Synchronous sequential that use clock pulses in the input of memory
elements are called clocked sequential circuit. Clocked sequential
circuit are type encountered most frequently. Their timing is divided
into independent discrete steps each of which is considered
separately.
 Memory elements in clocked sequential circuits are called flip-flop.
These circuits are binary cells capable of storing one bit of
information. A flip-flop circuit has two output one for normal value
and one for complement value. Binary information can enter a flip-
flop in a variety of ways , a fact give rise to a different types of flip-
flop.
TYPES OF SEQUENTIAL CIRCUITS
Contd..
Flip-Flops

 A flip-flop can maintain a binary state indefinitely (as long as power is

delivered to circuit) until directed by an input signal to switch state.
 Major difference among different types of flip-flop is the number of
inputs they possess and the manner in which inputs affect the binary
state.
 Flip-flop circuit can be constructed by two NAND gates and two NOR
gates.
Basic Flip-Flop Circuit Contd…

 Each flip-flop has two outputs Q and Q’ and two inputs set and reset.
This type of flip-flop is sometimes called as direct-coupled RS flip-flop
or SR latch.
 The cross coupled connection from the output of one gate to the
input of other gate constitutes a feedback path.
RS Flip-Flop

 RS Flip-Flop can be constructed by using basic flip-flop circuits with

two additional NAND gates.
RS Flip-Flop Contd…

 Pulse input act as an enable signal for other two inputs. Output of
NAND gates stay at logic 1 as long as CP remains at 0. When pulse
input goes to 1 information from S or R input is allowed to reach the
output. The set state is reached with S=1,R=0 and CP=1. This causes
the output of gate 3 to go to 0, the output of gate 4 to remain at 1,
and the output of flip-flop at Q to go to 1.
 To change the reset state, the output must be S=0, R=1 and CP=1. In
either case CP return to 0 circuit remains in the previous state.
D flip-flop

 To eliminate undesirable condition of indeterminate state in RS flip

flop is to ensure that input S and R are never equal to 1 at the same
time. This is achieved by using D flip-flop.
 D flip-flop has only two inputs D and Cp. D input goes directly to S
input and its complement is applied to the R input.
 As long as pulse input is at 0, the output of gates 3 and 4 are a the 1
level and circuit can not change state regardless of the value of D.
The D input is sampled when CP=1. if D is 1 he Q output goes to 1,
placing the circuit in the set state. If D is 0 output goes to 0 and
circuit switches to clear state.
 D flip-flop has ability to hold data due to its internal storage. This type
of flip-flop is sometimes called gated D-latch.
D flip-flop Contd…
JK and T flip-flop

 JK flip-flop is a refinement of the RS flip-flop in the indeterminate

state of RS type is defined in the jK type. Input J and K behave like
inputs S and R to set and clear the flip-flop. Input marked J is for set
and input marked K is for reset. When both inputs J and K are equal to
1, the flip-flop switches to its complement state i.e. if Q=1 it switches
to Q=0.
 Feedback connection in JK flip-flop , a CP pulse that remains in the
state while both J and K are equal to 1 will cause the output to
complement again and repeat complementing until the pulse goes
back to 0.
 To avoid this undesireable operation the clock pulse must have a time
duration that is shorter than the propgation delay time of flip-flop.
JK flip-flop
T flip-flop

 T flip-flop is a single input version of JK flip-flop. T flip-flop is obtained

from JK flip-flop when both inputs are tied together.
Triggering of flip-flops

 State of a flip-flop is switched by a momentary change in the input

signal. This momentary change is called a trigger and transition it
causes is said to trigger the flip-flop.
 A clocked pulse may be either positive an negative. A positive clock
source remains at o during the interval between the pulses and goes
to 1 during the occurrence of a pulse. The pulse goes form two signal
transition from 0 to 1 and back 1 to 0.
MASTER SLAVE FLIP-FLOP

 A master slave flip-flop is constructed from two separate flip-flops.

 One circuit serves as a master and the other as a slave.
 A clock and an inverter is present in the circuit.
 The output from the master flip-flop is connected to the two inputs of
the slave flip-flop.
 Each flip-flop is connected to a clock pulse complementary to each
other.
 If the clock pulse is in high state , the master flip flop is in ENABLE
state and the slave flip-flop is in DISABLE state.
 If the clock pulse is in low state , the master flip-flop is in DISABLE
state and the slave flip-flop is ENABLE state.
MASTER SLAVE FLIP-FLOP Contd…
Clocked Master Slave JK Flip-Flop
Clocked Master Slave JK Flip-Flop

 It consists of two flip-flops states 1 to through 4 from the master flip-

flop and gates 5 through 8 from the slave flip-flop. Information
present at the J and K inputs is transmitted to the master flip-flop on
the positive edge if a clock pulse and is held there negative edge of
clock pulse occurs . After which it is allowed to pass through slave
flip-flop.
 Te clock input is at o0, which keeps the outputs of gates 1 and 2 at
level 1. It prevent J and K inputs from affecting master flip-flop. Slave
flip-flop is a clocked RE type wit master flip-flop supplying the inputs
and the clock input being inverted by a ate 9. When the clock is 0
output of ate 9 is 1 so tat output Q is equal to Y and Q is equal to Y.
 When the positive edge of clock pulse occurs, master flip-flop is
affected and may switch states.
Latches

 Latches are asynchronous – which means, the output of the latch depends on
its input
 Latch is an electronic logic circuit with two stable states
 Latch is a type of temporary storage device.
 There are two inputs and two outputs of the latch.
 The outputs of the circuit are compliment of each other
 Latch circuits can work in two states depending on the triggering signal
being high or low: Active – High or Active – Low.
 In case of Active – High latch circuits, normally both the inputs are low. The
circuit is triggered by a momentary high on either of the inputs.
 In case of Active – Low latch circuits, normally both the inputs are high. The
circuit is triggered by a momentary low on either of the input
DIFFERENCE BETWEEN LATCHES &
FLIP-FLOP
 LATCHES
 Latches do not have a clock signal.
 Works with only binary input.
 Level triggered
 Asynchronous
 Operation is faster in latches.
FLIP –FLOPS

 FLIP –FLOPS
 Flip flop always has a clock signal.
 Works with binary input as well as the clock signal.
 Edge triggered.
 Synchronous
 Operation is comparatively slower due to clock signal.
The End

 Thanks