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VLSI Training & Placements
INTRODUCTION TO VLSI
DESIGN FLOW
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Outline
• What is an IC?
• ASIC Design Flow
• Frontend Block
• Backend Block
• DFT Flow
• Complete ASIC Design Flow
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What is an IC ?
• An Integrated Circuit (IC) chip is a device with large number of
electronic circuits built onto a tiny plate of semiconductor material
which is usually silicon
• VLSI refers to Very Large Scale Integration
• So, a VLSI-IC is where billions of transistors, resistors, capacitors
are placed on a small piece of silicon wafer to perform required
functionality/logic.
Plastic Case
Silicon Chip
Integrated
circuit’s elements
Integrated
circuit chip
Pins
(die)
wafer
ASIC Design Flow
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• ASIC (Application-Specific Integrated Circuit) is a customized
integrated circuit designed for a specific application or function,
unlike general-purpose ICs.
Front End
DFT
Logic Synthesis
Insertion
Back End
Frontend Block
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• Front-End Design in ASIC focuses on defining and verifying the
circuit's functionality before physical implementation.
Requirements in terms of Functionality,
power, performance, Area
Specifications
Architectural Design
always@(A or B or CI)
RTL Coding begin
S = A ^ B ^ CI;
Meet Specs? (No)
Co = (A & B) | (A & CI) | (B & CI);
Functional Verification end
Meet Specs? (Yes)
Backend Flow
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Frontend Block
• Steps in Frontend Block are:
Specification : Define functionality, power, performance, and area
requirements.
Architectural Design: High-level block design based on specs.
RTL Coding: Coding logic using hardware description languages
(e.g., Verilog)
Functional Verification: Checks if the RTL meets specifications.
Backend Block
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• Back-End Design in ASIC focuses on the physical implementation of
the circuit described in the front-end.
Frontend Flow Physical Design
Floorplanning
Placement and Clock Tree Synthesis
Logic Synthesis
Routing
Gate Level Netlist
Logic Equivalence Static Timing Analysis
Check Meet Specs? (No) Meet Specs? (Yes)
Physical Verification and Signoff
Logic Meet Specs? (No) Meet Specs? / Pass Checks (Yes)
Design Tape-out
Backend Block
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• Logic Synthesis: Converts the high-level design description (usually
written in HDL like Verilog or VHDL) into a gate-level netlist.
• Gate Level Netlist: A representation of the circuit in terms of logic
gates and interconnections.
• Logic Equivalence Check: Verifies that the synthesized gate-level
netlist is functionally equivalent to the original high-level design.
• Floorplanning: Determines the placement of major functional blocks
on the chip.
Backend Block
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• Placement and Clock Tree Synthesis: Places all standard cells in
the design and creates a balanced clock distribution network
• Routing: Connects all the placed cells according to the netlist using
metal layers.
• Static Timing Analysis: Analyzes the timing of the design to ensure
it meets the required performance.
• Physical Verification and Signoff: Checks for design rule violations
and ensures the layout matches the schematic.
• Tape-out: The final step where the design is sent to the fabrication
facility for manufacturing.
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DFT Flow
• DFT (Design for Testability) Flow ensures that ASIC designs are
testable after fabrication to detect manufacturing defects.
Specification
Functional
RTL
Verification
Synthesis
Netlist
DFT Insertion
Scan
Insertion
Floor Planning
ATPG
Place & Route
Pattern
Simulation
DFT Verification
DFT Insertion
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Netlist
• The netlist is a description of the electronic circuit, detailing the
components and their interconnections.
• It serves as the input for the DFT insertion process.
• The netlist is generated after the synthesis stage and is used to
ensure that the design can be tested effectively.
Scan Insertion
• Scan insertion involves adding scan chains to the design.
• Scan chains are used to shift test patterns into and out of the circuit.
• This step modifies the netlist to include additional logic for testability,
such as scan flip-flops.
DFT Insertion
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ATPG (Automatic Test Pattern Generation)
• ATPG is the process of generating test patterns that can be used to
detect faults in the circuit.
• These test patterns are designed to maximize fault coverage,
ensuring that as many potential defects as possible can be detected.
• ATPG tools analyze the modified netlist with scan chains to create
effective test vectors.
Pattern Simulation
• Pattern simulation involves simulating the generated test patterns on
the design.
• This step verifies that the test patterns will work correctly when
applied to the actual hardware.
ASIC Design Flow
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Specifications Routing
Architectural Design Signoff
RTL Design Fabrication
Logic Synthesis Packaging & Testing
DFT CHIP
Floorplan
Placement
CTS
