B38DF

Computer Architecture and Embedded Systems

Alexander Belyaev

Heriot-Watt University
School of Engineering & Physical Sciences
Electrical, Electronic and Computer Engineering

E-mail: [email protected]
Office: EM2.29

Based on the slides prepared by Dr. Mustafa Suphi Erden

B38DF: Computer Architecture and Embedded Systems 1/17

Processors – Part-1
 Processor (CPU) in a Computer

Fetching instructions from

the main memory and
determining their type

Performs operations such

as addition and Boolean
AND needed to carry out
Program Counter (PC): the instructions
points to the next
instruction to be fetched
for execution High-speed memory used
to store temporary results
and certain control
Instruction Register (IR): information
holds the instruction
currently being executed

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. 2/17
 Registers, ALU, Control Unit
• Registers hold data that can be readily accessed by the CPU.
• They can be implemented using D flip-flops.
– A 32-bit register requires 32 D flip-flops.

• The arithmetic-logic unit (ALU) carries out logical and arithmetic

operations as directed by the control unit.

• The control unit determines which actions to carry out according to

the values in a program counter register and a status register.

Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. 3/17
 Buses

• The CPU shares data with other system components by way of a data
bus.
– A bus is a set of wires that simultaneously convey a single bit
along each line.
• Two types of buses are commonly found in computer systems: point-
to-point (e.g., inside CPU), and multipoint buses.

4/17
 CPU Organization – Data Path

Data Path
=
Registers
+
ALU
+
Connection Buses

Data Path Cycle:

The process of running two
operands through the ALU and
Arithmetic
storing the result back in the
logic unit
registers

The heart of most CPUs

The faster the data path The data path of a typical
the faster the machine runs Von Neumann machine

5/17
Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc.
You already know how to build ALU : ADDer, Comparator, …

6/17
You already know how to build ALU : ADDer, Comparator, …

7/17
 Instruction Types
Register-memory instructions

• Allow memory words to be fetched into registers

• Allow registers to be stored back into memory

Register-register instructions

1. Fetch two operands from the register,

2. bring them to the ALU input registers,

3. perform some operation on them,

4. store the result back in one of the registers.

8/17
Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc.
 Instruction Format
Instructions are coded with bits
Machine Instruction = the opcode + the operands

Operation Code (Opcode)

The instruction set assigns each operation to a unique code.
ADD Add
integer addition opcode five SUB Subtract
integer subtraction opcode twelve MPY Multiply
DIV Divide
LOAD Load data from memory
Mnemonics are representations of Opcodes STOR Store data to memory

9/17
Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc.
 Instruction Format – Operand References

• Source Operand Reference

the place where the inputs are for the operation

• Result Operand Reference

the place where the result is to be recorded

• Next Instruction Reference

the place of the next instruction

10/17
Program Execution - CPU Cycle
Fetch-decode-execute

1) Instruction Read

2) Instruction Fetch

3) Decode and Specify Instruction

4) Data Read

5) Data Process

6) Data Store

7) Increment Program Counter

11/17
 1) Instruction Read
Program Counter (PC) register
points to the next instruction to
Program Execution 2) Instruction Fetch
3) Decode and Specify Instruction
be fetched for execution CPU Cycle 4)
5)
Data Read
Data Process
6) Data Store
CPU 7) Increment Program Counter
(Central Processing Unit)
Main Memory (1 word = 16 bits, 1MB)
Control Unit
PC 1 Operation Operand 1 Operand 2
Code (4bit for a (4bit for a
7
(8 bit) Register) Register)
IR 2

Arithmetic and 7 Operation Operand 1 Destination

Logic Unit Code
(ALU)
4 Destination (20 bit)
5 Registers
6

Instruction Register (IR) holds the

instruction currently being executed
12/17
 1) Instruction Read
Program Execution 2) Instruction Fetch
3) Decode and Specify Instruction
CPU Cycle 4)
5)
Data Read
Data Process
6) Data Store
CPU 7) Increment Program Counter
(Central Processing Unit)
Main Memory (1 word = 16 bits, 1MB)
Control Unit
Operation Operand 1 Operand 2
Code (4bit for a (4bit for a
PC 1
(8 bit) Register) Register)
7 Decode 2

Arithmetic and Operation Operand 1 Destination

Logic Unit (ALU) Code

Registers 4 Destination (20 bit)

6
5

13/17
Clocks
• Every computer contains at least one clock that synchronizes the
activities of its components.
• A fixed number of clock cycles are required to carry out each data
movement or computational operation.
• The clock frequency, measured in megahertz or gigahertz,
determines the speed with which all operations are carried out.
• Clock cycle time is the reciprocal of clock frequency.
– An 800 MHz clock has a cycle time of 1.25 ns.

• Clock speed should not be confused with CPU performance.

• The CPU time required to run a program is given by the general
performance equation:

We can improve CPU throughput when we reduce the number of instructions in

a program, reduce the number of cycles per instruction, or reduce the
number of nanoseconds per clock cycle. 14/17
 Memory Organization
• Computer memory consists of a linear array of addressable storage cells
that are similar to registers.

• Memory can be byte-addressable, or word-addressable, where a word

typically consists of two or more bytes.

• Memory is constructed of RAM chips, often referred to in terms of length ×

width.

• If the memory word size of the machine is 16 bits (2 bytes), then a 4M × 16

means the memory is 4M long (it has 4M = 22x220 = 222 words)

15/17
 Measures of Capacity and Speed

• Kilo- (K) = 1 thousand = 103 and 210

• Mega- (M) = 1 million = 106 and 220
• Giga- (G) = 1 billion = 109 and 230
• Tera- (T) = 1 trillion = 1012 and 240
• Peta- (P) = 1 quadrillion = 1015 and 250
• Exa- (E) = 1 quintillion = 1018 and 260
• Zetta- (Z) = 1 sextillion = 1021 and 270
• Yotta- (Y) = 1 septillion = 1024 and 280

16/17
 Memory Organization
• Physical memory usually consists of more than one RAM chip.
• Example: Suppose we have a memory consisting of 16 2K x 8 bit chips.

– Memory is 32K = 25 × 210 = 215

– 15 bits are needed for each address.
– We need 4 bits to select the chip, and
11 bits for the offset into the chip that
selects the byte.

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