Digital Circuit Design 2

10636321
Dr. Ashraf Armoush

© 2023 Dr. Ashraf Armoush

Chapter 02: Memory and

Programmable Logic

© 2023 Dr. Ashraf Armoush

 Outline
• Memory Unit
– Random Access Memory (RAM)
– Read-Only Memory (ROM)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)
• Sequential (or Simple) Programmable Logic
Device (SPLD)
• Complex Programmable Logic Devices (CPLD)
• Field Programmable Logic Array (FPGA)
© 2023 Dr. Ashraf Armoush , An-Najah National University 3

Random Access Memory (RAM)

• A memory unit stores binary information in groups of bits
called words
• Most computer memories use words that are multiples of 8
bits in length
• Communication between memory and its environment is
achieved through:
– Data input and output lines
– Address selection lines
– Control lines (direction)
• The memory unit is specified by:
– the number of words
– the number of bits in each word

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 Ex:
• A memory unit with a capacity of 1K words of 16 bits each.
 the memory can accommodate 2,048 = 2K bytes

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Write and Read Operations :

• Write
1. Apply the binary address of the
desired word to the address lines.
2. Apply the data bits that must be
stored in memory to the data input Initiate writing Latched
lines.
3. Activate the write input.

• Read
1. Apply the binary address of the
desired word to the address lines
2. Activate the read input

Note: The memory enable (sometimes Initiate reading

called the chip select) is used to
enable the particular memory chip in
a multichip implementation of a large
memory

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 Types of RAM :

• Static Random Access Memory (SRAM):

 consists of internal latches that store the binary information.
 The stored information remains valid as long as power is applied to the unit.
 SRAM is easier to use and has shorter read and write cycles
 The memory cell typically contains 6 transistors
• Dynamic Random Access Memory (DRAM)
 stores the binary information in the form of electric charges on capacitors
provided inside the chip by MOS transistors.
 The stored charge tends to discharge with time.
The capacitors must be periodically recharged by refreshing the dynamic
memory.
 DRAM offers reduced power consumption and larger storage capacity in a
single memory chip.
 A single MOS transistor and a capacitor for each DRAM cell.

© 2023 Dr. Ashraf Armoush , An-Najah National University 7

Types of RAM (Cont.):

• Synchronous Dynamic Random Access Memory (SDRAM):

 is dynamic random access memory (DRAM) that is synchronized with the
system bus.
 can run at much higher clock speeds than conventional memory.
• Double Data Rate Synchronous Dynamic Random
Access Memory (DDR SDRAM)
 transferring data on both the rising and falling edges of the clock signal.
Type Release Voltage Source I/O Bus Clock
DDR 2000 2.5 V – 2.6 V 100 – 200 MHz
DDR2 2003 1.8 V – 1.9 V 200 – 533 MHz
DDR3 2007 1.35 V – 1.5 V 400 – 1066 MHz
DDR4 2014 1.2 V – 1.4 V 800 – 1600 MHz
DDR5 2020 1.1 V 1600 – 3600 MHz

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 Types of RAM (Cont.):

• Low-Power Double Data Rate Synchronous Dynamic

Random Access Memory (LPDDR SDRAM)
 Also called mobile Double Data Rate Synchronous Dynamic Random
(mDDR)

 a type of double data rate synchronous dynamic random-access memory

that consumes less power and is targeted for some portable electronic
devices, like mobile phones, handhelds, and digital audio players

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Internal Construction:

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 Internal Construction (Cont.):

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Coincident Decoding :
K
A decoder with K inputs requires 2 AND gates with K inputs per gate

• Single decoder with K= 10

 1024 AND (with 10 inputs )

Each intersection
• 2 Decoder with K=5
represents a word
 2 * 32 = 64 AND (with 5 inputs) that may have any
number of bits.

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Address Multiplexing :

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Read Only Memory (ROM)

• ROM: a memory storage device that stores permanent binary
information.
• The stored information stays within the unit even when
power is turned off and on again (nonvolatile).

• Internally, a ROM can be implemented using a Decoder & a

number of OR gates equal to the number of outputs.

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Internal Logic of a ROM :
Fuses

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ROM Programming :
• The hardware procedure that programs the ROM blows fuse links in
accordance with a given truth table.
– 0 : No Connection (a blown fuse)
– 1 : Connection (an intact fuse)
Inputs Outputs
I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 1 0 1 1 0 1 1 0
0 0 0 0 1 0 0 0 1 1 1 0 1
0 0 0 1 0 1 1 0 0 0 1 0 1
0 0 0 1 1 1 0 1 1 - - 1 -
. .
. .
. .

1 1 1 0 0 0 0 0 0 1 0 0 1
1 1 1 0 1 1 1 1 0 0 0 1 0
1 1 1 1 0 0 1 0 0 1 0 1 0
1 1 1 1 1 0 0 1 1 0 0 1 1
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ROM Programming (Cont.) :

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Ex:
• Design a combinational circuit using a ROM to generate the square of 3-bit
input number

A2 A1 A0 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1
0 1 0 0 0 0 1 0 0
0 1 1 0 0 1 0 0 1
1 0 0 0 1 0 0 0 0
1 0 1 0 1 1 0 0 1
1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0 1
F1 F2 F3 F4 0 A0

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© 2023 Dr. Ashraf Armoush , An-Najah National University 19

Types of ROMs :
• ROM (Mask Programming): is done by the semiconductor company
during the last fabrication process of the unit.
• PROM (Programmable ROM):
– The fuses in the PROM are blown by the application of a high-voltage
pulse to the device through a special pin (Programming is irreversible).
– Special instruments are called PROM programmers.
• EPROM (Erasable PROM):
– Electrically Programmable
– Can be restructured to the initial state (erased) by using a special
ultraviolet light for a given length of time.
• EEPROM (Electrically Erasable PROM):
– Electrically Programmable.
– Electrically Erasable.
• FLASH Memory Devices:
– They are similar to the EEPROMs, but with additional built-in circuitry
to selectively program and erase the device in-circuit, without the
need for a special programmer.
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 Programmable Logic Devices (PLDs)

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Programmable Logic Array (PLA)

• Unlike the ROM, PLA does not generate all the minterms.
• The decoder is replaced by an array of AND gates that can be
programmed to generate any product term of the input
variables

– AND array : Programmable

– OR array: Programmable

• Ex1:
F1 = AB’ + AC + A’BC’
F2 = (AC + BC)’
{ 3 Inputs , 4 Product Terms (AND) , 2 outputs (OR)}

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 Ex 1 (cont.)

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Ex2:
Implement the following two Boolean functions with a PLA:
F1 (A, B, C) =  (0, 1, 2, 4)
F2 (A, B, C) =  (0, 5, 6, 7)

• Use the combination that

gives the minimum number
of product terms. (F1’ , F2)

– C: Complement output
– T: True output

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 Programmable Array Logic (PAL)

• It is a programmable logic device with:

– AND array : Programmable
– OR array: Fixed

• It is easier to program than the PLA.

• It is not as flexible as the PLA.

• Each input has a buffer-inverter gate.

• Each output is generated by a fixed OR gate.

• Product terms cannot be shared among two or more OR gates.

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Structure of a PAL :
• Commercial PAL devices
contain more gates than
the one shown in this
figure:

• One of the outputs is

connected to a buffer-
inverter gate and then fed
back into two inputs of the
AND gates.

© 2023 Dr. Ashraf Armoush , An-Najah National University 26

Ex3:
• Implement the following Boolean functions with a PAL:
w(A, B, C, D) =  (2, 12, 13)
x(A, B, C, D) =  (7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) =  (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) =  (1, 2, 8, 12, 13)

Simplifying the 4 functions to a minimum number of terms results in:

w = ABC' + A' B' CD'
x = A + BCD
y = A' B + CD + B' D'
z = ABC' + A' B' CD' + AC' D' + A' B' C' D
= w + AC' D' + A' B' C' D

© 2023 Dr. Ashraf Armoush , An-Najah National University 27

Ex3 (Cont.) : Programming Table

Product AND Inputs
Terms A B C D w Outputs
1 1 1 0 - - w = ABC’
2 0 0 1 0 - + A’B’CD’
3 - - - - -
4 1 - - - - x=A
5 - 1 1 1 - + BCD
6 - - - - -
7 0 1 - - - y = A’B
8 - - 1 1 - + CD
9 - 0 - 1 - + B’D
10 - - - - 1 z=w
11 1 - 0 0 - + AC’D’
12 0 0 0 1 - +A’B’C’D

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Ex3 (Cont.) :

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Sequential (or Simple) Programmable Logic Device

(SPLD)
• In addition to the AND-OR array, the SPLD includes flip-flops
connected to form a register.
• The circuit outputs can be taken from the OR gates or from
the outputs of the flip-flops.

• The configuration mostly used in an SPLD is the combinational

PAL together with D flip-flops (Registered PAL)

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Macrocell :
• Each section of an SPLD is called a macrocell
• It contains a sum-of-products combinational logic function and an optional
flip-flop.
• A typical SPLD has from 8 to 10 macrocells within one IC package.

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Macrocell (cont.):
• Typical programming options include:
– The ability to either use or bypass the flip-flop.

– The selection of clock edge polarity (positive or negative edge trigger)

– The selection of preset and clear for the register.

– The selection of the true value or complement of an output.

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Complex Programmable Logic Device (CPLD)
• It is a collection of individual PLDs on a single IC.
• Interconnected through a programmable switch matrix.

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Field-Programmable Gate Array (FPGA)

• A typical FPGA consists of an array of hundreds or thousands
of configurable logic blocks (CLB), surrounded by
programmable input and output (I/O) blocks and connected
together via programmable interconnections.

• FPGAs use a more flexible and faster interconnection

structure than CPLD.

[Will be covered later]

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 General Structure of an FPGA

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