EE2301 Lab Report-3

Rohith Madhani - EE23BTECH11038

Poluri Hemanth - EE23BTECH11046

Experiment:
Build a 5-bit SAR ADC
Objective:
We have to build a 5-bit SAR ADC.

Equipment Used:
• IC7474 × 12 (D-flip flop)

• Op-amp (LM358)

• 2KΩ × 6, 1KΩ × 4

• Red LED Bulbs × 5

• Breadboard × 3

Circuit Diagram:
The circuit used for the above circuit is given below.

SAR ADC
 Sample and hold circuit

The above circuit diagram shows the Sample and hold component,SAR component
and DAC component, the circuits used for them are

SAR Control logic

1kΩ 1kΩ 1kΩ 1kΩ

Vout (VDAC )

2kΩ 2kΩ 2kΩ 2kΩ 2kΩ 2kΩ

Q0 Q1 Q2 Q3 Q4

DAC
Theory:
Let’s start with the simplest circuit, the DAC, when Q0 is high at voltage V0

+V0

2kΩ
1kΩ 1kΩ 1kΩ 1kΩ
Vout (VDAC )

2kΩ 2kΩ 2kΩ 2kΩ 2kΩ

We get Vout as
V0
Vout =
16
Similariy when Q0 ,Q1 ,Q2 ,Q3 and Q4 are at high voltages of V0 , we get Vout as
 
1 1 1 1
Vout = V0 + + + +1
16 8 4 2

Depending on the output of the SAR Control logic different outputs are fed into the
comparator which then compares it the quantized and sampled signal and produces the
output to the SAR Control logic which generates a new digital output and the loop goes
on.

The sample and hold circuit works on the basis of the control signal given to it which
switches on and of based on the output of the op-amp.

Sample and hold circuit

 At the S/H control a clk signal is given. Based on the output of the first op-amp the
MOSFET turns on and off according to the Gate voltage signal. The time required for
the charge in the holding capacitor to rise up to a level that is close to the input voltage
during the sampling is called acquisition time. It needs to be as low as possible for the
above circuit to work at high accuracies.

Procedure and Working:

• Connect the circuit based on the circuit diagram given. First connect the SAR
control logic part of the circuit along with the bulbs at the output bits.

• Then connect the DAC part of the circuit along the outputs and the bulbs.

• Now connect the input side of the circuit starting with the Sample and Hold com-
ponent. Give the output of this comparator and feed the output back to the SAR
control logic.

• Now test the circuit by giving different DC inputs to capture the Digital output.

The working of the SAR ADC can be explained by the following flowchart
Working Example:
Suppose a five-bit SAR ADC. An analog voltage signal of 19 volts is applied at the input.

Vin = 19V

Initial Condition:
The operation starts by clearing all the bits in SAR. Let’s suppose Q is the output, since
it is a 5-bit ADC, the output will have five bits from Q0 to Q4. Initially, the contents in
successive approximation register (SAR) are given below:

Q = [00000]
VDAC = 0V
Vin > VDAC
Vcomp = high

Intial Condition

First Clock Cycle:

The comparator output is connected to SAR. As the comparator output goes high, the
device sets the SAR’s most significant bit to one while leaving the other bits at zero.
 First Clock Cycle

The outputs of the circuits during this clock cycle are given below.

Q = [10000]
VDAC = 16V
Vin > VDAC
Vcomp = high

Second Clock Cycle:

Again, the same procedure will be followed. This time the n-1 bit (that is, the 4th bit)
is set to 1, while all other bits remain unchanged.

Q = [11000]
VDAC = 24V
Vin < VDAC
Vcomp = low

In this clock cycle, the output of the comparator goes low. The n-1 bit is set to a low
value.

Second Clock Cycle

Third Clock Cycle:
In this clock cycle, the n-2 bit (that is, the 3rd bit) is set. while the value of the previous
n-1 bit is 0. The value of the SAR register during the third clock cycle is given below:

Q = [10100]
VDAC = 20V
Vin < VDAC
Vcomp = low

In this clock cycle, the output of the comparator goes low. The n-2 bit is set to a low
value.

Third Clock Cycle

Fourth Clock Cycle:

In this clock cycle, the n-3 bit (the second bit) is set. while the value of the previous n-2
bit is 0. The value of SAR in the third clock cycle was Q = [10100] = 20V . But this
value is greater than the input voltage. Again,n the approximation is wrong. The n-2 bit
goes low while the n-3 bit goes high.

Q = [10010]
VDAC = 18V
Vin > VDAC
Vcomp = high

In this clock cycle, the output of the comparator goes high. The n-3 bit is set to a high
value.
 Fourth Clock Cycle

Fifth Clock Cycle:

In this clock cycle, the n-4 or LSB bit is set. while the other bits remain unchanged. The
value of SAR in the fourth clock cycle was Q = [10010] = 18V. But this value is less than
the input voltage. The comparator output goes high. The least significant bit goes high.

Q = [10011]
VDAC = 19V

At the end of the conversion, the input of the DAC is equal to the output of the DAC.
We can understand how the SAR ADC works from the above example.

Fifth Clock Cycle

Conclusion:
In this report, we successfully designed and analysed the working of a Successive approx-
imation register(SAR) ADC. The above ADC can be used in communication systems
where an input analog signal needs to be converted into a digital signal. SAR ADC also
has a high accuracy compared to other ADCs. The circuit is simple compared to other
ADCs.