29/4/2010

Advancements over the years

Verilog

Prof. Abel Guilhermino

Aula X
© Intel 4004  © Intel P4 Processor

Processor  Introduced in 2000

Introduced in 1971  40 Million Transistors

2300 Transistors  1.5GHz Clock

108 KHz Clock

System Design Pyramid Introduction

Purpose of HDL:
1. Describe the circuit in algorithmic level
(like c) and in gate-level (e.g. And
gate)
2. Simulation

3. Synthesis

4. Words are better than pictures

History: Top-Down Design Approach

Need: a simple, intuitive and effective

way of describing digital circuits for
modeling, simulation and analysis.

Developed in 1984-85 by Philip
Moorby

In 1990 Cadence opened the language
to the public

Standardization of language by IEEE
in 1995

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Definition of Module Some points to remember

Interface: port and
The name of Module

parameter declaration

Body: Internal part of
Comments in Verilog
module  One line comment (// ………….)

Add-ons (optional)  Block Comment (/*…………….*/)

Description of Module (optional but

suggested)

The Module Interface Specifications of Ports

Port List

Port Declaration

Data Types Data Values

Data Values:
0,1,x,z module sample (a,b,c,d);
Numbers:
Parameters:

Wire Numbers are defined by
input a,b; number of bits parameter n=4;
- Synthesizes into wires
Value of 23: wire [n-1:0] t, d;
- Used in structural code output c,d;
5’b10111

Reg 5’d23 `define Reset_state = 0, state_B =1,
wire [7:0] b;
- May synthesize into latches, flip-flops or 5’h17 Run_state =2, finish_state = 3;
wires
Constants: if(state==`Run_state)
reg c,d;
- Used in procedural code wire [3:0] t,d;

Integer integer k;
assign t = 23;
- 32-bit integer used as indexes assign d= 4’b0111;

Input, Output, inout

- Defines ports of a module (wire by default)
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Operators Operators
reg [3:0] a, b, c, d; Reduction Operators: module sample (a, b, c, d);

Arithmetic: wire[7:0] x,y,z;


input [2:0] a, b;
*,+,-, /,% Unary operations returns single-bit values
parameter n =4; output [2;0] c, d;
• & : and

Relational • | :or
wire z,y;
<,<=,>,>=,==, != c = a + b; • ~& : nand
assign z = ~| a;

Bit-wise Operators d = a *n; • ~| : nor
c = a * b;
• ^ : xor
• Not: ~ • ~^ :xnor
If(a==b) d = 1; else d =0;
• XOR: ^ If(x==y) d = 1; else d =0;

Shift Operators d = a ~^ b;
• And : & 5’b11001 & 5’b01101 ==> 5’b01001
Shift Left: <<
• OR: | d = a ~^ b;
Shift right: >> if ((a>=b) && (z)) y=1;
• XNOR: ~^ or ^~
Concatenation Operator else y = !x;
if ((x>=y) && (z)) a=1;

Logical Operators else a = !x;
{ } (concatenation)
Returns 1or 0, treats all nonzero as 1 { n{item} } (n fold replication of an item) assign d << 2; //shift left twice

Conditional Operator assign {carry, d} = a + b;
• ! : Not
assign c = {2{carry},2{1’b0}};
• && : AND 27 && -3 ==> 1 Implements if-then-else statement
// c = {carry,carry,0,0}
• || : OR (cond) ? (result if cond true) : (result if cond false)
assign c= (inc==2)? a+1:a-1;

Examples Verilog Structure

All code are

contained in modules

Can invoke other
module exemplo ( X, Y, F, G); modules

Modules cannot be
input X;
input Y;
contained in another

Assigns are executed in parallel
output F,G; module
assign F = X & Y;
assign G = X | Y;

endmodule

Verilog Structure Structural Vs Procedural

Structural Procedural
module gate(Z,A,B,C);
input A,B,C;
textual description of
Think like C code
output Z; Z circuit

order does not matter
Order of statements are
assign Z = A|(B&C);
endmodule
important

Starts with assign
Starts with initial or
statements always statement
module two_gates(Z2,A2,B2,C2)
input A2,B2,C2;
output Z2; Z2
Harder to code
Easy to code
wire G2;
Need to work out logic
Can use case, if, for
gate gate_1(G2,A2,B2,C2); wire c, d; reg c, d;
gate gate_2(Z2,G2,A2,B2); assign c =a & b; always@ (a or b or c) begin
assign d = c |b; assign c =a & b;
endmodule
assign d = c |b; end

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Structural Vs Procedural Blocking Vs Non-Blocking

Blocking Non-blocking
Procedural Structural
<variable> <= <statement>
reg [3:0] Q; wire [3:0]Q;
<variable> = <statement>
wire [1:0] y; wire [1:0]y;
always@(y) assign
Similar to C code
The inputs are stored once
begin Q[0]=(~y[1])&(~y[0]), the procedure is triggered
Q=4’b0000; Q[1]=(~y[1])&y[0],
case(y) begin Q[2]=y[1]&(~y[0]),
The next assignment
waits until the present
Statements are executed in
2’b00: Q[0]=1; Q[3]=y[1]&y[0]; Q[0]
one is finished parallel
2’b01: Q[1]=1;
2’b10: Q[2]=1; Q[1]
2’b11: Q[3]=1;
Used for combinational
Used for flip-flops, latches
endcase logic and registers
Q[2]
end
y[0]
y[1]
Q[3] Do not mix both assignments in
one procedure

Blocking Vs Non-Blocking

Initial
begin
#1 e=2;
#1 b=1;
#1 b<=0;
e<=b; // grabbed the old b
f=e; // used old e=2, did not wait
e<=b