Question 1

If a processor clock is rated as 1.8 GHz, then its clock period is:
a) 5.55 × 10⁻⁹ sec
b) 0.55 × 10⁻¹⁰ sec
c) 55.5 × 10⁻⁹ sec
d) 5.55 × 10⁻¹⁰ sec

Question 2

_____ are numbers and encoded characters, generally used as operands.

a) Data
b) Information
c) Stored values
d) Output

Question 3

_____ is used to deal with the difference in the transfer rates between the
drive and the bus.
a) Data buffers
b) Enhancers
c) Data repeaters
d) None of them

Question 4

In memory-mapped I/O:
a) The I/O devices have a separate address space
b) A part of the memory is specifically set aside for the I/O operation
c) The I/O devices and the memory share the same address space
d) The memory and I/O devices have an associated address space

Question 5

In the CPU, what is the functionality of the control unit?

a) To transfer data to primary storage
b) To decode program instruction
c) To perform logic operations
d) To store program instruction

Question 6

The operation _________ yields true if either or both of its operands are
true.
a) OR
b) NAND
c) NOT
d) AND

Question 7

The ALU makes use of _______ to store the intermediate results.

a) Heap
b) Accumulators
c) Registers
d) Stack

Question 8

The ______ plays a very vital role in the case of super-scalar processors.
a) Compilers
b) Peripherals
c) Memory
d) Motherboard

Question 9

________ is used in scalar RISC processors to improve the performance of

instructions that require multiple cycles.
a) Out-of-order completion
b) In-order issue
c) In-order completion
d) Out-of-order issue

Question 10

In a system that has 32 registers, the register ID is __________ long.

a) 16 bits
b) 8 bits
c) 5 bits
d) 6 bits

Question 11

The utility program used to bring the object code into memory for
execution is ______
a. Extractor
b. Linker
c. Loader
d. Fetcher

Question 12

The commitment unit uses a queue called ______

a. None of them
b. Record buffer
c. Commitment buffer
d. Storage buffer

Question 13

Question: The time lost due to the branch instruction is often referred to
as ____________
a. Branch penalty
b. Delay
c. Latency
d. None of them

Question 14

Question: Individual blocks or records have a unique address based on

physical location with __________.
a. Sequential access
b. Physical access
c. Direct access
d. Associative

Question 15

Question: When dealing with the branching code, the assembler

___________
a. Replaces the target with the value specified by the DATAWORD directive
b. Does not replace until the test condition is satisfied
c. Finds the branch offset and replaces the branch target with it
d. Replaces the target with its address

Question 16

Question: For a given FINITE number of instructions to be executed, which

processor architecture provides faster execution?
a. All of them
b. Super-scalar
c. ISA
d. ANSA

Question 17

Question: When the processor executes multiple instructions at a time, it

is said to use _______
a. Multiple issues
b. Single issue
c. Multiplicity
d. Visualization
Question 18

Question: The directive used to perform initialization before the execution

of the code is ______
a. Store
b. Reserve
c. Dataword
d. EQU

Question 19

Question: The _________ contains logic for performing a communication

function between the peripheral and the bus.
a. I/O channel
b. I/O command
c. I/O module
d. I/O processor

Question 20

Question: _________ is where individual instructions are executed through a

pipeline of stages so that while one instruction is executing in one stage of
the pipeline, another instruction is executing in another stage.
a. Scalar
b. Simultaneous multithreading
c. Superscalar
d. Pipelining

Question 21

The small, extremely fast RAMs are called _____?

a) Cache
b) Heaps
c) Registers
d) Stack

Question 22

ISP stands for _________.

a) Interrupt Service Procedure
b) Information Standard Processing
c) Interchange Standard Protocol
d) Instruction Set Processor

Question 23

The transmission on the asynchronous BUS is also called _____.

a) Hand-Shake transmission
b) Switch mode transmission
c) Variable transfer
d) Bulk transfer

Question 24

CISC stands for ___________.

a) Computer Indexed Set Components
b) Complete Instruction Set Compliment
c) Complex Instruction Set Computer
d) Computer Instruction Set Compliment

Question 25

The ________ consists of the access time plus any additional time required
before a second access can commence.
a) Memory cycle time
b) Transfer rate
c) Latency
d) Direct access

Question 26

The time lost due to the branch instruction is often referred to as

____________.
a) None of them
b) Branch penalty
c) Latency
d) Delay

Question 27

What is the maximum addressable memory of a 32-bit microprocessor

with a 24-bit address?
a) 16 Mbits
b) 16 Gbits
c) 16 MB
d) 16 GB

Question 28

The stalling of the processor due to the unavailability of the instructions is

called ___________.
a) None of them
b) Structural hazard
c) Input hazard
d) Control hazard

Question 29
The step where the results stored in the temporary register are transferred
into the permanent register is called ______.
a) Inception step
b) Last step
c) Final step
d) Commitment step

Question 30

A _________ is an actual location in main memory.

a) Physical address
b) Partition address
c) Base address
d) Logical address

Question 31

A processor performing fetch or decoding of different instructions during

the execution of another instruction is called _____.
a) Sequencing
b) Parallel Computation
c) Super-scaling
d) Pipe-lining

Question 32

Which of the following RAID levels refers to memory-style ECC

organization?
a) 1
b) 3
c) 4
d) 2

Question 33

If a processor clock is rated as 3 GHz, then its clock period is _____.

a) 3.00 × 10⁻¹⁰ sec
b) 0.33 × 10⁻¹⁰ sec
c) 0.33 × 10⁻⁹ sec
d) 3.00 × 10⁻⁹ sec

Question 34

While using the iterative construct (Branching) in execution, _____________

instruction is used to check the condition.
a) None of them
b) TestCondn
c) Branch
d) TestAndSet

Question 35

A loop that iterates over an array of data can be split into a number of
smaller parallel loops in individual threads that can be scheduled in
parallel when using ________ threading.
a) Hybrid
b) Fine-grained
c) Multi-process
d) Coarse

Question 36

The assembler stores the object code in ______.

a) RAM
b) Magnetic disk
c) Cache
d) Main memory

Question 37

The address of the instruction following the CALL instruction is stored in

_____.
a) Stack
b) Static memory
c) Program counter
d) Heap

Question 38

"Memory is organized into records and access must be made in a specific

linear sequence" is a description of __________.
a) Associative
b) Random access
c) Sequential access
d) Direct access

Question 39

The reason for the implementation of cache memory is ________.

a) To reduce memory access and cycle time
b) The difference in speeds of operation of the processor and
memory
c) To increase the internal memory of the system
d) All of them

Question 40
Which of the following storage types may have an associative access
method?
a) Virtual memory
b) Main memory
c) Cache
d) Disks

Question 41

The approach where the memory contents are transferred directly to the
processor from the memory is called ______.
a) Read-later
b) None of them
c) Read-through
d) Early-start

Question 42

The amount of time required to read a block of data from a disk into
memory is composed of seek time, rotational latency, and transfer time.
Rotational latency refers to:
a) The time it takes for the read-write head to move into position over the
appropriate track
b) The time it takes for the platter to make a full rotation
c) None of them
d) The time it takes for the platter to rotate the correct sector
under the head

Question 43

Out of the following, which is not a CISC machine?

a) Intel 80486
b) IBM 370/168
c) VAX 11/780
d) Motorola A567

Question 44

The method of accessing the I/O devices by repeatedly checking the

status flags is ___________.
a) None of them
b) I/O mapped
c) Program-controlled I/O
d) Memory-mapped I/O

Question 45
The advantage of I/O mapped devices over memory-mapped is
___________.
a) The devices connected using I/O mapping have a bigger buffer space
b) The former offers faster transfer of data
c) No advantage as such
d) The devices have to deal with fewer address lines

Question 46

The purpose of the ORIGIN directive is ___________.

a) To list the locations of all the registers used
b) To indicate the starting of the computation code
c) To indicate the starting position in memory where the program
block is to be stored
d) To indicate the purpose of the code

Question 47

The average number of steps taken to execute the set of instructions can
be made to be less than one by following _______.
a) Sequential
b) Pipe-lining
c) ISA
d) Super-scaling

Question 48

The registers and ALU are connected by using _____.

a) Control path
b) Data path
c) Information path
d) Process route

Question 49

The computer architecture aimed at reducing the time of execution of

instructions is ________.
a) ISA
b) ANNA
c) RISC
d) CISC

Question 50

When using Branching, the usual sequencing of the PC is altered. A new

instruction is loaded which is called a ______.
a) Forward target
b) Loop target
c) Branch target
d) Jump instruction

Question 51

The iconic feature of the RISC machine among the following is _______.
a) Having a branch delay slot
b) All of them
c) Reduced number of addressing modes
d) Increased memory size

Question 52

The condition flag Z is set to 1 to indicate _______.

a) There is no empty register available
b) The operation has resulted in an error
c) The operation requires an interrupt call
d) The result is zero

Question 53

________ is when the processor spends most of its time swapping pages
rather than executing instructions.
a) Thrashing
b) Multitasking
c) Paging
d) Swapping

Question 54

The binary representation of -7 is _____.

a) 1101
b) 0111
c) 1001
d) 1011

Question 55

A __________ contains a permanent pattern of data that cannot be

changed, is nonvolatile, and cannot have new data written into it.
a) RAM
b) SRAM
c) Flash memory
d) ROM

Question 56

The main virtue of using a single bus structure is ____________.

a) Cost-effective connectivity and speed
b) Cost-effective connectivity and ease of attaching peripheral devices
c) Fast data transfers
d) None of them

Question 57

________ indicates whether this micro-op is scheduled for execution, has

been dispatched for execution, or has completed execution and is ready
for retirement.
a) State
b) Micro-op
c) Alias register
d) Memory address

Question 58

When we perform subtraction on -7 and -5, the answer in 2’s complement

form is ________.
a) 11110
b) 1110
c) 0010
d) 1010

Question 59

Lotus Domino or Siebel CRM are examples of ___________ applications.

a) Multi-process
b) Multi-instance
c) Java
d) Threaded

Question 60

The time delay between two successive initiations of memory operation is

called _______.
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay

Question 61

An interface that provides a method for transferring binary information

between internal storage and external devices is called _______.
a) I/O interface
b) I/O bus
c) Output interface
d) Input interface
Question 62

_____ is the binary representation of -1:

a) 00001111
b) 11110000
c) 11111111
d) 00000000

Question 63

The method of accessing the I/O devices by repeatedly checking the

status flags is _______.
a) I/O mapped
b) Programmed I/O
c) None of them
d) Memory-mapped I/O

Question 64

The situation where the second instruction needs data produced by the
first instruction to execute is referred to as _______.
a) Procedural dependency
b) Output dependency
c) Antidependency
d) True data dependency

Question 65

The temporal aspect of the locality of reference means _______.

a) That the recently executed instruction is temporarily not referenced
b) That the recently executed instruction will be executed soon
again
c) None of them
d) That the recently executed instruction won’t be executed soon

Question 66

The processor may perform some arithmetic or logic operation on data is

called _______.
a) Control
b) Data processing
c) Processor
d) Data transferring

Question 67

________ register keeps track of the instructions stored in the program

stored in memory.
a) PC (Program Counter)
b) XR (Index Register)
c) AR (Address Register)
d) AC (Accumulator)

Question 68

Instead of the first instruction producing a value that the second

instruction uses, with ___________ the second instruction destroys a value
that the first instruction uses.
a) In-order issue
b) Resource conflict
c) Antidependency
d) Out-of-order completion

Question 69

When we perform subtraction on -7 and 1, the answer in 2’s complement

form is _______.
a) 0110
b) 1010
c) 1110
d) 1000

Question 70

The Instruction fetch phase ends with _______.

a) Decoding the data in MDR and placing it in IR
b) Placing the data from the address in MAR into MDR
c) Placing the address of the data into MAR
d) Completing the execution of the data and placing its storage address
into MAR

Question 71

Which of the register(s) of the processor is/are connected to the Memory

Bus?
a) IR
b) Both PC and MAR
c) PC
d) MAR

Question 72

The technique which moves the program blocks to or from the physical
memory is called _______.
a) Framing
b) Overlays
c) Virtual memory organization
d) Paging

Question 73

__________ refers to whether memory is internal or external to the

computer.
a) Hierarchy
b) Tag
c) Access
d) Location

Question 74

The essence of the __________ approach is the ability to execute

instructions independently and concurrently in different pipelines.
a) Scalar
b) Flow dependency
c) Branch
d) Superscalar

Question 75

When performing a looping operation, the instruction gets stored in the

__________.
a) System stack
b) System Heap
c) Registers
d) Cache

Question 76

CISC stands for ___________.

a) Complex Instruction Set Computer
b) Complete Instruction Set Complement
c) Computer Indexed Set Components
d) Computer Instruction Set Complement

Question 77

The usual BUS structure used to connect the I/O devices is ___________.
a) Single BUS structure
b) Multiple BUS structure
c) Star BUS structure
d) Node to Node BUS structure

Question 78
_____ is not one of the four basic functions of a computer.
a) Data movement
b) Data processing
c) Data storage
d) I/O processing

Question 79

The unary operation _________ inverts the value of its operand.

a) NAND
b) NOT
c) OR
d) XOR

Question 80

Two processors A and B have clock frequencies of 700 MHz and 900 MHz,
respectively. Suppose A can execute an instruction in an average of 3
steps, and B can execute in an average of 5 steps.
For the execution of the same instruction, which processor is faster?
a) A
b) B
c) A and B take the same time
d) Insufficient information

Question 81

The assembler stores all the names and their corresponding values in
______.
a) Special purpose Register
b) Symbol Table
c) Value Map Set
d) None of them

Question 82

The bit used to signify that the cache location is updated is ________.
a) Update bit
b) Flag bit
c) Dirty bit
d) Reference bit

Question 83

An optimizing compiler does _________.

a) Better memory management
b) Takes advantage of the type of processor and reduces its
process time
c) Better compilation of the given piece of code
d) None of them

Question 84

Any condition that causes a processor to stall is called _________.

a) None of them
b) Page fault
c) System error
d) Hazard

Question 85

When using the __________ technique, all write operations made to main
memory are also made to the cache.
a) Write-through
b) LRU
c) Unified cache
d) Write-back

Question 86

The problem where process concurrency becomes an issue is called

___________.
a) Banker's problem
b) Bakery problem
c) Philosopher's problem
d) Reader-writer problem

Question 87

To overcome the lag in the operating speeds of the I/O device and the
processor, we use ___________.
a) Interrupt signals
b) Exceptions
c) Buffer spaces
d) Status flags

Question 88

The binary value of the ASCII letter "c" is 01100011. Its decimal value is
_______.
a) 99
b) 45
c) 123
d) 100

Question 89
A special unit used to govern the out-of-order execution of instructions is
called ______.
a) Supervisory unit
b) Temporal unit
c) Commitment unit
d) Monitor

Question 90

The third generation of computers was based on _____.

a) Vacuum tubes
b) VLSI
c) IC
d) Transistors

Question 91

_________ is determined by the number of instructions that can be fetched

and executed simultaneously and by the speed and sophistication of
mechanisms the processor uses to find independent instructions.
a) Output dependency
b) Procedural dependency
c) Machine parallelism
d) Instruction-level parallelism

Question 92

The binary representation of -15 is _____.

a) 11110001
b) 10000000
c) 01000000
d) 00100000

Question 93

The meter in and out lines are used for __________.

a) Monitoring the amount of data transferred
b) Monitoring the usage of devices
c) None of them
d) Measuring CPU usage

Question 94

The algorithm followed in most systems to perform out-of-order execution

is __________.
a) Tomasulo algorithm
b) Score carding
c) None of them
d) Reader-writer algorithm

Question 95

Data are transferred to and from the disk in __________.

a) Sectors
b) Tracks
c) Gaps
d) Pits

Question 96

RAID level _________ has the highest disk overhead of all RAID types.
a) 0
b) 3
c) 1
d) 5

Question 97

The input devices can send information to the processor when:

a) When the SIN status flag is set
b) None of them
c) When the data arrives regardless of the SIN flag
d) All of them

Question 98

A computer that is advertised as having 96K bytes of DRAM memory and a

2.1 Gigabyte hard drive has:
a) 96K bytes of cache, 2.1 Gigabytes of primary memory
b) 2.1 Gigabytes of auxiliary memory, 96 K bytes of primary memory and
96 bytes of cache
c) 2.1 Gigabytes of auxiliary memory and 96 K bytes of primary
memory
d) 96K bytes of secondary memory and 2.1 Gigabytes of primary memory

Question 99

Two processors A and B have clock frequencies of 2.2 GHz and 2.3 GHz,
respectively. Suppose A can execute an instruction in an average of 4
steps and B can execute an instruction in an average of 5 steps. For the
execution of the same instruction, which processor is faster?
a) Insufficient information
b) A
c) B
d) Both A and B take the same time
Question 100

The superscalar approach can be used on __________ architecture.

a) Both RISC and CISC
b) Neither RISC nor CISC
c) CISC
d) RISC

Question 101

A source program is usually in _______

a. High-level language

b. Machine level language

c. Assembly language

d. Natural language

Question 102

If a magnetic disc drive has 100 cylinders, each containing 10 tracks of 10

sectors, and each sector can contain 128 bytes, what is the maximum
capacity of the disc drive in KB?

a.1,250

b.1,280

c.160,000

d.1,280,000

Question 103

The first computer constructed using vaccum tubes was _____

a.EDVAC

b.EDIAC

c.IBM PC

d.ENIAC

Question 104

The second generation of computers based on _____

a.Vacuum tubes

b.VLSI

c.IC

d.Transistors

Question 105

When using the Big Endian assignment to store a number, the sign bit of
the number is stored in _____

a.The higher order byte of the word

b.None of them

c.The lower order byte of the word

d.Can’t say

Question 106

The instructions following a branch have a _________ on the branch and

cannot be executed until the branch is executed.

a.procedural dependency

b.resource dependency

c.true data dependency

d.output dependency

Question 107

According to the specifications of a particular hard disk, a seek time takes

0.3 milliseconds between adjacent tracks. If the disk has 100 cylinders
how long will it take for the head to move from the innermost cylinder to
the outermost cylinder.

a.300 microseconds

b.0.3 seconds

c.30 milliseconds

d.3000 microseconds
Question 108

One distinguishing characteristic of memory that is designated as

_________ is that it is possible to both to read data from the memory and to
write new data into the memory easily and rapidly.

a.EEPROM

b.ROM

c.EPROM

d.RAM

Question 109

The processing required for a single instruction is called an _____

a.Instruction processing

b.Memory instruction

c.Memory cycle

d.Instruction cycle

Question 110

Which of the following is the RAID level distributes parity and data across
all the disks?

a.3

b.6

c.5

d.4

Question 111

The system is notified of a read or write operation by ___________

a.Enabling the read or write bits of the devices

b.Raising an appropriate interrupt signal

c.Appending an extra bit of the address

d.Sending a special signal along the BUS

Question 112

For random-access memory, __________ is the time from the instant that an
address is presented to the memory to the instant that data have been
stored or made available for use.

a.Transfer rate

b.Direct access

c.Access time

d.Memory cycle time

Question 113

The I/O function includes a _________ requirement to coordinate the flow of

traffic between internal resources and external devices.

a.status reporting

b.data

c.cycle

d.control and timing

Question 114

The algorithm to remove and place new contents into the cache is called
_______

a.Updation

b.Renewal algorithm

c.None of them

d.Replacement algorithm

Question 115

The binary address issued to data or instructions are called as ______

a.Physical address
b.Logical address

c.Location

d.Relocatable address

Question 116

What is the function of MBR?

a.Specify an address of memory

b.Read a word from memory

c.Store address of the next instruction

d.Contains the 8 bit opcode

Question 117

Oracle database, SAP, and PeopleSoft are examples of ________

applications.

a.multi-instance

b.multithreaded native

c.Java

d.multi-process

Question 118

Q10. Which of the architecture saves memory?

a.Harvard & Von Neumann

b.None of them

c.Harvard

d.Von Neumann

Question 119

__________ exists when instructions in a sequence are independent and

thus can be executed in parallel by overlapping.

a.Flow dependency
b.Instruction-level parallelism

c.Machine parallelism

d.Instruction issue

Question 120

The contention for the usage of a hardware device is called ______

a.Stalk

b.None of them

c.Structural hazard

d.Deadlock

Question 121

The Sun micro systems processors usually follow _____ architecture.

a.CISC

b.ISA

c.ULTRA SPARC

d.RISC

Question 122:

The problem where process concurrency becomes an issue is called as

___________

a. Bakery problem

b. Bankers problem

c. Reader-writer problem

d. Philosophers problem

Question 123:

The spatial aspect of the locality of reference means ________

a. That the instruction executed will be executed at a later time

b. That the instruction in close proximity of the instruction

executed will be executed in future

c. That the recently executed instruction is executed again next

d. That the recently executed won’t be executed again

Question 124:

________ is a protocol used to issue instructions.

a. Micro-ops

b. Scalar

c. Instruction issue policy

d. SIMD

Question 125:

The program is divided into operable parts called as _________

a. Frames

b. Pages

c. Segments

d. Sheets

Question 126:

Adjacent tracks are separated by _________.

a. sectors

b. heads

c. pits

d. gaps

Question 127:

Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch
prediction strategy based on the history of recent executions of branch
instructions.

a. Pentium

b. Pentium 4

c. Pentium Pro

d. 486

Question 128:

Q30. The registers, ALU and the interconnection between them are
collectively called as _____
a. data

b. process route

c. information path

d. information trail

Question 129:

The contention for the usage of a hardware device is called ______

a. Deadlock

b. Stalk

c. Structural hazard

d. None of them

Question 130:

A computer's memory is composed of 4K words of 64 bits each. How many

total bits in memory?

a. 131072

b. 262144

c. 256000

d. 128000

Question 131

I/O addressing methods:

a. None of them
b. Isolated I/O
c. Both memory-mapped I/O and isolated I/O
d. Memory-mapped I/O

Question 132

The ............. is the minimum storage unit of a hard drive.

a. Sector
b. Cluster
c. Cylinder
d. Track

Question 133
_____ directive specifies the end of execution of a program.
a. Stop
b. Terminate
c. End
d. Return

Question 134

With _______, register banks are replicated so that multiple

threads can share the use of pipeline resources.
a. Pipelining
b. Superscalar
c. SMT
d. Scalar

Question 135

Which of the architecture is power efficient?

a. CISC
b. ISA
c. IANA
d. RISC

Question 136

__________ is the simplest mapping technique and maps each block

of main memory into only one possible cache line.
a. Associative mapping
b. Set associative mapping
c. None of them
d. Direct mapping

Question 137

Since it uses the out-of-order mode of execution, the results are

stored in ______
a. TLB
b. Temporary registers
c. Buffers
d. Special memory locations
Question 138

The register used to store the flags is called as _________

a. Log register
b. Status register
c. Flag register
d. Test register

Question 139

SDRAM stands for _____

a. Synchronous dynamic random access memory
b. Syndrome dynamic random access memory
c. System dynamic random access memory
d. Static dynamic random access memory

Question 140

The master indicates that the address is loaded onto the BUS, by
activating _____ signal.
a. MSYN
b. WMFC
c. INTR
d. SSYN

Question 141

Hardwired Control
________ are the different type/s of generating control signals.
a. Both Micro-programmed and Hardwired
b. Micro-programmed
c. Both Hardwired and Micro-instruction
d. Micro-instruction

Question 142

One way to control power density is to use more of the chip area
for ________.
a. Cache memory
b. Multicore
c. Resistors
d. Silicon
Question 143

In memory-mapped I/O ____________

a. A part of the memory is specifically set aside for the I/O operation
b. The I/O devices and the memory share the same address space
c. The I/O devices have a separate address space
d. The memory and I/O devices have an associated address space

Question 144

The 8-bit encoding format used to store data in a computer is

______
a. ANCI
b. ASCII
c. UNICODE
d. EBCDIC

Question 145

How many possible values can we have with 8 bits?

a. 127
b. 256
c. 8
d. 1 byte

Question 146

Which of the following is the RAID level with no redundancy?

a. 2
b. 0
c. 1
d. 3

Question 147

Which of these is a valid byte?

a. 10022011
b. AA-AA-BB-BB
c. 11011011
d. 00-11-FF-F
Question 148

Can you perform an addition on three operands simultaneously in

ALU using the Add instruction?
a. Yes
b. Not permitted
c. Not possible using Add, we’ve to use AddSetCC
d. None of them

Question 149

__________ converts the programs written in assembly language

into machine instructions.
a. Assembler
b. Interpreter
c. Converter
d. Machine compiler

Question 150

The virtual memory basically stores the next segment of data to

be executed on the _________
a. RAM
b. Disks
c. Secondary storage
d. ROM

Question 151

During the execution of the instructions, a copy of the

instructions is placed in the _____
a. Register
b. RAM
c. HDD
d. Cache

Question 152

The MSYN signal is initiated __________

a. Soon after the decoding of the address
b. Soon after the address and commands are loaded
c. After the slave gets the commands
d. None of them

Question 153

The ISA standard buses are used to connect ___________

a. CD/DVD drives and Processor
b. GPU and Processor
c. Hard disk and Processor
d. RAM and Processor

Question 154

If a system is a 32-bit machine, then the length of each word will

be .......................
a. 16 bytes
b. 8 bytes
c. 4 bytes
d. 12 bytes

Question 155

RTN stands for ___________

a. Register Transfer Notation
b. Regular Transmission Notation
c. Register Transmission Notation
d. Regular Transfer Notation

Question 156

Both the CISC and RISC architectures have been developed to

reduce the ______
a. Cost
b. Semantic gap
c. All of them
d. Time delay

Question 157

The effectiveness of the cache memory is based on the property

of ________
a. Memory size
b. Locality of reference
c. Memory localization
d. None of them

Question 158

Using a direct mapping method for a memory of 32 blocks and a

cache of 4 lines, how many bits are used for the tag field?
a. 3
b. 4
c. 2
d. 5

Question 159

____________ method is used in centralized systems to perform out-

of-order execution.
a. Scoreboarding
b. Optimizing
c. Scorecard
d. Redundancy

Question 160

The ______ format is usually used to store data.

a. Decimal
b. Octal
c. Hexadecimal
d. All of them

Question 161

Processors are called ________.

a. Cores
b. Interconnects
c. Dies
d. QPI

Question 162
The control unit controls other units by generating ___________
a. Command Signals
b. Timing Signals
c. Transfer Signals
d. Control Signals

Question 163

The ________ is responsible for maintaining coherency among L1

data caches.
a. Distributed Interrupt Controller
b. Watchdog
c. Snoop Control Unit (SCU)
d. VFP Unit

Question 164

Which representation is most efficient to perform arithmetic

operations on the numbers?
a. 1’s Complement
b. 2’s Complement
c. None of them
d. Sign-Magnitude

Question 165

The situation wherein the data of operands are not available is

called ______
a. Stock
b. Structural Hazard
c. Deadlock
d. Data Hazard

Question 166

To reduce the memory access time, we generally make use of

______
a. Heaps
b. Higher Capacity RAM’s
c. SDRAM’s
d. Cache’s
Question 167

The OS maintains a __________ for each process that shows the

frame location for each page of the process.
a. Page Table
b. Kernel
c. Logical Address
d. TLB

Question 168

The associatively mapped virtual memory makes use of _______

a. TLB
b. Page Table
c. Frame Table
d. None of them

Question 169

RAID level 1+0 is used because RAID level 1

provides .......... ...whereas RAID level 0 provides ....................
a. Performance, Redundancy
b. Redundancy, Performance
c. Performance, Reliability
d. Reliability, Performance

Question 170

The alternate way of writing the instruction, ADD #5,R1 is ______

a. There is no other way
b. ADDI 5,R1;
c. ADD [5],[R1];
d. ADDIME 5,[R1];

Question 171

_____ directive is used to specify and assign the memory required

for the block of code.
a. Reserve
b. Assign
c. Set
d. Allocate
Question 172

A _______ is an electronic circuit that produces an output signal

that is a simple Boolean operation on its input signals.
a. Flip-flop
b. Decoder
c. Gate
d. Counter

Question 173

Which memory device is generally made of semiconductors?

a. CDROM
b. RAM
c. Floppy disk
d. DVD

Question 174

Which method/s of representation of numbers occupies a large

amount of memory than others?
a. 1’s & 2’s complement
b. Sign-magnitude
c. 1’s complement
d. 2’s complement

Question 175

An interface that provides I/O transfer of data directly to or from

the memory unit and peripheral is termed as ........
a. DDA
b. Serial interface
c. BR
d. DMA

Question 176

__________ is used to implement virtual memory organisation.

a. None of them
b. MMU
c. Page table
d. Frame table

Question 177

The instructions like MOV or ADD are called as ______

a. OP-Code
b. Operators
c. Commands
d. None of them

Question 178

Which registers can interact with the secondary storage?

a. R1
b. PC
c. MAR
d. IR

Question 179

The periods of time when the unit is idle is called as ________

a. Hazards
b. Both Stalls and Bubbles
c. Stalls
d. Both Bubbles and Hazards

Question 180

The ________ connects to the external bus, known as the Front Side
Bus, which connects to main memory, I/O controllers, and other
processor chips.
a. Bus interface
b. All of them
c. L2
d. APIC

Question 181

The Intel Core i7-990X, introduced in 2008, implements ______ x86

SMT processors, each with a dedicated L2 cache, and with a
shared L3 cache.
a. 2
b. 8
c. 4
d. 6

Question 182

RAID splits file(s) into many segments, and sends the segments
to several disks. Files that have been segmented in this way are
called:
a. Striped Data
b. Striped File
c. None of them
d. Striped Array

Question 183

A complete microcomputer system consists of _____

a. Microprocessor
b. Peripheral equipment
c. All of them
d. Memory

Question 184

The process wherein the processor constantly checks the status

flags is called as ___________
a. Reviewing
b. Polling
c. Inspection
d. Echoing

Question 185

A portion of main memory used as a buffer to hold data

temporarily that is to be read out to disk is referred to as a
_________.
a. Miss
b. Latency
c. Virtual address
d. Disk cache
Question 186

The.............. process divides the disk into sectors and tracks.

a. Initiation
b. Formatting
c. Creation
d. Modification

Question 187

The method of synchronising the processor with the I/O device in

which the device sends a signal when it is ready is?
a. Interrupts
b. DMA
c. Exceptions
d. Signal handling

Question 188

____________ method is used in centralized systems to perform out-

of-order execution.
a. Scorecard
b. Score boarding
c. Optimizing
d. Redundancy

Question 189

________ refers to the process of initiating instruction execution in

the processor's functional units.
a. Instruction issue
b. Procedural issue
c. In-order issue
d. Out-of-order issue

Question 190

The situation wherein the data of operands are not available is

called ______
a. Stock
b. Data hazard
c. Deadlock
d. Structural hazard

Question 191

For internal memory, the __________ is equal to the number of

electrical lines into and out of the memory module.
a. Unit of transfer
b. Memory ratio
c. Access time
d. Capacity

Question 192

To overcome the problems of the assembler in dealing with

branching code, we use _____
a. Interpreter
b. Two-pass assembler
c. Op-Assembler
d. Debugger

Question 193

The instructions like MOV or ADD are called as ______

a. Operators
b. OP-Code
c. None of them
d. Commands

Question 194

The ________ introduced a full-blown superscalar design with out-

of-order execution.
a. Pentium
b. Pentium Pro
c. 486
d. 386

Question 195
The processor keeps track of the results of its operations using
flags called ________
a. Test output flags
b. Conditional code flags
c. None of them
d. Type flags

Question 196

Where does the CPU store its computations?

a. Processor
b. Registers
c. Binary
d. External Data Bus

Question 197

The BUS that allows I/O, memory, and Processor to coexist is

_______
a. Attributed BUS
b. Backplane BUS
c. External BUS
d. Processor BUS

Question 198

The method of placing the heads and the discs in an airtight

environment is called as ........
a. Winchester technology
b. RAID Arrays
c. Fleming reduction
d. ATP tech

Question 199

The method of synchronising the processor with the I/O device in

which the device sends a signal when it is ready is ...
a. Signal handling
b. Exceptions
c. DMA
d. Interrupt-driven I/O
Question 200

Facilities and services provided by the OS that assist the

programmer in creating programs are in the form of _________
programs that are not actually part of the OS but are accessible
through the OS.
a. Multitasking
b. JCL
c. Logical address
d. Utility