University of Babylon

College of Engineering
Electrical Department

Sequential Circuits with

Programmable Logic Devices

Presented by :
Noora Subhi Noor Raheem

Supervised by :
Dr. Ehab A. Alhialy
 CONTENTS :
• Registered Programmable Logic Devices.
• Field-Programmable Logic Sequencers.
• PLS105.
• PLS155.
• Registered PALS.
• PAL16R6.
• PLDS with Programmable Logic Macrocells.
• PAL22V1O.
• EP910.
• Sequential Circuit Design and PLD Device Selection
• PLD Design Examples.
 Registered Programmable Logic Devices
❖ The basic model of a sequential circuit is that of
Fig.1
 Registered Programmable Logic Devices

❖The general structure of a registered PLD is shown in Fig..2

❖ a registered PLD contains a programmable AND array whose outputs feed an OR array.
❖ Each output of the OR array drives either an external output pin, in which case it is referred to
as a combinational output, or an excitation input of a flip-flop.
❖ Flip-flop outputs may be connected to external pins, in. which case the pins are referred to as
registered outputs, or else the flip-flop outputs may be fed back to the AND array without being
connected to external pins, in which case they are referred to as buried registers.
❖Both combinational and registered outputs may likewise be fed back to the AND array. These
different configurations are illustrated in Fig.3.
Figure.2 General structure of a registered PLD. Figure.3 Registered PLD output options.
❖Mealy models can be implemented with registered PLDs as shown in Fig.4a, by using
combinational outputs for the output functions and flip-flops to store the state variables.
❖ Since the state variables need not be visible at the outputs either buried registers or registered
outputs with feedback can be used.
❖Moore models require that the state flip flops drive the external outputs, as shown in Fig .4b,
and thus registered outputs with feedback are needed .
 Field-Programmable Logic Sequencers

❖The field - programmable logic sequencer (FPLS) is one of the oldest programmable logic
elements developed to support sequential logic circuit implementation. A typical FPLS device is
organized around a field-programmable logic array (FPLA).
❖An FPLA contains a programmable AND array whose outputs feed a programmable OR array,
as shown in Fig. 4.
❖ In an FPLS, the OR array outputs drive either flip-flop excitation inputs or combinational
outputs. The outputs of the flip-flops are normally fed back to the AND arrays allowing state
variables to be realized.
• Table .1 lists several FPLS devices available from Philips[1] which are
• typical of the devices available from various manufacturers. We will examine two of these in
detail,
• the PLS 105, which contains SR flip-flops, and
• the PLS 155, which contains user-configurable flip-flops .

Table (1 ) Signetics Fpls Devices “1”

 ➢ PLS 105
▪ The PLS 105 FPLS device [1] was one of the first FPLS devices commercially available and is
based on the PLS100 FPLA device. As shown in Fig.5
▪ The PLS 105 contains 14 SR flip-flops.
▪ The outputs of eight of the flip-flops are connected to external output pins and are not fed
back to the AND array, So they are not suitable for implementing state variables.
▪ These flip-flops would be used to create an output register. The outputs of the remaining six
flip-flops, P5 to P0 are fed back to the AND array, but are not connected to external output pins.
▪ In this configuration, the latter six flip-flops are referred to as buried registers, since they are
contained within the chip without their outputs being directly accessible, Thus, sequential
machines with up to six state variables and eight outputs may be realized with a single PLS 105.
▪ All 14 of the flip-flops on the PLS 105 are driven by a common clock input pin, CK,.
Figure (5)
 ➢ PLS 105
• The overall organization of the PLS105 is 16 x48 x 8 with 16 dedicated inputs I15 to I0 ,8
outputs .F7 to F0, and 48 product terms generated in the AND array.
• The OR array of the PLA portion of the device has 29 outputs; 28 drive the S and R excitation
inputs of the 14 flip- fIops ,
• and one complemented SOP expression, C, is produced and fed back to the AND array along
with the six flip-flop outputs P5 to P0.
 ➢ PLS 155
• contains four registered outputs, F0 – F3 , and eight combinational outputs, B0 to B7.
• All 12 of these signals are fed back as inputs to the AND array .
• The flip-flops of the PLS 155 are flexible in that they can be programmed to operate as either
JK ,T or D flip - flops.
• data sheet for the PLSI55 [1] lists its organization as 16 x 45 x 12, indicating that there are 16
inputs, 45 product terms, and 12 outputs. Examination of Fig. 7 .
• The foldback buffer , controlled by determines the actual mode of operation. If the buffer
is disabled by = 1, it acts as an open circuit, making the inputs to the flip-
flop independent, as illustrated in Fig. 9a.If the buffer is enabled by = 0, as illustrated in
Fig. 9b, the input becomes equal to the complement of the input.
 ➢ Registered PALS
• Many PAL devices are members of families that utilize a single basic PAL
structure but have different output architectures. The most common output
architectures are summarized in Table.2
• Ex : PAL I6R6 has a total of 16 inputs and 6 registered outputs
❖Table .3 lists several commonly used registered PALS and their configurations.
 ➢ PAL 16R6
• It contains eight dedicated input pins, I8 to I1 As shown in Fig. 10 ,and eight output pins, of
which two are combinational (I/0 8 and I/01) ,and six are registered (07 to 02).
• Each registered output pin is driven by a D flip-flop whose outputs and their complements are
fed back to the AND array.
• The combinational outputs are likewise fed Back, making a total of 32 inputs to the AND array.
• Each D flip-flop excitation input is driven by one of the eight PAL SOP outputs .
• Hence, the PAL has a total of 32 inputs and 8 outputs.
 ➢ PAL 16R6
• All six flip-flops are controlled by a single clock input pin CLK, All eight output pins. are
driven by tri state drivers that are controlled by the single OE control pin.
➢ PLDS with Programmable Logic Macrocells

❖A Macrocell is a logic circuit associated with an output pin that contains a flip-flop and a
number of programmable options.
❖ This minimizes the number of device types needed for a given design
❖Two of the more commonly used configurations are the PAL22V 10 and the Altera EP9 10 .
❖Typical programmable options include the ability to either use or bypass the flip-flop, selection
of the operational mode of the flip-flop (D,T,SR, or JK), selection of the true (Q)or
complement (Q)of the flip-flop as the output and/or as the feedback signal, the ability to make
the flip-flop either a registered output or a buried register, and other options related to flip-flop
clock, preset, and clear inputs
➢ PAL 22V10
• The PAL22V 10 contains a 44 x 132 PAL that drives 10 output macrocells as Fig.11
• macrocells has four output options and two feed back options which are programmed
using fuses S1 and S0 according to Table .4
 ➢ PAL 22V10

❖The complete logic diagram of the PAL22V1O is shown in Fig..13.

❖Note that all 10 flip-flops are controlled by common clock , preset, and reset signals.
❖The clock comes from the CLK/I0 dedicated input pin,
❖ and the preset and reset signals are supplied by product terms generated in the AND array.
❖The PAL circuit has a total of 44 inputs.
 ➢ EP 910
❖EP9IO Is one of a family of EPLD (erasable PLD) devices that contain a PAL with Macrocell
outputs [3].
❖ The fuse configuration of an EPLD can be erased by exposing it to an ultraviolet light for a
short period of time, As shown in Fig. 14,
❖ The EP9IO contains 24 macrocdlls.
❖The PAL section of the EP9IO has 72 inputs, and generates 72 product terms.
 Sequential Circuit Design and PLD Device Selection

❖Sequential circuit design with programmable logic proceeds in the same manner
as when using discrete gates and flip-flops.

1. Design a state diagram from the problem description and derive the state table.
2. Identify and remove redundant states.
3. Make a state variable assignment and derive a state transition table.
4. Select flip-flop types and derive excitation tables for each flip-flop.
5. Derive excitation equations from the excitation tables
6. Derive output equations from the state table,
7. Map the equations onto logic gales and flip flops.
❖The selection of a programmable logic device to realize a given design is
dictated by a number of key features of the design.
1. Number of inputs.
2. Number of storage elements
3. Flip-flop types.
4. Number of outputs.
5. combinational logic.
6. Special features.
7. Physical properties
 PLD Design Examples
Example:
Design a circuit with one input x and one output z that will produce an output of 1 whenever
the last four inputs are 1, that is, a circuit that recognizes the input sequence x = 1111.Realize
the circuit in a PAL16R6 device.
Solution:

Lets:
A=00 , B=01 , C=10 , D=11
From state table we see that two F.F and one combinational output are required to realize the
circuit
The excitation equations for the D flip-flop excitation inputs D1 and D2 and the output
equation are derived from the transition table

These equations are mapped onto the PAL16R6 as illustrated below

 X X
y1y2 0 1 y1y2 0 1
00 0 0 00 0 1
01 0 1 01 0 0
11 0 1 11 0 1
10 0 1 10 0 1

𝑫𝟏 = 𝑿 𝒀𝟏 + 𝑿𝒀𝟐 𝑫𝟐 = 𝑿𝒀𝟏 + 𝑿𝑌ഥ𝟐

X
y1y2 0 1
00 0 0
01 0 0
11 0 1
10 0 0

𝐙 = 𝑿 𝒀𝟏 𝒀𝟐 ഥ + 𝒀𝟏 + 𝒀𝟐
𝐙=𝑿
Example2:
Repeat Example .1, but using the PLS155 FPLS device with the storage elements configured as
JK flip-flops
solution:
From the excitation map the equation will be
Example: Design a circuit with one I/P X and one O/P Z , the output Z is equal to (1)If during two
immediately preceding clock cycles the I/P X was equal to 1 otherwise the value of Z is equal to
(0). Realize the circuit in a PAL16R6 device.
Solution:
x=0 x=1 x=1 x=1
A B C Lets:
x=0 x=0
A=00 , B=01 , C=10
x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1
A A/0 B/0 00 00 01 00 0 0
B A/0 C/0 01 00 10 01 0 0
11 X X 11 X X 11 X X Z= xy1
C A/0 C/1 10 10 0 1 =x+y
00 10

a) state table b) transition table c) 0/P map

 x x
y1y2 0 1 y1y2 0 1

00 0 0 00 0 1
01 0 1 01 0 0

11 X X 11 X X

10 0 1 10 0 0

D1 = xy2 + xy1 D2 = x y1 y2

These equations are mapped onto the PAL16R6 as illustrated below

Example: Design the four-state sequential circuit defined by the following state
table,using the indicated state assignment. using A PLS155, with the flip-flops
configured for JK operation.

Solution:

Lets:
x x A=00 , B=01 , C=11 , D=10
y1y2 0 1 y1y2 0 1
00 01 11 00 0 0
01 10 00 01 0 1
11 00 10 11 1 0 Z= Y1 X + Y1 Y2 + Y1 Y2 X1
10 10 01 10 1 1
a) Transition table b) Output
Present state Next state Output
X=0 x=1 X=0 x=1
00 01 11 0 0
01 10 00 0 1
11 00 10 1 0
10 10 01 1 1

Present Next state output

State X=0 X=1 X=0 X=1
Y1 Y2 J1K1 J2K2 J1K1 J2K2 Z Z
00 0d 1d 1d 1d 0 0
01 1d d1 0d d1 0 1
11 d1 d1 d0 d1 1 0
10 d0 0d d1 1d 1 1
 x x
0 1
0 1 y1y2
y1y2
00 0 1 00 d d
01 1 0 01 d d
11 1 0
11 d d J1 = X Y2 + X Y2 K1 = X Y2 + X Y2
10 0 1
10 d d

x x
0 1 0 1
y1y2 y1y2
00 1 1 00 d d
01 1 1
01 d d
J2 = Y1 Y2 + X 11 1 1 K2 = 1
11 d d
10 0 1 10 d d
X
Example: For the circuit described by the state table and state assignment given below, find a PLS155
implementation, configuring the flip-flops for JK operation. (a) Write the logic equations and indicate the PLS155
pin number to be assigned to each input, output, and state variable.
(b) Sketch the logic diagram using the format of Fig. 11.28.

Solution:
Example: Design a PAL16R4 implementation of a synchronous sequential circuit that recognizes the input sequence
1010. Sequences may overlap. For example,
X =00101001010101110
z = 00000100001010000
Derive the logic equations, then draw the PAL16R4 circuit diagram using the
format of Fig. 11.26.
Solution:

Lets:
A=00 , B=01 , C=11 , D=10
HW:

Design a circuit with one I/P X and one O/P Z , the output Z is equal to (1) after this sequence 1001
otherwise the value of Z is equal to (0). Realize the circuit in a) PLS155 device and b)PAL16R6