DIGITAL SIGNAL PROCESSING

(ECE 3005B)
LABORATORY MANUAL

Third Year- B.TECH (SEM-V)

(ECE & ECE-AIML)
(2024-25)

Department of Electrical and

Electronics Engineering

MITWPU, Pune

1
 Preface
This lab manual is designed to provide a hands-on, practical experience to complement the
theoretical knowledge gained in the classroom. DSP is a vital field that impacts many areas
of modern technology, from telecommunications and multimedia systems to medical
imaging and radar systems. The goal of this lab is to bridge the gap between theory and
practice, allowing students to understand and apply DSP concepts through real-world
experiments and projects.

Objectives

The primary objectives of the DSP Lab are to:

1. Reinforce Theoretical Concepts: Provide practical experience with the fundamental principles
and techniques of DSP, reinforcing the material covered in lectures.
2. Develop Practical Skills: Equip students with the necessary skills to design, implement, and
analyze DSP algorithms using modern software tools and hardware platforms.
3. Encourage Analytical Thinking: Foster critical thinking and problem-solving abilities through
hands-on experimentation and exploration of DSP applications.
4. Promote Innovation: Inspire creativity and innovation by encouraging students to develop and
test their own DSP applications and projects.

2
 School of Electronics and Communication
 Vision and Mission of School

Vision
To be a recognized leader in Electronics and Communication Engineering education and
research with emphasis on social and ethical values

Mission

1. To provide an excellent academic environment for quality education and knowledge

generation in the field of electronics and allied fields
2. To foster a culture of inter disciplinary research and innovation
3. To develop entrepreneurs and leaders to meet growing challenges of the industries

 Program Educational Objectives (PEOs)

The Electronics and Communication Engineering Graduates will excel in their chosen careers
by:

1. Exhibiting the ability to tackle trans disciplinary engineering problems with global
competencies
2. Having a quest for leadership qualities
3. Contributing for the betterment of the society through technology

 Program Outcomes (POs) & Program Specific Outcomes (PSOs)

Program Outcomes:

Engineering Graduates will be able to:

PO1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals and an engineering specialization to the solution of complex engineering
problems.
PO2 Problem analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences and engineering sciences.

3
PO3 Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs
with appropriate consideration for the public health and safety, and the cultural,
societal, and environmental considerations.
PO4 Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
PO5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
PO6 The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
PO7 Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
PO8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
PO9 Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
PO10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend
and write effective reports and design documentation, make effective presentations,
and give and receive clear instructions.
PO11 Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary
environments.
PO12 Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change.

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 Course Objectives and Course Outcomes
Course Objectives:
1. Knowledge
(i) To introduce students with transforms for analysis of Discrete time signals
(ii) To introduce the students with multi-rate sampling techniques and its
applications
2. Skills (i) To understand architecture of DSP processor and use it for real time
Applications
3. Attitude (i) To design and verify the implementation of digital filters.

Course Outcomes: After completion of this course students will be able to

1. Analyze discrete time signals using transform domain techniques (CL-IV)
2. Design and implement LTI filters for filtering different real-world signals (CL-VI)
3. Design and implement multi-rate digital signal processing (CL-VI)
4. Make use of DSP Processors and resources for signal processing applications (CL-III)

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 Digital Signal Processing (ECE 3005B)

List of Experiments
Sr. No Name of the Experiment
1 Analysis of frequency contents of various audio signals using Discrete
Fourier Transform
2 Comparison of Circular Convolution and Linear Convolution
3 Solution to Difference Equation using Simulink
4 Design FIR filter for speech signal and study the effect of different windows
on FIR filter response
5 Design IIR filter for speech signal using the Impulse Invariance / Bilinear
Transformation Techniques
6 Implementation of an Interpolator /Decimator structure.
7 Circular Convolution using TMS320C6748
8 Linear Convolution using TMS320C6748

Signature of the Faculty Head of the Department

6
 Digital Signal Processing
INDEX
Sr. No Name of the Experiment Page Date of Signature of
Checking Batch I/C
1 Analysis of frequency contents of various
audio signals using Discrete Fourier
Transform
2 Comparison of Circular Convolution and
Linear Convolution
3 Solution to Difference Equation using
Simulink
4 Design FIR filter for speech signal and
study the effect of different windows on
FIR filter response
5 Design IIR filter for speech signal using
the Impulse Invariance / Bilinear
Transformation Techniques
6 Implementation of an Interpolator
/Decimator structure.
7 Circular Convolution using TMS320C6748
8 Linear Convolution using TMS320C6748

CERTIFICATE
Certified that Mr. /Ms. ___________________________________________________ of Class
T.Y. B.Tech. (ECE/AIML) Division ______ PRN No. ___________________has completed the
laboratory work in the subject Digital Signal Processing during the Semester V in the School
of Electrical and Electronics Engineering during the Academic Year 2024-2025.

7
 TY. B.Tech (ECE & ECE-AIML))

Semester: 5 Subject:Digital Signal Processing(ECE3005B)

Name: Class:
PRN No: Batch:

Experiment No: 01

Name of the Experiment: Frequency contents of various audio signals

Performed on:
Marks Teacher’s Signature with date
Submitted on:

Aim: Analysis of frequency contents of various audio signals using Discrete Fourier
Transform

Prerequisite: Fourier transform, DFT, DTFT

Objective:
1. To understand signals in time domain and frequency domain

Components and equipment required:

1. PC with MATLAB

Theory:
The Discrete Fourier Transform (DFT) of a time domain sequence x(n) of length
N is defined by
N −1
X ( k )= ∑ x (n)e− j2 π k n/ N , 0≤k≤N −1 (1)
n=0

8
The DFT coefficients X(k) are complex numbers even when x(n) is real. The length-N DFT
sequence is referred as the N-point DFT.

Applying the commonly used notation.

W N =e− j 2 π / N (2)

We can rewrite above equation as

N −1
kn
X ( k )= ∑ x(n)W N 0≤k≤N − (3)
n=0 1
The Inverse Discrete Fourier Transform (IDFT) is given by

N −1
1 −kn
x (n )= ∑ X (k )W N , 0≤n≤N-1 (4)
N k=0

There are four built-in functions in MATLAB for the computation for the DFT and the IDFT:
1. fft(x)
2. fft(x, N)
3. ifft(x)
4. ifft(x, N)

All of these functions make use of FFT algorithms which are computationally highly
efficient compared to the direct computation of DFT and the inverse DFT. The DFT and
IDFT have a number of symmetry properties which are used for computation of DFT and
IDFT.
Read the following code and implement it for different signal and sampling frequencies along
with different N point FFTs.
Verify DFT properties for real sequences: a) X(k) = X*(N-k) = X*((-k))
b) XR(k) is real and even
c) XI(k) is imaginary and odd

9
% Lab_1A_code.m - Frequency contents of sinusoidal signals

clear; % clear Matlab Workspace

close all; % close all figures
clc; % clear Command Window

A1=5; % amplitude of sine wave

fsig1=1000; % frequency, Hz, of the sine wave
T1=1/fsig1; % period, sec, of the sine wave
FS=8000; % sampling frequency, Hz
N=8; % number of sampling points for the sine wave and number of DFT points

%Plot CT signal
t=0:T1/100:T1; % time axis values
x=A1*sin(2*pi*fsig1*t); % sine wave (continuous time) values
figure('Name', 'FFT Analysis 1A'); % plot figure name
subplot(3,1,1);
plot(t,x); % plot of sine wave (continuous time) vs time
xlabel('time ms');
ylabel('x(t)');

%Plot DT signal--
n=0:N-1; % sample numbers
xn=A1*sin(2*pi*fsig1/FS*n); % sine wave (discrete time) values
subplot(3,1,2);
stem(n,xn); % stem plot of sine wave (discrete time) vs sample number
xlabel('sample n');
ylabel('x(n)');

%Plot DFT signal

XFT=fft(xn,N); % N point DFT of xn using FFT function

disp(XFT); % display DFT values
XFTmag=abs(XFT); % magnitudes of DFT values
subplot(3,1,3);
stem(n,XFTmag); % stem plot of DFT values vs sample number
xlabel('discrete frequency k');
ylabel('XFTmag(k)');

10
To analyse any audio signal using fft function:
Algorithm:
 Read the audio file with .wav file type as extension
 Observe this signal in time domain
 Determine its frequency contents (magnitude and phase response)
 Divide the time domain signal in small time slots
 Observe the amplitude variation of each time slots in time domain
 Observe the magnitude and phase response of each time slots in frequency domain
 Repeat the above steps for different sets of audio signal

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Observation table for Lab_1A:

Sr. Fs KHz N fsig1 A1 NZ X(k) NZ X(k) k Fk Hz

No. KHz XR(k) XI(k)
1 8 8 1 5

2 8 16 1 5

3 8 32 1 5

4 10 8 2 10

5 10 16 2 10

6 10 32 2 10

Conclusions:

Post Lab Questions:

1. What are 'twiddle factors' of the DFT?
2. What is the difference between discrete Fourier Series and DFT?
3. Explain the difference between the DTFT and DFT.
4. Explain the meaning of 'frequency resolution' of the DFT.
5. Give the number of complex additions and complex multiplications required for the
direct computation of N-point DFT.
6. What is the need for FFT algorithm?
7. Give the computation efficiency of FFT over DFT for N=1024 and N=2048
Additional links for more information:
https://nptel.ac.in/courses/108101039/download/Lecture-34.pdf
https://www.tutorialspoint.com/digital_signal_processing/
dsp_discrete_fourier_transform_introduction

12
 TY. B.Tech (ECE & ECE-AIML))

Semester: 5 Subject: Digital Signal

Processing(ECE3005B)
Name: Class:
PRN No: Batch:

Experiment No: 02

Name of the Experiment: Comparison of Circular Convolution and Linear Convolution

Performed on: Marks Teacher’s Signature with date

Submitted on:

Aim: Write a program to find 4 point circular convolution and compare the result with 8 point
circular convolution to study aliasing effect in time domain.

Prerequisite: Linear convolution, Circulation convolution, MATLAB input output built-in

functions

Objectives:
1. To study the difference between linear convolution and circular convolution
2. To understand the aliasing effect of circular convolution

Components and equipment required:

PC with MATLAB

Theory:
The circular convolution of two sequences x1(n) and x2(n), each of length N, can
be obtained both in time domain as well as in frequency domain.

In time domain, the circular convolution is obtained as:

13
 n−1
y ( n )=x 1 ( n ) © x 2 ( n )=∑ x 1 ( n ) x 2((m−n))N m=0, 1, . . . . . . .N-1
0

where x 2 ((m−n))N is the circularly reversed (reflected) and shifted counter-

clockwise by n time units version of sequence x2(n).

The circularly reflected and shifted version of x2(n) is given below:

x 2 ( n )=[ x 2 ( 0 ) , x 2 ( 1 ) … … . x 2 ( N −3 ) , x 2 ( N−2 ) , x 2 ( N−1 )]

x 2 ( (−n) )N =[x 2 ( 0 ) , x 2 ( N −1 ) , x 2 ( N −2 ) , x 2 ( N −3 ) , … x 2 ( 2 ) , x 2 ( 1 ) ]

x2¿¿

x2¿¿
x 2 ( N −3 ) , … x 2 (3 ) ¿

⁞
x2¿¿

For N = 4, we get

x 2 ( n )=[ x 2 ( 0 ) , x 2 ( 1 ) , x 2 ( 2 ) , x 2 ( 3 )]

x2¿¿

x2¿¿

x2¿¿

x2¿¿

For N = 8, we get

x 2 ( n )=[ x 2 ( 0 ) , x 2 ( 1 ) , x 2 ( 2 ) , x 2 ( 3 ) , x 2 ( 4 ) , x 2 ( 5 ) , x 2 ( 6 ) , x 2 ( 7 ) ]

x2¿¿

x2¿¿

14
x2¿¿

x2¿¿

x2¿¿

x2¿¿

x2¿¿

x2¿¿

In the frequency domain the circular convolution is obtained as:

y ( n )=IDFT [Y (k )]

Y ( k ) =X 1 ( k ) X 2 ( k ) k =0 , 1 ….. N −1

X 1 ( k )=DFT [x 1(n)]

N −1
X 1 ( k )= ∑ x 1(n) e−2 jπnk / N , k=0 , 1 … … . N −1
n=0

N −1
X 1 ( k )= ∑ x 1 ( n ) W N nk , k =0 ,1 … … . N−1
n=0

−2 jπnk
nk N
where W N =e

Similarly,

X 2 ( k ) =DFT [x 2(n)]

N −1
X 2 ( k ) = ∑ x 2(n) e−2 jπnk / N , k=0 ,1 … … . N−1
n=0

N −1
X 2 ( k ) = ∑ x 2 ( n ) W N nk , k =0 , 1… … . N −1
n=0

Algorithm:

Part A:

15
4 point circular convolution

1. Enter N1 = 4.
2. Enter 1st input sequence x1 of length N1.
3. Enter 2nd input sequence x2 of length N1.
4. Initialize y1(n) = 0.
5. i = 1:N1 & calculate j = n - i + 1.
6. If j < 1, then j = j + N1.
7. Calculate y1(n) = y1(n) + x1(i) * x2 (j).
8. Calculate y3, linear convolution of x1 & x2 using “conv” function in
MATLAB.
9. Make lengths of the two sequences y1 & y3 equal to 2N1(8) by zero
padding, y1 with 4 zeros and y3 with 1 zero.
10.Compare y1 & y3 by obtaining their difference z1 = y1 - y3.

Part B:

8 point circular convolution

1. Enter N2 = 8.
2. Make length of x1 & x2 equal to N2 by zero padding each sequence by
N1(4) zeros.
3. Initialize y2(n) = 0.
4. i = 1:N2 & calculate j = n - i + 1.
5. If j < 1, then j = j + N2.
6. Calculate y2(n) = y2(n) + x1(i) * x2(j).
7. Compare y2 & y3 by obtaining their difference z2 = y2-y3.

Conclusion:

16
Post Lab Questions:

1. Explain the procedure for obtaining the circular graphical convolution of

two sequences each of length N.
2. How is the above procedure modified if the sequences are of different
lengths N & M?
3. Explain the procedure for obtaining the circular convolution of 2
sequences of length N using DFT.
4. Explain the matrix multiplication method for obtaining the circular
convolution of two sequences each of length N.

T.Y. B.Tech (ECE)

Semester: 5 Subject: Digital Signal Processing

Name: Class:

17
Roll No: Batch:

Experiment No: 03

Name of the Experiment: Solution to difference equation using Simulink

Performed on: Marks Teacher’s Signature with date

Submitted on:

Aim: To solve a second order difference equation using Simulink

Prerequisite: Z transform, transfer function in z domain

Objective:
2. To understand discrete time signals and systems in time domain and z domain

Components and equipment required:

2. PC with MATLAB

Theory:
A general Constant Coefficient Linear Difference Equation (CCLDE) is described by

M N
y(n )= ∑ b m x(n−m)− ∑ a k y(n−k )
m=0 k=1 with initial conditions y(i)=−1,−2,. . .. .. . , N , (1)

whose solution can be expressed as:

y ( n )= y zi ( n )+ y zs ( n )

where

yzi (n) = zero input response due to only initial conditions with no inputs

yzs (n) = zero state response due to only inputs with no initial conditions

18
Now consider a second order system i.e. N = 2 & M = 2

y(n ) + a1 y(n- 1) + a 2 y(n- 2) = b 0 x(n ) + b1 x(n-1 ) + b 2 x(n-2) (2)

with initial conditions y(-1) & y(-2).

To solve this second order difference equation using Simulink, we first take the Z transform of both
sides and then implement the resulting Z domain equation as a Direct Form II structure shown in Fig.
1 below:

Taking the Z transform of (2), we get:

−1 −2 −1 −2
Y ( z )=−a 1 z Y ( z )−a2 z Y ( z )+ b0 X ( z )+ b1 z X ( z )+ b2 z X ( z )

Putting this into the Direct Form II structure we have:

y ( n )=bo w ( n )+ b1 w ( n−1 )+ b2 w ( n−2 )

where

w ( n )=x ( n )−a1 w ( n−1 ) −a2 w ( n−2 )

To convert the given initial conditions y(-1) & y(-2) into equivalent conditions w(-1) & w(-2):

y (−1 )=b o w (−1 ) +b1 w (−2 )+ b2 w (−3 )=bo w (−1 ) +b 1 w (−2 )

y (−2 )=b o w (−2 ) +b 1 w (−3 ) +b2 w (−4 ) =bo w (−2 )

Hence

y (−2 ) y (−1 )−b 1 w (−2 ) y (−1 ) b1 y (−2 )

w (−2 )= , w (−1 )= = − (3)
bo bo bo b20

To obtain the equivalent values of x(-1) and x(-2) which produce the initial conditions w(-1) & w(-2)
or y(-1) & y(-2):

For n = -1

y (−1)+a1 y (−2)+a2 y (−3)=b 0 x (−1)+b 1 x (−2)+ b2 x (−3) (4)

As this is a second order system, y(-3) and x(-3) are not present and thus:

19
b 0 x (−1 )= y (−1 ) +a1 y (−2 )−b1 x (−2) (5)

For n = -2

y (−2)+a 1 y (−3)+a 2 y (−4)=b 0 x (−2)+b 1 x (−3)+b2 x (−4 ) (6)

As above, y(-3), y(-4), x(-3) and x(-4) are not present and thus:

y (−2 )=b 0 x (−2 )

x (−2 )=
y (−2 )
b0
, x (−1 )=
b0 (
y (−1 ) a1 b1
)
+ − 2 y (−2 ) (7)
b0 b0

Fig. 1 Second Order Direct Form II Structure

20
Data:

1
y (n )= [ x (n )+x (n−1)+x (n−2)] +0 . 9 y (n−1 )−0 . 81 y (n−2 )
3
nπ
where x (n )=sin ( ) n≥0
6
y (−1)=−3 , y (−2 )=2
Obtain the output y(n) for the first 101 samples (use a sample time of 0.001s and a
simulation time of 0.1s).

Procedure:

1. In the Matlab Command Window, click on the Simulink icon. The Simulink start
page opens. Select Blank Model and click on Create Model.

2 An untitled Simulink model window opens. Save the model as DSP_Expt_3.slx.

3. Open the Library Browser and select Simulink / Sources /Sine Wave. Enter Ctrl + I
to add the sine wave block to the model.
4. Alternatively, double click in an empty area of the model window. The Create
Annotation pop-up appears. Type ‘sine’ and all listed Simulink components in
various libraries whose name begins with ‘sine’ appear. Select Sine Wave and load
it into the model.
5. In a similar manner, enter the remaining items into the model as shown in Fig. 2.

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 Fig. 2 Structure for solution of 2nd order Difference Equation in Simulink

6. Next, the parameter values for the different blocks have to be entered/selected by
double-clicking on the blocks, as follows:

6.1 Sine Wave Sine type: Sample based

Time (t): Use simulation time
Amplitude: Vs
Samples per period: 2*pi/w0
Sample time: 1e-3
All other parameters should be kept at their default values

6.2 Gain blocks -a1, -a2, b0, b1, b2

6.3 Unit Delay1 block Initial condition: wi1

6.4 Unit Delay2 block Initial condition: wi2

7. In order to load the values of -a1, -a2, b0, b1, b2, w0, yi1, yi2 into the model, the
Model post-load function in Model callbacks in the Model Explorer under the Tools
menu is used as shown below in Fig. 3

Fig. 3 Model post-load function in Model callbacks in the Model Explorer

22
8. Finally, open the Model Configuration Parameters menu and enter the parameters as
shown below in Fig. 4.

9. Now save the model file, close it and re-open it once again. This ensures that all
data is loaded into the model by the post-load callback function.
10. Click on the Run button to start the simulation. After the simulation ends, double
click on the scope to observe the input signal x(n) and the output signal y(n). Also
open the ideal.mat using Matlab and open the ans output structure to see the values
of y(n) versus n.
11. By making the input voltage zero and keeping the initial conditions, we can obtain
the zero-input response yzi(n).

12. By making the initial conditions zero and keeping the input voltage, we can obtain
the zero-state response yzs(n).

Fig. 4 Model Configuration Parameters

Conclusions:

23
Post Lab Questions:

1. What is the nature of the zero input response yzi(n) if the system poles are:
i. Inside the unit circle.
ii. On the unit circle.
iii. Outside the unit circle.

2. Multiplication of two sequences in powers of z or z-1 is equivalent to the

convolution of the coefficient sequences. Justify this statement.

TY. B.Tech (ECE & ECE-AIML))

Semester: 5 Subject:Digital Signal Processing(ECE3005B)

Name: Class:
PRN No: Batch:

Experiment No: 04

Name of the Experiment: Design FIR filter for speech signal and study the effect of
different windows on FIR filter response

Performed on:
Marks Teacher’s Signature with date
Submitted on:

Aim: Design FIR filter for speech signal and study the effect of different windows on FIR
filter response

24
Prerequisite: Frequency response of LTI systems, FFT

Objective:
3. To design a FIR LPF filter as per specifications and compare its time-domain outputs
when modified by different windows

Components and equipment required:

3. PC with MATLAB

Theory:
Digital filters are classified on the basis of their impulse response. They are classified as

1. FIR (Finite Impulse Response) filter

2. IIR (Infinite Impulse Response) filter

25
Filter Specifications:

These are shown in Fig. 1 below:

The important specifications which are shown above are:

Next, expressions for the ideal, impulse response of standard filters (LPF, HPF, BPF & BRF) is
shown in Fig. 2.

26
It will be seen that such a response can be never be directly implemented in practice because:

a) The impulse response is of infinite duration

b) The impulse response is non-causal

To convert the impulse response into that which can be physically realizable, the following
steps are carried out:

a) The impulse response is truncated to N points (N is odd) to convert it into a finite response

b) The impulse response is made causal by delaying it by (N-1)/2 points

Methods for FIR filter design:

1. Window Method
2. Frequency Sampling Method
3. Optimal Design

27
The various advantages of FIR filters are:

1. Linear Phase Response

2. Always stable
3. Realized efficiently in hardware

Window Method:

One possible way of obtaining a FIR filter is to truncate the infinite Fourier series
corresponding to the ideal filter. But the abrupt truncation of Fourier series results in
oscillations in passband & stopband. These oscillations are due to convergence of Fourier
series. To reduce the oscillations the Fourier coefficients of the filter are modified by
multiplying with impulse response a finite duration weighing of sequence w(n). w(n) is called a
window.

w ( n )≠0 for 0≤n ≤N- 1

= 0 otherwis e

After multiplying window sequencew (n ) with impulse response h(n) we get finite duration
impulse response hd(n) which satisfies the desired magnitude response.

hd (n )= h(n ). w (n ) for 0≤n ≤N- 1

=0 otherwise

The following fixed window functions are commonly used in the design of FIR filters.

1. Rectangular

2. Hanning

3. Hamming

4. Blackman

5. Kaiser

6. Bartlett

The important parameters of these window functions are shown in Fig. 3 below.

28
Windows descriptions:

1. Rectangular Window: Rectangular window is defined as

w (n )=1 for 0≤n ≤N- 1

= 0 otherwise
The spectrum of rectangular window W(ω) is given by the Fourier transform of w(n)

N−1
W rect = ∑ e
− jω n

n=0

In the rectangular window the convolution of desired frequency response with the frequency
response of window gives rise to ripples in both passband and stopband. The amplitude of
sidelobes is unaffected by length of window; so increase in length N does not reduce amplitude
of the ripple but only increases the ripple frequency.

2. Hamming Window: This window was introduced by R.W. Hamming. It is similar to Hanning
window but has nonzero terms. It is expressed as

2π n
w (n )=0 .54−0. 46 cos( ) for 0≤n ≤N- 1
N−1
= 0 otherwise

The frequency response of Hamming window is calculated using the Fourier transform as

29
 N −1

n=0
(
W hamm(ω)= ∑ 0.54−0. 46cos(
2πn
N−1
) ) e− jωn

3. Hanning Window: The Hanning window named after Julius von Hann and also known as
the Hanning (for being similar in name and form to the Hamming window), von Hann and
the raised cosine window.It is expressed as

(
w ( n )=0.5 1−cos ( N−1
2 πn
))
=0 Otherwise

The frequency response of Hanning window is calculated using the Fourier transform as
N −1
W hann(ω)= ∑ 0.5 1−cos(
n=0
( 2π n
N −1
) ) e− jω n

4.Blackmann Window: It was designed to have close to the minimal leakage possible. It is used
as one of many windowing functions for smoothing values. It is also known as an apodization
(which means “removing the foot”, i.e. smoothing discontinuities at the beginning and end of
the sampled signal) or tapering function. It is known as a “near optimal” tapering function,
almost as similar to the Kaiser window. It is expressed as

w (n)=0.42−0.5 cos ( N2 −1
πn
)+0.08 cos ( N−1
4 πn
)
The frequency response of Blackman window is calculated using the Fourier transform as

( N2 −1 )+0.08 cos ( N4 −1 )e
N−1
πn πn
W black = ∑ 0.42−0.5 cos − jwn

n=0

Algorithm:

30
1. Read audio file and obtain input sequence x(n) and sampling frequency Fs Hz.
2. Enter the LPF specifications [fp, ApdB, fs, AsdB] from 9(a) below, where normalized
frequencies fp (passband cutoff) and fs (stopband cutoff) are w.r.t. the Nyquist
frequency Fs/2.
3. Compute normalized 'fc' at middle of transition band and width of transition band
'ftran' w.r.t. the Nyquist frequency Fs/2.
4. Convert 'ftran' to w.r.t. the sampling frequency Fs.
5. Select the required window function (rectangular, hanning, hamming, blackman),
obtain the filter length N (must be odd), generate FIR filter coefficients and display the
frequency response.
6. Extract and filter the audio file using the FIR LPF.
7. Plot the original signal 'x(n)' vs. sample number 'n' and below it the low pass filtered
signal 'xlp(n)' vs. sample number 'n'.
8. Repeat for 9(b) to 9(g) below and give your comments.
9. a) lpspecrec_1 = [0.01, 0.877, 0.03, 18] Rectangular window
b) lpspecrec_2 = [0.02, 0.877, 0.04, 18] Rectangular window
c) lpspecrec_3 = [0.03, 0.877, 0.05, 18] Rectangular window
d) lpspecrec_4 = [0.07, 0.877, 0.09, 18] Rectangular window
. e) lpspechan = [0.02, 0.103, 0.06, 27] Hanning window
f) lpspecham = [0.02, 0.0376, 0.06, 48] Hamming window
g) lpspecblk = [0.02, 0.0155, 0.06, 62] Blackman window
10. For each frequency response for 9(a) to 9(g) measure
i) Normalized cutoff frequency 'fc'

ii) Normalized half-lobe width 'fh'

iii) Normalized transition width 'ftran'

iv) Stop band attenuation 'AsdB'

31
Result Table:

Normalized
Normalized transition
cutoff
width
frequency Minimum
Sr. Half-lobe ftran stopband
fc
Window
No. width, f h Hz attenuation,
Actual AsdB
Desig
Actual Theoretical f s−f p
n
Fs

1.1 Rectangular 0.9/N

1.2 Rectangular 0.9/N

1.3 Rectangular 0.9/N

1.4 Rectangular 0.9/N

2 Hanning 3.1/N =

3 Hamming 3.3/N =

4 Blackman 5.5/N =

Conclusions:
Post Lab Questions:

1. What is the association between FIR filters and "linear-phase"?

2. What is a linear phase filter?
3. What is the condition for linear phase?
4. What is the Z transform of a FIR filter?
5. What is the frequency response formula for a FIR filter?
6. What is the DC gain of a FIR filter?
7. Are FIR filters inherently stable?
8. Which filters generally used in multirate (decimating and interpolating)
systems?
9. What types of FIR filters are there?

32
 TY. B.Tech (ECE & ECE-AIML))

Semester: 5 Subject:Digital Signal Processing(ECE3005B)

Name: Class:
PRN No: Batch:

Experiment No: 05

Name of the Experiment: Design IIR filter for speech signal using the Impulse Invariance /
Bilinear Transformation Techniques

Performed on:
Marks Teacher’s Signature with date
Submitted on:

Aim: Design of IIR filter for speech signal using Impulse Invariance/Bilinear Transformation
Techniques

Prerequisite: Frequency response of LTI systems, FFT

Objective:
4. To design a IIR LP filter using a second order analog Butterworth LPF prototype, and
employing the Bilinear Transformation technique.

Components and equipment required:

4. PC with MATLAB

Theory:
Digital filters are classified on the basis of their impulse response. They are classified as

3. FIR (Finite Impulse Response) filter

4. IIR (Infinite Impulse Response) filter

33
Filter Specifications:

These are shown in Fig. 1 below:

The important specifications which are shown above are:

Procedure (using Butterworth LP analog protoype filter):

1. Analog frequencies are pre-warped to obtain normalized (digital) frequencies.

w pp=tan(w p ¿ ¿(2∗F s))¿

w ps=tan(w s ¿ ¿(2∗F s))¿

34
 where wp = pass band cutoff frequency in radians/sec.

ws = stop band cutoff frequency in radians/sec.

w pp=¿normalized pre-warped pass band frequency in radians/sample.

w ps=¿normalized pre-warped stop band frequency in radians/sample

Fs = Sampling frequency in Hz.

2. Obtain the order of the Butterworth filter, N:

If attenuation is given in absolute values use:

( )
1
2
−1
As
log 10
1
−1
A p2
N=
2 log 10
( )
w ps
w pp

If attenuation is given in dB values use:

( )
AsdB
10
10 −1
log 10 ApdB
10
10 −1
N=
2 l og10
( )
w ps
w pp

Round up the value of N to nearest integer value.

3. Obtain the cutoff frequency of the Butterworth filter

If attenuation is given in absolute values use:

[( ]
1 w pp w ps
w c= +

) ( )
1 1
2 1 1
−1 2N
−1 2N
A p2 A s2

If attenuation is given in dB values use:

35
 [( ]
1 w pp w ps
w c= 1
+ 1
2
) (10 )
A p dB As dB
2N 2N
10 10
−1 10
−1

4. Obtain the transfer function of the analog LP Butterworth prototype filter

i. If N = 1
wc
H a (s)=
s+ wc
ii. If N = 2
2
wc
H a (s)=
s + √ 2 wc s +w c
2 2

5. Obtain transfer function of the digital IIR Butterworth filter using BLT method.

z−1 1−z−1
s= =
In the bilinear transformation z +1 1+ z−1 is used to transform Ha(s) to Hd (z).

6. For the first order Butterworth digital filter

−1
w c + wc z
H d ( z )= −1
( 1+w c )−( 1−w c ) z
For the second order Butterworth digital filter
−1 −2
b 0+ b1 z +b 2 z
H d ( z )= −1 −2
a 0 + a1 z + a2 z

where b0 = wc

b1 = 2wc

b2 = wc

a 0=1+ √ 2 wc +w c
2

a 2=1−√ 2 wc + wc
2

2
a 1=2 wc −2

2. The coefficient vectors hab & haa representing the coefficients of the numerator and
denominator polynomials of the analog first order transfer function H a(s) = hab(s)/
haa(s) are:

36
 hab = [0, wc]

haa = [1, wc]

The coefficient vectors hdb & hda representing the coefficients of the numerator and
denominator polynomials of the digital first order transfer function Hd(z) = hdb(z)/ hda(z) are:

hdb = [wc, wc ]

hda= [(1+wc), -(1-wc)]

Similarly for a second order transfer function:

hab = [0, 0, w c 2]

haa = [1, √ 2wc, w c 2]

hdb = [wc, 2wc, wc]

hda = [(1+ √ 2 wc +w c ¿ , ( 2 w c −2 ) ,(1− √ 2 w c + wc ) ]

2 2 2

Algorithm:
9. Enter pass band cutoff frequency ‘fp’ Hz.

10. Enter stop band cutoff frequency ‘fs’ Hz.

11. Enter pass band attenuation Ap (actual) or Ap dB.

12. Enter stop band attenuation As (actual) or As dB.

13. Enter sampling frequency Fs in Hz.

6. Compute w pp=tan(w p ¿ ¿(2∗F s))¿

w ps =tan(w s ¿ ¿(2∗F s))¿

7. Obtain the order N of the Butterworth filter.

8. Obtain the cutoff frequency of the Butterworth filter.

9. Compute hdb.

10. Compute hda.

11. Compute hab.

37
 12. Compute haa.

13. fc = wc/(2*pi)*Fs

14. f = 0 : fc/1000 : Fs/2

15. Calculate hd = freqz (hdb, hda, f, F)

16. Normalize hd so that magnitude of hd at w=0 is 1 and hdnorm = hd/hd(1)

17. Figure (1)

semilogx(f, 20log10(abs(hdnorm)), ’r’)

18. Figure (2)

semilogx(f, 180/π*angle(hd), ’r’)

19. Repeat for fe = 0 : fc/1000 : 3F.

21. Figure (3)

plot(fe, 20log10(abs(hdnorm)), ’r’)

22. Figure (4)

plot(fe, 180/π*angle(hd), ’r’,)

Sample Inputs:
1. fpass = 100Hz, fstop = 500Hz, F = 10000Hz , Ap(actual) = 0.7943, As(actual) = 0.3162
2. fpass = 100Hz, fstop = 500Hz, F = 10000Hz , ApdB = 2dB, As = 10dB
3. fpass = 1150Hz, fstop = 2150Hz, F = 10000Hz , Ap(actual) = 0.7943, As(actual) = 0.2818
4. fpass = 1150Hz, fstop = 2150Hz, F = 10000Hz , Ap = 2dB, As =11dB
Conclusions:
Post Lab Questions:

1. Why is the bilinear transformation method superior to the impulse invariance method?
2. Can the bilinear transformation be used for designing high pass and band stop filters.
Justify your answer.

38
3. Why does the frequency response of digital filters using either bilinear transformation or
impulse invariance methods match with frequency response of the corresponding analog
filter only for limited range of frequency?

39
 TY. B.Tech (ECE & ECE-AIML))
Semester: 5 Subject:Digital Signal Processing(ECE3005B)
Name: Class:
PRN No: Batch:

Experiment No: 06

1. Name of the Experiment: Implementation of an Interpolator /Decimator structure.

Performed on:
Marks Teacher’s Signature with date
Submitted on:

Aim: Design an Interpolator and Decimator for speech signals and observe the effect of
downsampling and upsampling.

Prerequisite: Discrete time signals and systems

Objective:
5. To design an Interpolator and Decimator and verify proper functioning of the
upsampling and downsampling blocks.

Components and equipment required:

5. PC with MATLAB

Theory:
There are many applications where the signal at a sampling rate needs to be converted into
another signal with a different sampling rate. For example, in digital audio, 3 different sampling
rates are presently employed: 32 kHz in broadcasting, 44.1 kHz in digital CD and 48 kHz in
Digital audio Tape (DAT). Conversion of sampling rates of audio signals among these three
different rates is necessary in many situations. Discrete time systems with unequal sampling
rates at various parts of the system are called multirate systems.

40
Down-sampling and Decimation –

A down-sampler with a down-sampling factor M, where M is positive integer, creates an output

sequence y(n) with a sampling rate that is (1/M)th of that of the input sequence x(n). The
down-sampling operation is implemented by keeping every M th sample of the input sequence
and removing the M-1 in-between samples to generate the output sequence according to the
relation

y(n)=x(nM)

As a result all input samples with indices equal to an integer multiples of M are retained at the
output and all others are discarded as shown in Fig. 1.

The relation between the Fourier transform of the output and the input of the factor M down-
sampler is given by

M−1
1
jw
Y (e )=
M
∑ X (e j( w−2 πk) /M )
k =0

The above relation implies that Y(ejw) is a sum of M uniformly shifted and stretched versions of
X(ejw), scaled by factor 1/M. Aliasing due to a factor of M down-sampling is absent if and only if
x(n) is band limited to π/M. To avoid aliasing lowpass filter called the decimation filter with
cutoff frequency π/M is used prior to down-sampling.

41
Up-sampling and Interpolation –

An up-sampler with an up-sampling factor L, where L is a positive integer, develops an output

sequence y(n) with a sampling rate that is L times larger than that of the input sequence x(n).
The up-sampling operation is implemented by inserting L-1 equidistant zero valued samples
between two consecutive samples of the input sequence x(n) according to the relation

y(n) = x(n/L), n=0,±L, ±2L, ±3L,….

=0 otherwise

The frequency domain relationship between input and output sequence of up-sampler is given
by

42
 Y(ejw) = X(ejwL)

The factor of L sampling rate expansion leads to L-fold repetitions of X(e jw). This process is
called imaging because we get additional ‘images’ of the input spectrum. In case of a factor of L
sampling rate expansion, there will be (L-1) additional images of the input spectrum in the
baseband. To avoid imaging effect, in sampling rate expansion a lowpass filter with cutoff
frequency π/L is used after up-sampler. This process is known as interpolation. The lowpass
filter called interpolation filter, removes L-1 unwanted images in the spectra of the up-sampled
signal as shown in Fig. 2.

Algorithm:

Part A: Downsampling and Decimation

43
 11. Read audio file and obtain input sequence “x(n)”, its length “xlen” and sampling
frequency “Fs” Hz.
12. Enter the decimation factor “M”, the order “N” (should be an even integer) of the low
pass anti-aliasing FIR filter and decimated output sequence length “L”.
13. Obtain the coefficients of the low pass filter “h(n)” of order “N” and normalized cutoff
frequency “1/M”.
14. Filter the input sequence using the LPF to obtain “xlpf(n)”.
15. Downsample “xlpf(n)” by a factor M to obtain the decimated output signal “xdec(n)”
16. Plot complete input, filtered and decimated sequences.
17. Plot selected portion of input, filtered and decimated sequences.
18. Verify that "xdec(n)" is correctly downsampled from "xlpf(n)” by checking the
corresponding values of "xdec(n)" and "xlpf(n)” for any four indices of “xdec(n)".

Part B: Upsampling and Interpolation

1. Read audio file and obtain input sequence “x(n)”, its length and sampling frequency “Fs”
Hz.
2. Enter the interpolation factor “M”, the order “N” (should be an even integer) of the low
pass anti-imaging FIR filter and selected length “L” of input sequence “x(n)”.
3. Obtain the coefficients of the low pass filter “h(n)” of order “N” and normalized cutoff
frequency “1/M”.
4. Upsample the input sequence by a factor “M” to obtain “xups(n)”.
5. Now filter "xups(n)" using the LPF to obtain interpolated output signal "xint(n)".
6. Plot complete input, upsampled and interpolated (filtered) sequences.
7. Plot selected portion of input, upsampled and interpolated (filtered) sequences.
8. Verify that "xups(n)" is correctly upsampled from "x(n)” by checking the corresponding
values of "x(n)" and "xups(n)” for any four indices of “x(n)".

Conclusion:

Post Lab Questions:

10.Draw the block diagram obtaining sampling rate conversion by a rational factor I/D.

44
11.In a decimator, downsampling by factor D is done after low pass filtering with
normalized cutoff frequency 1/D. What will happen if the sequence of operations is
reversed viz. downsampling by factor D is done before low pass filtering with
normalized cutoff frequency 1/D?
12.In an interpolator, upsampling by factor D is done before low pass filtering with
normalized cutoff frequency 1/D. What will happen if the sequence of operations is
reversed viz. upsampling by factor D is done after low pass filtering with normalized
cutoff frequency 1/D?
13.Draw the direct and transposed block diagrams of a polyphase filter structure with
M = 4.

45
 TY. B.Tech (ECE & ECE-AIML))
Semester: 5 Subject:Digital Signal Processing(ECE3005B)
Name: Class:
PRN No: Batch:

Experiment No: 07

Name of the Experiment: Circular Convolution using TMS320C6748

Performed on:
Marks Teacher’s Signature with date
Submitted on:

Aim: To write a C- program to implement circular convolution using TMS320C6748

Prerequisite: Linear convolution, Embedded processor

Objective:
6. To understand code composer studio and environment of DSP processor

Components and equipment required:

 PC
 Code Composer Studio CCSv5 or CCSv6
 Power supply (+5V)
 EPB_C6748
 Emulator with emulator cable


Features of DSP Processor TMS320C6748:

 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP

 C674x Instruction Set Features
o Superset of the C67x+ and C64x+ ISAs
o Up to 3648 MIPS and 2746 MFLOPS
o Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
o 8-Bit Overflow Protection
o Bit-Field Extract, Set, Clear
o Normalization, Saturation, Bit-Counting
o Compact 16-Bit Instructions
 C674x Two-Level Cache Memory Architecture

46
 o 32KB of L1P Program RAM/Cache
o 32KB of L1D Data RAM/Cache
o 256KB of L2 Unified Mapped RAM/Cache
o Flexible RAM/Cache Partition (L1 and L2)
 Enhanced Direct Memory Access Controller 3 (EDMA3):
o 2 Channel Controllers
o 3 Transfer Controllers
o 64 Independent DMA Channels
o 16 Quick DMA Channels
o Programmable Transfer Burst Size
 TMS320C674x Floating-Point VLIW DSP Core
o Load-Store Architecture with Nonaligned Support
o 64 General-Purpose Registers (32-Bit)
o Six ALU (32- and 40-Bit) Functional Units
 Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE
Double Precision/64-Bit) Floating Point
 Supports up to Four SP Additions Per Clock, Four DP Additions Every Two
Clocks
 Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation
(RCPxP) and Square-Root Reciprocal Approximation (RSQRxP)
Operations Per Cycle
o Two Multiply Functional Units:
 Mixed-Precision IEEE Floating-Point Multiply Supported up to:
 2 SP x SP → SP Per Clock
 2 SP x SP → DP Every Two Clocks
 2 SP x DP → DP Every Three Clocks
 2 DP x DP → DP Every Four Clocks
 Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-
Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex
Multiples
o Instruction Packing Reduces Code Size
o All Instructions Conditional
o Hardware Support for Modulo Loop Operation
o Protected Mode Operation
o Exceptions Support for Error Detection and Program Redirection
 Software Support
o TI DSPBIOS
o Chip Support Library and DSP Library
 128KB of RAM Shared Memory
 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
 Two External Memory Interfaces:
o EMIFA
 NOR (8- or 16-Bit-Wide Data)
 NAND (8- or 16-Bit-Wide Data)
 16-Bit SDRAM with 128-MB Address Space
o DDR2/Mobile DDR Memory Controller with one of the following:
 16-Bit DDR2 SDRAM with 256-MB Address Space
 16-Bit mDDR SDRAM with 256-MB Address Space

47
 Three Configurable 16550-Type UART Modules:
o With Modem Control Signals
o 16-Byte FIFO
o 16x or 13x Oversampling Option
 LCD Controller
 Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
 Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O
(SDIO) Interfaces
 Two Master and Slave Inter-Integrated Circuits
(I2C Bus)
 One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High
Bandwidth
 Programmable Real-Time Unit Subsystem (PRUSS)
o Two Independent Programmable Real-Time Unit (PRU) Cores
 32-Bit Load-Store RISC Architecture
 4KB of Instruction RAM Per Core
 512 Bytes of Data RAM Per Core
 PRUSS can be Disabled via Software to Save Power
 Register 30 of Each PRU is Exported From the Subsystem in Addition to
the Normal R31 Output of the PRU Cores.
o Standard Power-Management Mechanism
 Clock Gating
 Entire Subsystem Under a Single PSC Clock Gating Domain
o Dedicated Interrupt Controller
o Dedicated Switched Central Resource
 USB 1.1 OHCI (Host) with Integrated PHY (USB1)
 USB 2.0 OTG Port with Integrated PHY (USB0)
o USB 2.0 High- and Full-Speed Client
o USB 2.0 High-, Full-, and Low-Speed Host
o End Point 0 (Control)
o End Points 1,2,3,4 (Control, Bulk, Interrupt, or ISOC) RX and TX
 One Multichannel Audio Serial Port (McASP):
o Two Clock Zones and 16 Serial Data Pins
o Supports TDM, I2S, and Similar Formats
o DIT-Capable
o FIFO Buffers for Transmit and Receive
 Two Multichannel Buffered Serial Ports (McBSPs):
o Supports TDM, I2S, and Similar Formats
o AC97 Audio Codec Interface
o Telecom Interfaces (ST-Bus, H100)
o 128-Channel TDM
o FIFO Buffers for Transmit and Receive
 10/100 Mbps Ethernet MAC (EMAC):
o IEEE 802.3 Compliant
o MII Media-Independent Interface
o RMII Reduced Media-Independent Interface
o Management Data I/O (MDIO) Module
 Video Port Interface (VPIF):

48
 o Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video
Capture Channels
o Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
 Universal Parallel Port (uPP):
o High-Speed Parallel Interface to FPGAs and Data Converters
o Data Width on Both Channels is 8- to 16-Bit Inclusive
o Single-Data Rate or Dual-Data Rate Transfers
o Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
 Serial ATA (SATA) Controller:
o Supports SATA I (1.5 Gbps) and SATA II
(3.0 Gbps)
o Supports All SATA Power-Management Features
o Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
o Supports Port Multiplier and Command-Based Switching
 Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
 Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
 One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-
Purpose Timers)
 Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
o Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
o 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge
Asymmetric Outputs
o Dead-Band Generation
o PWM Chopping by High-Frequency Carrier
o Trip Zone Input
 Three 32-Bit Enhanced Capture (eCAP) Modules:
o Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM)
Outputs
o Single-Shot Capture of up to Four Event Time-Stamps
 Packages:
o 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
o 361-Ball Pb-Free PBGA [ZWT Suffix],
0.80-mm Ball Pitch
 Commercial, Extended, or Industrial Temperature

49
Block Diagram of DSP Processor TMS320C6748

Device Compatibility
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families

50
DSP Subsystem:

The DSP Subsystem includes the following features:

• C674x DSP CPU

• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 256KB Unified Mapped RAM/Cache (L2)
• Boot ROM (cannot be used for application code)
• Little endian

DSP TMS320C6748 Mega Module Block Diagram:

51
TMS320C674x Mega Module:

The C674x Mega module consists of the following components:

• TMS320C674x CPU
• Internal memory controllers:
– Level 1 program memory controller (PMC)
– Level 1 data memory controller (DMC)
– Level 2 unified memory controller (UMC)
– Extended memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals:
– Interrupt controller (INTC)
– Power-down controller (PDC)
– Bandwidth manager (BWM)
• Advanced event triggering (AET)

Features of the EPB_C6748 Development Board

The EPB_C6748 is a stand-alone card--allowing developers to evaluate the TMS320C6748 DSP to

determine if it meets their Application requirements. Furthermore, the module is an excellent platform
to develop and run software for the TMS320C6748 DSP.

The EPB_C6748 is shipped with a TMS320C6748 DSP. The EPB_C6748 allows full speed verification of
C6748 code.

To simplify code development and shorten debugging time, a C6000 Code Composer Studio driver is
provided. In addition, an onboard JTAG connector provides interface to emulators, with assembly
language and ‘C’ high level language debug.

52
1.1 Key Features of the EPB_C6748

1.1.1 Hardware Features

Mechanical Parameters
Size: 160mm x 136mm
Input Voltage - 5V DC

Processor
TMS320C6748 – Fixed/ Floating Point Digital Signal Processor
DSP with up to 375/456 MHz performance.
On board 14 Pin (2x7 Pin) JTAG emulation connector
Boot mode selection switch

Memory

53
On board 256 MB Flash memory
On board 128 MB DDR2 RAM memory

Data Transfer Interfaces

On board DB9 connector for UART-1 interface
On board 3 pin header for UART-2 interface
On board USB TYPE B Connector for UART-2 interface for Debug Console
LED indication for USB connection for Debug Console
On board Reset Switch with LED indication
On board USB Type A Connector for USB host interface
On board micro USB Type A Connector for USB OTG interface
On board RJ45 connector for 10/100 Ethernet interface
On board I2C based Temperature sensor
On board I2C based RTC interface with battery backup
On board SPI based micro SD card interface
On board SATA connector

Input/Output Interfaces and other Facilities

On board Power-On LED indication
On board 4 User LED at GPIO Pin as GPIO Test point
On board 5 user push buttons for various applications

Special functionality
Boot mode selection switch
On board Video in port available
On board VGA out connector
On board composite video out connector
On board Graphics LCD interface connector
On board audio jack and speaker (Mic in) interface
On board audio codec for speaker out
On board CMOS sensor connector to interface CMOS camera

54
On board Temperature sensor with interrupt out facility
On board jumper selection to switch various video out options
On board LED to indicate power surge
On board LED to indicate high voltage input
On board excessive voltage protection circuit with LED indication
Various test points for various signals
On board jumper selection to switch UART2 between USB connector and 3 pin connector

1.1.2 Software Features

 TI Code Composer Studio 5.0 or later

 BIOS C600SDK

55
Principal Components and I/O Interfaces of the EPB_C6748 Development Board

56
Procedure:
1. Connect the power supply (+5v) at J16 power socket connector of the EPB_C6748 kit.

2. Connect Texas Instruments XDS100v2 Emulator to the PC using USB A to Mini A cable.

3. Connect JTAG connector of Texas Instruments XDS100v2 Emulator to JTAG connector of

EPB_C6748 kit.

4. Start CCSv5 and select workspace as “C:\workspace_v5_3_Pune_DSP.

OR

5. Start CCSv6 and select workspace as “C:\workspace_v6_1_Pune_DSP”

6. Now refer to document “Chapter 5.1 Creating New Project with CCS_v5 and C6748.doc”
(attached) and create a new CCS empty Project (with “main.c”) named “Circular
Convolution”.

7. The “CCS Edit” perspective will open as shown in Fig. 1 with “Circular Convolution
[Active - Debug]” project in bold as the active debug project.

Fig. 1

8. Under the “Project Explorer” tab, click on “Circular Convolution [Active - Debug]” project.
The three default files/folders created during project creation viz. “Includes”,
“targetConfigs”, and “C6748.cmd” along with the source file “main.c” are now visible as
shown in Fig. 2.

57
58
Fig. 2

9. Next, set the correct Target Configuration as under:

9.1 Open file “targetConfigs\TMS320C6748.ccxml”. The “Basic” page opens.
9.2 Open drop-down tab “Connection” and, if not already selected, select “Texas
Instruments XDS100v2 USB Emulator”.
9.3 Open drop-down tab “Connection” and, if not already selected, select “Texas
Instruments XDS100v2 USB Emulator”.
9.4 Open drop-down tab “Board or Device” and, if not already selected, select
“TMS320C6748”.
9.5 Now open the “Advanced Setup” page. The “Target Configuration” tree appears.
9.6 Return to the “Basic” page and click on “Save Configuration”. The “Target
Configuration” menu is shown in Fig. 3.
9.7 Under tab “Test Connection” click “Test Connection”. The connection between
CCSv5.3 or CCS6 and the C6748 target board via the XDS100v2 emulator is now
checked. Confirm that the following two statements appear on the screen as
shown in Fig. 4:
“The JTAG IR Integrity scan-test has succeeded.”
“The JTAG DR Integrity scan-test has succeeded.”

59
Fig. 3

Fig. 4

10. Now, enter the C progam in file “main.c”.

60
11. Next, build the project by clicking on “Project → Build Project” (Fig.5). If this is grayed out,
then click on “Clean” and clean and select only the current project. Also select “Start a build
immediately” (Fig. 6). If there are no errors during build, as shown by the “Problems”
window, the “Console” window should show 'Finished building target: Circular Convolution.out' and
**** Build Finished **** as shown in Fig. 7.

Fig. 5

61
Fig.6 6

Fig. 7

12. To link the generated object code with the selected library header files and create the hex
file which is to be loaded into the C6748 program memory, click on Run\Debug or F11.
Next click on “View” drop-down menu and select windows “Project Explorer”,
“Variables/Expressions/Registers”, “Console”, “Problems”, “Debug” and “main.c” to
appear in the “CCS Debug” perspective as shown in Fig. 8.

62
Fig. 8

13. To run the project, the three commands viz. “Resume (F8, Green Right Arrow)”, “Suspend
(Alt + F8, Two Vertical Bars)” and “Terminate (Ctrl + F2, Red Square)” are used to start,
pause and terminate the program.
14. Run the program, enter the required data (each element of h(n) and x(n) has to be
separately entered) and obtain the Circular Convolution output on the Console (expand
the window) as shown in Fig. 9.
Fig. 9

15. To obtain the values of the input and output variables, add a breakpoint on the “main.c”
program at the last instruction “while(1)” (line 80). Since the program has now halted at
this line, the values of simple variables as well as array variables are now visible in the
expanded “Variables/Expressions/Registers” window as shown in Fig. 10.

63
Fig. 10

16. To obtain a graphical display of the contents of any array variable e.g. x(n), right click that
variable in the “Variables/Expressions/Registers” window and select “Graph”. The
“Console” window opens displaying graph “Single Time-X” as shown in Fig. 11.

Fig. 11

64
 Edit this graph to display it in the desired “Bar” format by clicking “Show the Graph
Properties” icon on the Menu bar on the right side as shown in Fig. 12.

Fig. 12

Edit the values of parameters “Acquisition Buffer Size”, “Dsp Data Type”, “Display Data
Size” as required (15 and 10 respectively in this case). Also select “Bar” for “Data Plot
Style”. Now edit the Y axis label by clicking “Display Properties” icon on the Menu bar on
the right side. Select “Axes” and enter “x(n)” as “Title” for “Y –Axis” as shown in Fig. 13.

65
Fig. 13

The final graph (expanded) is shown in Fig. 14. In this manner all other arrays can be
graphically displayed.

Fig. 14

Verification: Confirm that your circular convolution result is correct by checking with the
“cconv” command of Matlab.

66
Conclusions:

Post Lab Questions:

1. List the on-chip peripherals in TMS320C67XX processor.

2. List the various types of multiply operations performed by Multi Functional Unit of
TMS320C67xx.
3. Write down the steps to be followed to convert a signed decimal number into IEEE 754
Single Precision Floating Point format and Double Precision Floating Point format

67
 TY. B.Tech (ECE & ECE-AIML))

Semester: 5 Subject:Digital Signal Processing(ECE3005B)

Name: Class:
PRN No: Batch:

Experiment No: 08

Name of the Experiment: Linear Convolution using TMS320C6748

Performed on:
Marks Teacher’s Signature with date
Submitted on:

Aim: To write a C- program to implement linear convolution using TMS320C6748

Prerequisite: Linear convolution, Embedded processor

Objective:
7. To understand code composer studio and environment of DSP processor

Components and equipment required:

 PC
 Code Composer Studio CCSv5 or CCSv6
 Power supply (+5V)
 EPB_C6748
 Emulator with emulator cable


Features of DSP Processor TMS320C6748:

 375- and 456-MHz C674x Fixed- and Floating-Point VLIW DSP

 C674x Instruction Set Features
o Superset of the C67x+ and C64x+ ISAs
o Up to 3648 MIPS and 2746 MFLOPS
o Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
o 8-Bit Overflow Protection
o Bit-Field Extract, Set, Clear
o Normalization, Saturation, Bit-Counting
o Compact 16-Bit Instructions

68
 C674x Two-Level Cache Memory Architecture
o 32KB of L1P Program RAM/Cache
o 32KB of L1D Data RAM/Cache
o 256KB of L2 Unified Mapped RAM/Cache
o Flexible RAM/Cache Partition (L1 and L2)
 Enhanced Direct Memory Access Controller 3 (EDMA3):
o 2 Channel Controllers
o 3 Transfer Controllers
o 64 Independent DMA Channels
o 16 Quick DMA Channels
o Programmable Transfer Burst Size
 TMS320C674x Floating-Point VLIW DSP Core
o Load-Store Architecture with Nonaligned Support
o 64 General-Purpose Registers (32-Bit)
o Six ALU (32- and 40-Bit) Functional Units
 Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE
Double Precision/64-Bit) Floating Point
 Supports up to Four SP Additions Per Clock, Four DP Additions Every Two
Clocks
 Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation
(RCPxP) and Square-Root Reciprocal Approximation (RSQRxP)
Operations Per Cycle
o Two Multiply Functional Units:
 Mixed-Precision IEEE Floating-Point Multiply Supported up to:
 2 SP x SP → SP Per Clock
 2 SP x SP → DP Every Two Clocks
 2 SP x DP → DP Every Three Clocks
 2 DP x DP → DP Every Four Clocks
 Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-
Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex
Multiples
o Instruction Packing Reduces Code Size
o All Instructions Conditional
o Hardware Support for Modulo Loop Operation
o Protected Mode Operation
o Exceptions Support for Error Detection and Program Redirection
 Software Support
o TI DSPBIOS
o Chip Support Library and DSP Library
 128KB of RAM Shared Memory
 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
 Two External Memory Interfaces:
o EMIFA
 NOR (8- or 16-Bit-Wide Data)
 NAND (8- or 16-Bit-Wide Data)
 16-Bit SDRAM with 128-MB Address Space
o DDR2/Mobile DDR Memory Controller with one of the following:
 16-Bit DDR2 SDRAM with 256-MB Address Space

69
  16-Bit mDDR SDRAM with 256-MB Address Space
 Three Configurable 16550-Type UART Modules:
o With Modem Control Signals
o 16-Byte FIFO
o 16x or 13x Oversampling Option
 LCD Controller
 Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
 Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O
(SDIO) Interfaces
 Two Master and Slave Inter-Integrated Circuits
(I2C Bus)
 One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High
Bandwidth
 Programmable Real-Time Unit Subsystem (PRUSS)
o Two Independent Programmable Real-Time Unit (PRU) Cores
 32-Bit Load-Store RISC Architecture
 4KB of Instruction RAM Per Core
 512 Bytes of Data RAM Per Core
 PRUSS can be Disabled via Software to Save Power
 Register 30 of Each PRU is Exported From the Subsystem in Addition to
the Normal R31 Output of the PRU Cores.
o Standard Power-Management Mechanism
 Clock Gating
 Entire Subsystem Under a Single PSC Clock Gating Domain
o Dedicated Interrupt Controller
o Dedicated Switched Central Resource
 USB 1.1 OHCI (Host) with Integrated PHY (USB1)
 USB 2.0 OTG Port with Integrated PHY (USB0)
o USB 2.0 High- and Full-Speed Client
o USB 2.0 High-, Full-, and Low-Speed Host
o End Point 0 (Control)
o End Points 1,2,3,4 (Control, Bulk, Interrupt, or ISOC) RX and TX
 One Multichannel Audio Serial Port (McASP):
o Two Clock Zones and 16 Serial Data Pins
o Supports TDM, I2S, and Similar Formats
o DIT-Capable
o FIFO Buffers for Transmit and Receive
 Two Multichannel Buffered Serial Ports (McBSPs):
o Supports TDM, I2S, and Similar Formats
o AC97 Audio Codec Interface
o Telecom Interfaces (ST-Bus, H100)
o 128-Channel TDM
o FIFO Buffers for Transmit and Receive
 10/100 Mbps Ethernet MAC (EMAC):
o IEEE 802.3 Compliant
o MII Media-Independent Interface
o RMII Reduced Media-Independent Interface
o Management Data I/O (MDIO) Module

70
 Video Port Interface (VPIF):
o Two 8-Bit SD (BT.656), Single 16-Bit or Single Raw (8-, 10-, and 12-Bit) Video
Capture Channels
o Two 8-Bit SD (BT.656), Single 16-Bit Video Display Channels
 Universal Parallel Port (uPP):
o High-Speed Parallel Interface to FPGAs and Data Converters
o Data Width on Both Channels is 8- to 16-Bit Inclusive
o Single-Data Rate or Dual-Data Rate Transfers
o Supports Multiple Interfaces with START, ENABLE, and WAIT Controls
 Serial ATA (SATA) Controller:
o Supports SATA I (1.5 Gbps) and SATA II
(3.0 Gbps)
o Supports All SATA Power-Management Features
o Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries
o Supports Port Multiplier and Command-Based Switching
 Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
 Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
 One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-
Purpose Timers)
 Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
o Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
o 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge
Asymmetric Outputs
o Dead-Band Generation
o PWM Chopping by High-Frequency Carrier
o Trip Zone Input
 Three 32-Bit Enhanced Capture (eCAP) Modules:
o Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM)
Outputs
o Single-Shot Capture of up to Four Event Time-Stamps
 Packages:
o 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
o 361-Ball Pb-Free PBGA [ZWT Suffix],
0.80-mm Ball Pitch
 Commercial, Extended, or Industrial Temperature

71
Block Diagram of DSP Processor TMS320C6748

Device Compatibility
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families

72
DSP Subsystem:

The DSP Subsystem includes the following features:

• C674x DSP CPU

• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 256KB Unified Mapped RAM/Cache (L2)
• Boot ROM (cannot be used for application code)
• Little endian

DSP TMS320C6748 Mega Module Block Diagram:

73
TMS320C674x Mega Module:

The C674x Mega module consists of the following components:

• TMS320C674x CPU
• Internal memory controllers:
– Level 1 program memory controller (PMC)
– Level 1 data memory controller (DMC)
– Level 2 unified memory controller (UMC)
– Extended memory controller (EMC)
– Internal direct memory access (IDMA) controller
• Internal peripherals:
– Interrupt controller (INTC)
– Power-down controller (PDC)
– Bandwidth manager (BWM)
• Advanced event triggering (AET)

Features of the EPB_C6748 Development Board

The EPB_C6748 is a stand-alone card--allowing developers to evaluate the TMS320C6748 DSP to

determine if it meets their Application requirements. Furthermore, the module is an excellent platform
to develop and run software for the TMS320C6748 DSP.

The EPB_C6748 is shipped with a TMS320C6748 DSP. The EPB_C6748 allows full speed verification of
C6748 code.

To simplify code development and shorten debugging time, a C6000 Code Composer Studio driver is
provided. In addition, an onboard JTAG connector provides interface to emulators, with assembly
language and ‘C’ high level language debug.

74
1.1 Key Features of the EPB_C6748

1.1.3 Hardware Features

Mechanical Parameters
Size: 160mm x 136mm
Input Voltage - 5V DC

Processor
TMS320C6748 – Fixed/ Floating Point Digital Signal Processor
DSP with up to 375/456 MHz performance.
On board 14 Pin (2x7 Pin) JTAG emulation connector
Boot mode selection switch

Memory

75
On board 256 MB Flash memory
On board 128 MB DDR2 RAM memory

Data Transfer Interfaces

On board DB9 connector for UART-1 interface
On board 3 pin header for UART-2 interface
On board USB TYPE B Connector for UART-2 interface for Debug Console
LED indication for USB connection for Debug Console
On board Reset Switch with LED indication
On board USB Type A Connector for USB host interface
On board micro USB Type A Connector for USB OTG interface
On board RJ45 connector for 10/100 Ethernet interface
On board I2C based Temperature sensor
On board I2C based RTC interface with battery backup
On board SPI based micro SD card interface
On board SATA connector

Input/Output Interfaces and other Facilities

On board Power-On LED indication
On board 4 User LED at GPIO Pin as GPIO Test point
On board 5 user push buttons for various applications

Special functionality
Boot mode selection switch
On board Video in port available
On board VGA out connector
On board composite video out connector
On board Graphics LCD interface connector
On board audio jack and speaker (Mic in) interface
On board audio codec for speaker out
On board CMOS sensor connector to interface CMOS camera

76
On board Temperature sensor with interrupt out facility
On board jumper selection to switch various video out options
On board LED to indicate power surge
On board LED to indicate high voltage input
On board excessive voltage protection circuit with LED indication
Various test points for various signals
On board jumper selection to switch UART2 between USB connector and 3 pin connector

1.1.4 Software Features

 TI Code Composer Studio 5.0 or later

 BIOS C600SDK

77
Principal Components and I/O Interfaces of the EPB_C6748 Development Board

78
Procedure:
17. Connect the power supply (+5v) at J16 power socket connector of the EPB_C6748 kit.

18. Connect Texas Instruments XDS100v2 Emulator to the PC using USB A to Mini A cable.

19. Connect JTAG connector of Texas Instruments XDS100v2 Emulator to JTAG connector of
EPB_C6748 kit.

20. Start CCSv5 and select workspace as “C:\workspace_v5_3_Pune_DSP.

OR

21. Start CCSv6 and select workspace as “C:\workspace_v6_1_Pune_DSP”

22. Now refer to document “Chapter 5.1 Creating New Project with CCS_v5 and C6748.doc”
(attached) and create a new CCS empty Project (with “main.c”) named “Linear
Convolution”.

23. The “CCS Edit” perspective will open as shown in Fig. 1 with “Linear Convolution [Active
- Debug]” project in bold as the active debug project.

Fig. 1

24. Under the “Project Explorer” tab, click on “Linear Convolution [Active - Debug]” project.
The three default files/folders created during project creation viz. “Includes”,
“targetConfigs”, and “C6748.cmd” along with the source file “main.c” are now visible as
shown in Fig. 2.

79
Fig. 2

25. Next, set the correct Target Configuration as under:

25.1 Open file “targetConfigs\TMS320C6748.ccxml”. The “Basic” page opens.
25.2 Open drop-down tab “Connection” and, if not already selected, select “Texas
Instruments XDS100v2 USB Emulator”.
25.3 Open drop-down tab “Connection” and, if not already selected, select “Texas
Instruments XDS100v2 USB Emulator”.
25.4 Open drop-down tab “Board or Device” and, if not already selected, select
“TMS320C6748”.
25.5 Now open the “Advanced Setup” page. The “Target Configuration” tree appears.
25.6 Return to the “Basic” page and click on “Save Configuration”. The “Target
Configuration” menu is shown in Fig. 3.
25.7 Under tab “Test Connection” click “Test Connection”. The connection between
CCSv5.3 or CCS6 and the C6748 target board via the XDS100v2 emulator is now
checked. Confirm that the following two statements appear on the screen as
shown in Fig. 4:
“The JTAG IR Integrity scan-test has succeeded.”
“The JTAG DR Integrity scan-test has succeeded.”

80
Fig. 3

Fig. 4

26. Now, enter the C progam in file “main.c”.

81
27. Next, build the project by clicking on “Project → Build Project” (Fig.5). If this is grayed
out, then click on “Clean” and clean and select only the current project. Also select “Start a
build immediately” (Fig. 6). If there are no errors during build, as shown by the
“Problems” window, the “Console” window should show 'Finished building target: Linear
Convolution.out' and **** Build Finished **** as shown in Fig. 7.

Fig. 5

Fig. 6

82
Fig. 7

28. To link the generated object code with the selected library header files and create the hex
file which is to be loaded into the C6748 program memory, click on Run\Debug or F11.
Next click on “View” drop-down menu and select windows “Project Explorer”,
“Variables/Expressions/Registers”, “Console”, “Problems”, “Debug” and “main.c” to
appear in the “CCS Debug” perspective as shown in Fig. 8.

Fig. 8

83
29. To run the project, the three commands viz. “Resume (F8, Green Right Arrow)”, “Suspend
(Alt + F8, Two Vertical Bars)” and “Terminate (Ctrl + F2, Red Square)” are used to start,
pause and terminate the program.
30. Run the program, enter the required data (each element of h(n) and x(n) has to be
separately entered) and obtain the Linear Convolution output on the Console (expand
the window) as shown in Fig. 9.

Fig. 9

31. To obtain the values of the input and output variables, add a breakpoint on the “main.c”
program at the last instruction “while(1)” (line 57). Since the program has now halted at
this line, the values of simple variables as well as array variables are now visible in the
expanded “Variables/Expressions/Registers” window as shown in Fig. 10.

84
Fig. 10

32. To obtain a graphical display of the contents of any array variable e.g. x(n), right click that
variable in the “Variables/Expressions/Registers” window and select “Graph”. The
“Console” window opens displaying graph “Single Time-X” as shown in Fig. 11.

Fig. 11

85
 Edit this graph to display it in the desired “Bar” format by clicking “Show the Graph
Properties” icon on the Menu bar on the right side as shown in Fig. 12.

Fig. 12

Edit the values of parameters “Acquisition Buffer Size”, “Dsp Data Type”, “Display Data
Size” as required (15 and 10 respectively in this case). Also select “Bar” for “Data Plot
Style”. Now edit the Y axis label by clicking “Display Properties” icon on the Menu bar on
the right side. Select “Axes” and enter “x(n)” as “Title” for “Y –Axis” as shown in Fig. 13.

86
Fig. 13

The final graph (expanded) is shown in Fig. 14. In this manner all other arrays can be
graphically displayed.

Fig. 14

Verification: Confirm that your linear convolution result is correct by checking with the
“conv” command of Matlab.

87
Conclusions:

Post Lab Questions:

4. List the addressing modes supported by the TMS320C6X processor.

5. Explain the operation of circular addressing mode with an example.
6. Explain pipeline operations in the TMS320C6X processor.

88