GUJARAT POWER ENGINEERING AND RESEARCH

INSTITUTE
Department of Computer Engineering
Subject: Computer Organization and Architecture (3140707)
Semester: IV

Unit 1 : Computer Data Representation

1. Discuss 4-bit binary adder with a neat diagram. S-23, S-22
2. Discuss three state bus buffers with a neat diagram. S-23, W-21
3. Write the difference(s) between arithmetic shift left and logical shift left S-23
instruction. Support your answer with proper illustration.
4. What is binary and decimal equivalent of F8 hexadecimal value? S-22
5. Write Steps for two n digit numbers subtraction in base r. S-22
6. State and Explain any seven logic micro operation. S-22
7. What is arithmetic micro operation? S-22
8. Write down RTL statements for the fetch and decode operation of basic S-21
computer.
9. Explain how (r-1)’s complement is calculated. Calculate 9’s complement of S-21
546700.
10. Define RTL. Give block diagram and timing diagram of transfer of R1 to R2 S-21
when P=1.
11. What is combinational circuit? Explain multiplexer in detail. How many S-20
NAND gates are needed to implement 4 x 1 MUX?
12. Design a simple arithmetic circuit which should implement the following S-20
operations: Assume A and B are 3 bit registers.
Add : A+B, Add with Carry: A+B+1, Subtract: A+B’, Subtract with
Borrow: A+B’+1, Increment A: A+1, Decrement A: A-1, Transfer A:
A
13. Explain how addition and subtraction of signed data is performed if a computer S-20
system uses signed magnitude representation.
14. What is Tri-State buffer? Why it is useful to form a bus system? S-19
15. Explain arithmetic shift left operation. Describe how overflow is handled. S-19
16. Explain BCD adder with diagram. S-19
17. Show different ways to represent fixed-point positive integers including zero. W-23
18. Explain any four Arithmetic operations carried out by ALU. W-23
19. Apply J K flip-flops to design a 3-bit synchronous binary counter. W-23
20. Apply the combinational circuits to design a 4-bit adder/subtracter circuit which W-23
performs subtraction using 2’s complement.
21. Draw the block diagram of 4-bit combinational circuit shifter W-22
22. Construct diagram of common bus system of four 4-bits registers with diagram. W-22
23. What is the role of sequence counter (SC) in control unit? Interpret its concept W-22
with the help of its three inputs using diagram.
24. Construct a 4-bit adder-subtractor circuit. W-21
 Unit 2 : Basic Computer Organization and Design
1. Write the name of basic computer registers with their functionalities. S-23, S-22, W-
22
2. Write sequence of microoperations to execute the following instructions: S-23
- AND
- STA
3. List and explain Memory reference instructions in detail. S-22
4. Explain register reference instruction format. S-22
5. Explain register transfer using block diagram and timing diagram. S-22
6. Draw and explain control unit diagram for basic computer. S-22
7. State various phases of instruction cycle. S-22
8. Explain any four input output reference instruction. S-22
9. Enlist register reference instructions and explain any one of them in detail. S-20
10. Draw the flowchart for instruction cycle and explain. S-20, S-19
11. Explain LDA and STA instructions with its micro-operations with relevant D S-19
and T notations.
12. What do you mean by instruction set completeness? Explain. S-19
13. Explain instructions:- BSA, ISZ, SZE W-23
14. Draw the block diagram of a hypothetical basic computer. W-23
15. Calculate and show the number of clock cycles required to execute BSA W-23
instruction.
16. Show the working of LDA instruction using RTL. W-23
17. Which are the different phases of Instruction Cycle? Describe Register transfer W-22
for fetch phase with its diagram.
18. Define: microinstruction; Identify different types of 16 bits instruction formats W-22
for basic computer using figure.
19. Use BSA and BUN instruction with example and diagram. W-22, W-21
20. Describe how control unit determine instruction type after the decoding using W-22
flowchart for instruction cycle.
21. Interpret the following instructions: INP, ISZ and LDA W-22
22. What is interrupt? Describe interrupt cycle with neat diagram. W-21
23. What is the need of common bus? Draw common bus cycle. W-21
Unit 3 : Assembly Language Programming
1. Write an assembly language program to subtract two numbers. S-23, S-22, S-
21
2. Draw the flowchart for the first pass of assembler and explain the same in brief. S-23, S-22, S-
21, W-22, W-
21
3. Write assembly language program to add two numbers. S-22
4. Write assembly language program to multiply two numbers. S-22, S-19
5. Write the symbolic microprogram routine for the BSA instruction. Use the S-21
microinstruction format of basic microprogrammed control unit.
6. How many AND gates and Adders will be required to multiply a 5 bit number S-21
with a 3 bit number? Also say size of adder (bits). How many bits will be there
in the result?
7. Write an assembly language program to find the Fibonacci series up to the S-20
given number.
8. Write an assembly language program to find average of 15 numbers stored at S-20
 consecutive location in memory.
9. What is assembler? Draw the flowchart of second pass of the assembler. S-20, S-19
10. Justify the use of STA instruction in assembly program with an example. W-23
11. Apply BUN instruction in assembly program that needs to use a looped W-23
subroutine to check a flag.
12. Write assembly program for the arithmetic shift-left operation on a number W-23
stored in register B. Stop the program in case of overflow.
13. What is the fundamental difference between a subroutine call and an interrupt W-23
request? Analyze the possibility of common memory stack for both.
14. Write a program in assembly language to multiply two numbers in registers B W-23
and C in case the processor has only ADD instruction.
15. Write an Assembly level program for addition of 50 numbers. W-22
16. Write an Assembly level program to move one block of data to another W-22
location.
17. Differentiate assembly language and machine language. W-21
18. Write an assembly language program to find whether the given number is prime W-21
or not.
19. Write an assembly language program to find factorial of the given number. W-21
Unit 4 : Microprogrammed Control Organization
1. A computer uses a memory unit with 256K words of 32 bits each. A binary S-23
instruction code is stored in one word of memory. The instruction has four
parts: an indirect bit, an operation code, a register code part to specify one of 64
registers, and an address part.
1. How many bits are there in operation code, the register code part and the
address part?
2. Draw the instruction word format and indicate the number of bits in each
part.
3. How many bits are there in the data and address inputs of the memory?
2. Discuss microprogrammed control organization with a neat diagram. S-23
3. What is address sequencing? S-22, S-20, W-
21
4. State differences between hardwired control unit and Micro programmed S-21
control unit.
5. Explain using a flowchart how address of control memory is selected in S-21
microprogrammed control unit.
6. One hypothetical basic computer has the following specifications: S-20
Addressing Mods = 16
Total Instruction Types = 4 (IT1, IT2, IT3, IT4)
Each of the instruction type has 16 different instructions.
Total General-Purpose Register = 8
Size of Memory = 8192 X 8 bits
Maximum number of clock cycles required to execute one instruction
= 32
Each instruction of the basic computer has one memory operand and one
register operand in addition to other required fields.
a. Draw the instruction word format and indicate the number of bits in each
part.
b. Draw the block diagram of control unit.
7. Draw and explain 20 bits microinstruction code format. S-19
8. Which address sequencing capabilities are required in a control memory?
9. Explain the concept of Address Translation and working of the Translation W-23
Look-Aside Buffer
10. Discuss the importance of “control word” in a processor. W-23
11. Analyze the 20-bits microinstruction code format with 7 bit used for address. W-23
12. Sketch Microinstruction code format. Quote BR and CD field in brief W-22
13. Define followings: W-21
1. Control Memory
2. Control Word
3. Control Address Register
Unit 5 : Central Processing Unit
1. Enlist various kinds of addressing modes. Explain any five of the same and S-23
support your answer by taking small examples.
2. Write two address, one address and zero address instructions program for the S-23
following arithmetic expression:
X = (A + B) * (C – D / E) + F * G
3. Explain status bit conditions with a neat diagram. S-23
4. State the differences between RISC and CISC. S-23, W-22
5. Explain register stack. S-22
6. What is difference between two address and three address instructions? S-22
7. What is difference between direct and indirect addressing mode? S-22
8. Explain register stack and memory stack. S-21
9. Write a program to evaluate the arithmetic statement: S-21
A*B+C*D+E
i. Using an accumulator type computer.
ii. Using a stack organized computer.
10. List down six major characteristics of RISC processors. S-21, W-21
11 Enlist different status bit conditions. S-20
12. What is addressing mode? Explain direct and indirect addressing mode with S-20
example.
13. Compare and contrast RISC and CISC. S-20
14. In zero-address instructions format, how data from memory is accessed? S-19
Explain with example.
15. Explain RISC and CISC processor. S-19
16. Explain three-address, two-address and one-address instructions with example. S-19
17. Explain overlapped register windows. S-19
18. What is register stack? Explain Push operation. S-19
19. List addressing modes and explain any two of them. S-19
20. Differentiate between tightly coupled and loosely coupled systems. S-19
21. A subroutine return address can be stored in an index register instead of a stack. W-23
Analyze the advantages and disadvantages of both configurations.
22. Summarize following addressing modes with example. W-22
1) Implied mode 2) Register mode
23. Criticize Three-Address Instructions and Zero address instruction with common W-22
example.
24. What addressing mode means? Explain any three addressing modes in detail W-21
with example.
25. Write a program to evaluate X = (a*b)/c+d in two address and three address W-21
instruction formats.
 Unit 6 : Pipeline And Vector Processing
1. Explain Flynn’s classification for computers in brief. S-23, W-22
2. Explain pipeline conflicts in brief. S-23, S-20, W-
21
3. Write a note on the SIMD array processor. S-23
4. In certain scientific computations it is necessary to perform the arithmetic S-23
operation (Ai + Bi) * (Ci + Di) with a stream of numbers. Specify pipeline
configuration to carry out this task. List the contents of all registers in the
pipeline for i=1 through 4.
5. Explain arithmetic pipeline. S-22, S-20
6. Define pipelining. For arithmetic operation (Ai *Bi + Ci) with a stream of S-21
seven numbers (i=1 to 7). Specify a pipeline configuration to carry out this task.
7. A non-pipeline system takes to process a task. The same task can be processed S-21
in a six segment pipeline with a clock cycle of 10ns. Determine the speedup
ratio of the pipeline for 100 tasks. What is the maximum speed up that can be
achieved?
8. List and explain major instruction pipeline conflicts. S-21
9. Draw and explain 4-segment pipeline with space-time diagram. S-19
10. Summarize major hazards in pipelined execution. W-22
11. Demonstrate four-segment instruction pipeline in detail W-22
12. What is the significance of pipelining in computer architecture? Write a note on W-21
instruction pipeline.
Unit 7 : Computer Arithmetic
1. Assume A = + 6 and B = + 7, apply the Booth algorithm for multiplying A and S-23
B. Make necessary assumptions if required.
2. Perform A – B (subtract) operation for the following numbers using signed S-23
magnitude number format. (Write necessary assumptions if required)
A = + 11 and B = - 6
3. Explain booth’s multiplication algorithm with example. S-22, S-20, S-
19
4. Show the contents of registers E, AC, BR, QR and SC during the process of S-21
multiplying 11111 with 10101
5. Explain the non-restoring methods for dividing two numbers. S-21
6. Explain using flowchart the working of Booth’s multiplication algorithm of W-23
signed-2’s complement numbers.
7. Draw neat and clean flowchart for divide operation. Explain with example. W-21
Unit 8 : Input-Output Organization
1. Elaborate CPU-IOP communication. S-23, S-21
2. Explain DMA in brief. S-23, S-19
3. Write a note on asynchronous data transfer. S-22, S-21, S-
20
4. Discuss source-initiated transfer using handshaking in asynchronous data S-21
transfer.
5. Differentiate isolated I/O and memory mapped I/O. S-20, W-21
6. Write about Time-shared common bus interconnection structure. S-20
7. Explain the working of Direct Memory Access (DMA). S-20
8. Explain daisy chain arbitration. S-19
9. What is asynchronous data transfer? Differentiate between strobe control S-19
method and handshaking method.
10. Discuss various Dynamic Arbitration Algorithms for Inter-processor W-23
Arbitration.
11. Prepare flowchart of CPU-IOP communication. W-22
12. Which are the different ways to transfer data to and from peripheral devices? W-21
Explain any one of them in detail.
Unit 9 : Memory Organization
1. Write a detailed note on associative memory. S-23, S-20
2. Write a brief note on memory hierarchy. S-23, S-21, W-
23, W-22
3. Explain any two types of mapping procedures when considering the S-23
organization of cache memory.
4. What is RAM and ROM? S-22, S-20
5. Write a short note on virtual memory. S-22, W-21
6. Elaborate content addressable memory (CAM). S-21
7. What do you mean by cache memory? Justify the need of cache memory in S-21
computer systems.
8. What is cache memory address mapping? Which are the different memory S-20
mapping techniques? Explain any one of them in detail.
9. Differentiate between paging and segmentation techniques used in virtual S-20
memory.
10. Explain paging and address translation with example. S-19
11. What is cache memory? Explain how it enhances speed of accessing data? S-19
12. A RAM operates with 8-bit data bus, 2 chip select lines and 7-bit address lines. W-23
Calculate the number of such RAM chips required to have 512 bytes of main
memory.
13. An address space is specified by 24 bits and the corresponding memory space W-23
by 16 bits. How many words are there in the address space and in the memory
space?
14. How many 128 x 8 RAM chips are needed to provide a memory capacity of W-23
4096 bytes?
15. How many 128 x 8 RAM chips are needed to provide a memory capacity of W-23
4096 bytes?
16. What is cache memory? Interpret direct addressing mapping with diagram. W-22
17. List out modes of transfer. Formulate direct memory access technique in detail. W-22
18. What is cache memory address mapping? Compare and contrast direct address W-21
mapping and set-associative address mapping.
Unit 10 : Multiprocessors
1. Discuss cache coherence problem in detail. S-23, S-19, W-
21
2. Discuss multistage switching network with neat diagrams. S-21
3. Elaborate cache coherence problem with its solutions. S-21
4. Write a note on interprocess communication and synchronization. S-20
5. Discuss in brief the interconnection structures of a multiprocessor system. W-23