Session 2

The document provides guidelines for writing Verilog modules based on circuit diagrams, emphasizing naming conventions and data types for output ports. It outlines the importance of determining whether outputs are continuously driven or change with input, and details the process of naming wires for effective code writing. Additionally, it lists various combinational circuits such as encoders, multiplexers, and adders as examples.

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Session 2

Uploaded by

Ruturaj Nakum

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Session2

18 December 2024 15:04

How to write modules from diagram

Name of module or instance cannot start with a number

Literals for naming modules and variables and instances in verilog

To be able to describe circuit by looking at a its diagram, we need to first decide what data type output port will be
Will it be continuously driven?
Use of pre written gates or any submodule will continuously drive the output.
Or will it be changing at input changes (in procedural block)
Y=some_equation
While connecting gates or different submodules according to the provided diagram, we need to first name the number of wires required
Naming wires will help in writing the code for it.
Pre written gates have single output but some gates may have multiple inputs. To be able to connect correct signal to ip or op, rule is
that, we connect output signal first. Then rest of the inputs can be connected
Combinational ciruits
8to3 encoder
4x1 mux
1x4 demux
Excess3 to decimal code converter
2 bit adder
Full adder using half adder and required extra circuitory

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Session 2

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Session 2

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Session2

18 December 2024 15:04

How to write modules from diagram

Name of module or instance cannot start with a number

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