Session1
17 December 2024 14:58
HDL
Hardware Description Language
Digital circuit
Inputs
Outputs
Internal logic
HDL
Coding language that describes behavior of a digital circuit
Why do we need HDL
We need parallel execution in digital ckt description
Eg. Verifying memory element will require clock signal running parallelly and allowing data to be stored
wrt a particular clock edge
Hardware like data types
Reg types
Net types (wires)
Time consumption mimicking
Time consumption to wait for a particular event to occur for functionality to be executed
Metastable states
x don't care state, z high impedance state
Data types
For data storage
Attribute for interpretation of the value
real 32 bit decimal data type no metastable states
time 32 bit +ve data type no metastable states
realtime
integer 32 bit data type metastable states available
String is not a required in hardware description because we cannot provide characters to digital ckt.
ASCII code is binary representation of characters
reg : it stores previously provided value unless specifically updated. It is single bit data type.
x,z,0,1 possible values
net : wire
x,z,0,1 possible values
It gets driven by a particular ckt continuously. We cannot change it's value at any given time. Ckt drives the
value for this data type
wor
wand or output
tri
reg a;
wire b;
//procdure
a=0; //allowed
//adder_ckt(.out1(b),….)
b=0; //not allowed
Behavioral modelling
Describing the functionality of the circuit in logic
using a procedural block
Data flow modelling
Circuit is described with equation.
Continuously evaluating RHS variables and assigning output
Structural modelling / gate level modelling
Main module created using multilple types of submodules or multiple submodules of same type.
You generally define a circuit within module endmodule
module adder(a,b,sum,cout);
input a,b;
output reg sum, cout;
//following is always procedural block
always@(a,b)begin //a,b is called as sensitivity list
{cout,sum}= a+b;
//LHS above is concatenation
//LHS has size of 2 bits
end
endmodule
A B Cout Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
module adder_DF(a,b,sum,cout);
input a,b;
output sum, cout;
assign sum=a^b; //^ means xor operator
assign cout=a&b; //& means anding operator
endmodule
To verify described circuit, we need to setup something called as verification environment
Functionality of a testbench is to provide all possible input stimulus and observe corresponding outputs (if reference output
for those combination input are available, compare with them )
With 2 total inputs, we have 4 possible input combinations
If I have 15 total inputs, we have 2^15 possible input combinations
HW: look up what all data types available in verilog
How to use data types
What all discussed concepts are synthesizable and what all are not synthesizable
Why do we need non synthesizable constructs in verilog
Can we verify design for all possible input combinations?
Try and write single bit subtractor
Whatever keyword and concepts we have seen today, try going thru their theory in websites mentioned
