ELEC 335

Digital Logic Design

Exclusive OR / NOR
& Adders & Comparators

4–1 ELEC 335, Digital Logic Design, UAE University

 Outline
• Exclusive OR / NOR
• Parity Generator
• Parity Checker
• Adders
• Binary Ripple Adder
• Overflow Checking
• BCD Adder

4–2 ELEC 335, Digital Logic Design, UAE University

 Exclusive OR and exclusive NOR
• Two special logic circuits that occur quite often in
digital systems are the exclusive-OR and exclusive-
NOR circuits
XOR Truth Table XNOR Truth Table

A B XOR A B XNOR
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

A + B = AB + AB A+ B = A B + A B
4–3 ELEC 335, Digital Logic Design, UAE University
 XOR and XNOR
• X +Y = XY + XY
• X + Y = XY + X Y
• X + Y = XY + XY = XY ⋅ XY = (X+Y)(X+Y)
= X Y + XY
• XOR properties
1) X+ 0 = X X +1 = X
2) X+X = 0 X+X = 1
3) X + Y = X +Y X + Y = X +Y
4) X + Y = Y +X
5) (X + Y) + Z = X +(Y +Z)
4–4 ELEC 335, Digital Logic Design, UAE University
 XOR and XNOR symbols

A AB + AB
B =1

A AB + AB
B =1

Traditional symbol IEEE/ANSI symbol

4–5 ELEC 335, Digital Logic Design, UAE University

 Parity Generator
• When transmitting n bits of information from one
place to another, often a parity bit is used to detect
a single bit error

Information n bits n + 1bits Transmit

to be Parity generator n bits plus a
transmitted parity bit

4–6 ELEC 335, Digital Logic Design, UAE University

 Parity checker
• On the receiving side, the parity of the received
information is checked to make sure no error
occurred

Received n +1 bits ERROR report

information Parity checker
(n + 1) bits

4–7 ELEC 335, Digital Logic Design, UAE University

 Three bit even parity generator

1 x 0
1 y p 1
1 z

p = 1 if x, y, and z have odd parity, therefore the parity of x, y, z

and p is always even

z 1
y 0
x 1 Transmit
1 x 1
0 y p 0
1 z

4–8 ELEC 335, Digital Logic Design, UAE University

 Four bit even parity checker

1 x 0 1
1 y Error
1 z 1
0 p

If output is 1 then there was an error

If output is 0 then there was no error

4–9 ELEC 335, Digital Logic Design, UAE University

 Digital Logic Design

Half Adder

Add two binary numbers Dec Binary

● A0 , B0 → single bit inputs
1 1
+1 +1
● S0 → single bit sum
● C1 → carry out
2 10

A0 B0 C1 S0 A0
0 0 0 0
S0
B0
0 1 0 1
1 0 0 1
C1
1 1 1 0
 Digital Logic Design

Multiple-bit Addition

Consider adding a 4-bit number to a 4-bit number:

(single-bit adder are used for each bit position)
A3 A2 A1 A0 B3 B2 B1 B0
A 0 1 0 1 B 0 1 1 1

1 1 1 Ci+1 Ci
A 0 1 0 1 Ai
B 0 1 1 1 +Bi
1 1 0 0 Si
Each bit position creates a sum and carry
 Digital Logic Design

Full Adder

Full adder includes a carry−in Ci

(Notice interesting pattern in Karnaugh map)

Ci Ai Bi Ci+1 Si AiBi
Ci 00 01 11 10
0 0 0 0 0
0 0 1 0 1 0 1 1
0 1 0 0 1
1 1 1
0 1 1 1 0
1 0 0 0 1 Si
1 0 1 1 0
Si = Ci Ai Bi + Ci Ai Bi + Ci Ai Bi + Ci Ai Bi
1 1 0 1 0
1 1 1 1 1
 Digital Logic Design

Full Adder

Reduce AND/OR representations into XORs

Si = Ci Ai Bi + Ci Ai Bi + Ci Ai Bi + Ci Ai Bi
= Ci (Ai Bi + Ai Bi ) + Ci (Ai Bi + Ai Bi )
= Ci (Ai ⊕ Bi ) + Ci (Ai  Bi )
= Ci (Ai ⊕ Bi ) + Ci (Ai ⊕ Bi )
= Ci ⊕ Ai ⊕ Bi
 Digital Logic Design

Full Adder

Now consider implementation of carry−out

Ci Ai Bi Ci+1 Si
AiBi
Ci 00 01 11 10
0 0 0 0 0
0 1
0 0 1 0 1
0 1 0 0 1 1 1 1 1
0 1 1 1 0
1 0 0 0 1 Ci+1
1 0 1 1 0
Ci+1 = Ai Bi + Ci Bi + Ci Ai
1 1 0 1 0
1 1 1 1 1
 Digital Logic Design

Full Adder

Any relation to the SUM? AiBi

Ci 00 01 11 10
Ci+1 = Ai Bi + Ci Ai Bi + Ci Ai Bi 0 1
= Ai Bi + Ci (Ai Bi + Ai Bi )
1 1 1 1
= Ai Bi + Ci (Ai ⊕ Bi)
Ci+1
Final Equations:
Si = Ci ⊕ Ai ⊕ Bi

Ci+1= Ai Bi + Ci (Ai ⊕ Bi)

 Digital Logic Design

Full Adder

Full adder made of two half adders

Si = Ci ⊕ Ai ⊕ Bi Ci+1= Ai Bi + Ci (Ai ⊕ Bi)

Ci
Ai Si
Bi

Ci+1

Half-adder
Half-adder
 Digital Logic Design

Full Adder

Hardware repetition simplifies hardware design

Ci Si
half-adder
Ai S C
half-adder C i+1
Bi
C

A full adder can be made from

two half adders (plus an OR gate)
 Digital Logic Design

Full Adder

Putting it all together

● Single-bit full adder
Ai Bi
● Common piece of
computer hardware

Ci+1 Full Adder Ci

Si
Block Diagram
 Digital Logic Design

4-Bit Adder

Chain single-bit adders together

• What does this do to delay?

A3 B3 A2 B2 A1 B1 A0 B0

Full Adder Full Adder Full Adder Full Adder 0

C3 C2 C1

C4 S3 S2 S1 S0

C 1 1 1 0
A3A2A1A0 B3B2B1B0
A 0 1 0 1
Cout 4-bit Binary Adder Cin
B 0 1 1 1 S3S2S1S0
S 1 1 0 0
 Digital Logic Design

Negative Numbers – 2’s Complement

● Subtracting a number is similar
● Perform 2’s complement
● Perform addition

● Can we augment the adder with 2’s complement

hardware?

A3 A2 A1 A0
+ B3 B2 B1 B0
+ 1
 Digital Logic Design

4-bit Subtractor

A3 B3 A2 B2 A1 B1 A0 B0

Full Full Full Full

1
Adder Adder C2 Adder C1 Adder
C3

C4 D3 D2 D1 D0
 Digital Logic Design

Adder- Subtractor Circuit

 Overflow Checking
• When two numbers are added or subtracted, we must
check if an overflow has occurred
• Overflow conditions for unsigned and signed numbers are
different
• For unsigned numbers, there is an overflow if there is a
carry out of the most significant bit for addition or if
there is a borrow into the most significant bit for
subtraction
• For signed numbers, there is an overflow if the sign of the
result is different than the sign of expected result. Another
way to check for this is if the carry out of the most
significant bit is not equal to the carry into the most
significant bit, then there is an overflow

4–23 ELEC 335, Digital Logic Design, UAE University

 Examples (unsigned)
• Add the following 8 bit numbers
10101101 10001001
+ +
01111000 00110101
1 00100101 10111110

Carry out of most significant bit indicates an overflow

No carry out of most significant bit, therefore no overflow

4–24 ELEC 335, Digital Logic Design, UAE University

 Examples (signed)
Different (overflow) Different (overflow)

0 1 11 1 0 01
0111 1001
+ +
0111 1001
1110 10010
Same (no overflow) Same (no overflow)

0 0 00 1 1 00
0010 1110
+ +
0001 1101
0011 11011
4–25 ELEC 335, Digital Logic Design, UAE University
 Checking for overflow

V Cn-1

Cn N –bit add/sub
C

4–26 ELEC 335, Digital Logic Design, UAE University

 Digital Logic Design

Comparators

The function of a comparator is to compare the magnitudes of two

binary numbers to determine the relationship between them. In the
simplest form, a comparator can test for equality using XNOR gates.
How could you test two 4-bit numbers for equality?

AND the outputs of four XNOR gates.

A1
B1
A2
B2 Output
A3
B3
A4
B4
1. For the full-adder shown, assume the input bits are as
shown with A = 0, B = 0, Cin = 1. The Sum and Cout will be
a. Sum = 0 Cout = 0
Σ Σ Sum
b. Sum = 0 Cout = 1 0 A Σ A Σ

c. Sum = 1 Cout = 0 0 B Cout B Cout

d. Sum = 1 Cout = 1 1
Cout
2. The output will be LOW if
a. A < B A1
B1
b. A > B A2 Output
B2
c. both a and b are A3
correct B3
A4
d. A = B B4