Assignment 2
You would be designing a structural Verilog model of a 32-bit ALU as part of this assignment. The architecture of ALU
consists of a set of basic logic gates, a carry look ahead adder , a barrel shifter and a set of multiplexors connected
in the schematic shown below. You need to model each of these modules individually and then instantiate them
into the top level ALU design. The inputs of ALU include two 32-bit data A and B, and a 4-bit alucntrl
(aluc). Three multiplexers are used: two 2-to-1 multiplexers and a 4-to-1 multiplexer. Their selection signals use
some bit(s) of aluc. The component of adder performs ADD or SUB based on aluc[2]. The component of shift
performs SLL, SRL, or SRA, based on aluc[3:2]. Three kinds of logic gates perform AND, OR, and XOR,
respectively. LLI (Load Lower Immediate) can be done by wiring upper 16 bits to lower 16 bits of B input The
outputs of the ALU are a 32-bit r (result).
a. Design a behavioral model of a 32-bit 4x1 and 32-bit 2x1 multiplexors using the case statement. Ensure a
latch free design.
b. Design a 32 bit barrel shifter that shifts 32-bit input, left or right by 5 bits, based on a control input (A[4:0]).
The barrel shifter should provide logical left, logical right operations, by inserting zeroes in the shifted bit
positions and an arithmetic right operation that replicates the sign bit in the shifted bit positions. The
four inputs to barrel shifter comprise of shift value, sv (5 bits, taken from 32 bits of input A), 32-bit data
input( B), 2-bits control input to select between logical and arithmetic operations. Use Verilog shift
operators [<<, >>, $signed(input)] to implement shift operations. For example,
• Data: 00000000_11111111_00000000_11111111
• Logical left shift (by five bits): 00011111_11100000_00011111_11100000
• Logical right shift (by five bits): 00000000_00000111_11111000_00000111
• Arithmetic right shift (by five bits): 00000000_00000111_11111000_00000111
c. Design a 32-bit carry look ahead adder. It has two inputs A and B, each of 32 bits and one 1-bit “enable
input”. The sum and carry out of CLA is given as:
• Si = Pi ⊕ Ci
• Ci + 1 = Gi + Pi * Ci, where, Gi = AiBi and Pi = Ai ⊕ Bi are called carry generate and carry propagate
respectively. These equations show that a carry signal will be generated in two cases:
i. if both bits Ai and Bi are 1
ii. if either Ai or Bi is 1 and the carry-in Ci is 1.
• If you apply these equations to a 4-bit adder:
i. C1 = G0 + P0C0
ii. C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
iii. C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
iv. C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
• These expressions show that C2, C3 and C4 do not depend on its previous carry-in. Therefore C4
does not need to wait for C3 to propagate. As soon as C0 is computed, C4 can reach steady state.
The same is also true for C2 and C3.
MUX
A[31:0]
B[31:0] ADDER
ALU Cntrl[3:0]
ALUC [2] OUT[31:0]
ALUC [2]
AND_Out
MUX
OR_Out
XOR_Out
LLI_Out MUX
B [15:0]
ALUC [2]
A [4:0]
ALUC [2] SHIFTER
ALUC [3]
ALUC [1:0]
ALUC Operation
x000 ADD
X100 SUB
X010 XOR
X001 AND
X101 OR
X110 LLI
0011 SLL
0111 SRL
1111 SRA
