MODULE II

PROGRAMING OF MICROCONTROLLERS AND ITS APPLICATIONS

I. ADDRESSING MODES OF 8051 :

The way the data sources or destination addresses are specified in the Mnemonic
that moves that data is called the 'addressing mode.

The following are the 6 addressing modes of 8051

1. Direct Addressing Mode.

2. Indirect Addressing Mode.

3. Register Addressing Mode

.
4. Register Specific (Register Implicit) Addressing Mode.

5. Immediate Addressing Mode.

6. Indexed Addressing Mode.

1. Direct Addressing Mode :

 In this addressing Mode, the operands are specified used the 8-bit address field
 in the instruction format.
 Only internal data RAM and SFRS can be directly addressed.
 Example : MOV R., 90H,Here 90H is address of a SFR P1.

2.Indirect Addressing Mode :

 In this addressing Mode, the 8-bit address of an operand is stored in a register and instead of the
8-bit address, is specified in the instruction.
 The registersR0 to R7 of the selected bank of registers or stack pointer can be used as address
registers for storing the 8-bit address.
 The address register for 16-bit addresses can only be 'data pointer' (DPTR).
 Example : ADD A @R

3.Register Addressing Mode:

 In this addressing mode, operands are stored in the registers R0 to R7 of the selected register
bank.
 One of these 8 registers (R0.-R7) is specified in the instruction using the 3-bit register
specification field of the opcode format.
 A register bank can be selected using the two bank select bits of the PSW.!
 Example : ADD A, RS.

4.Register Specific (Register Implicit) Addressing Mode:

 In this mode, the operand is implicitly specified using one of the registers.
 Some of the instructions always operate only on a specific register.
 These type of instructions fall under this mode.
 Example: RRA,This instruction rotates accumulator right.
5.Immediate Addressing Mode:

 In this mode, an immediate data, i.e., a constant is specified in the instruction, after the opcode
byte.
 Example : MOV A, # 120, The immediate data 120 (decimal) is loaded into the accumulator.
 For specifying a hexadecimal number in this type of instruction, it should be followed by “#” sign
.
6. Indexed Addressing Mode :

 Only program memory can be accessed using this mode.

 Basically, this addressing mode is accomplished in 8051 for look-up table manipulations.
 Program counter or data pointer are the allowed 16-bit address storage, in this mode of
addressing.
 These 16-bit registers point to the base of the look-up table and the accumulator contains a code
to be converted using the look-up table i.e., it contains the relative address of the code in the look-
up table.
 The look-up table address is found out by adding the contents of accumulator with that of the
program counter or data pointer. In case of jump instruction, the contents of accumulator are
added with one of the specified 16-bit registers to form the jump destination address.
 Example : MOVCA, @ A+ DPTR
JMP@ A + DPTR

II. INSTRUCTION SET OF 8051

 The MCS - 51 instruction set includes 111 instruction, 49 of which are 45 two-byte and 17 three
byte.
 The instruction opcode format consists mnemonic followed by a "destination, source" operand
field.

 The 8051 (MCS - 51) instruction set is divided into four,

i. Data transfer
ii. Arithmetic
iii. Logic
iv. Control Transfer

i. Data Transfer :
Data transfer operations are divided into three classes :

a) General purpose
b) Accumulator – Specific
c) Address-Object

General - Purpose Transfers :

 MOV performs a bit or byte transfer from the source operand to the operand
 PUSH increments the SP register and then transfers a byte from operand to the stack location
currently addressed by SP.
 POP transfer a byte operand from the stack location addressed destination operand and then
decrements SP.

Accumulator Specific Transfer :

 XCH exchanges the byte source operand with register A (accumulator)

 XCHD exchanges the low-order nibble of the byte source operant low-order nibble of A.
  MOVX performs a byte move between the External Data Memory and the accumulator.
 The external address can be specified by the DPTR register (16-bit) or the R1 and RO register (8-
bit).
 MOVC moves a byte from Program memory to the accumulator. The operand in A is used as an
index into a 256-byte table pointed to by the base register (DPTR or PC). The byte operand
accessed is transferred to the accumulator.

Address-Object Transfer :

 MOV DPTR, # data loads 16-bits of immediate data into a pair of destination DPH and DPL.

Arithmetic :

The 8051 has four basic mathematical operations. Only 8-bit operations using usigned arithmetic are
supported directly. The overflow flag, however, permits the addition and subtraction operation to serve for
both unsigned and signed binary integers
Arithmetic can also be performed directly on packed decimal (BCD) representations.

1. Addition :

 INC (increment) adds one to the source operand and puts the result in the operand. ADD adds A
to the source operand and returns the result to A.
 ADDC (add with Carry) adds A and the source operand, then adds one (1) if CY is set, and puts
the result in A.
 DA (decimal - add-adjust for BCD addition) corrects the sum which results from the binary
addition of two two-digit decimal operands. The packed decimal sum formed by DA is returned to
A. CY is set if the BCD result is greater than 99, otherwise it is cleared.
 Eg:- ADD A,B ; add the accumulator data with data in B register

2. Subtraction :

 SUBB (subtract with borrow) subtracts the second source operand from the first operand (the
accumulator), subtracts one(1) ifCY is set and returns the result to A
 DEC (decrement) subtracts one(1) from the source operand and returns the result into the operand.
 Eg:- SUBB A,B ; subtract data in B register from Accumulator

Multiplication :

 MUL performs an unsigned multiplication of the A register by the B register,

returning a double-byte result.
 A receives the low-order byte, B receives the high-order byte.
 Eg:- MUL AB ; multiply the data in A with B

Division:-

 DIV performs an unsigned division of the A register by the B register and returns the integer
quotient to A and returns the fractional remainder to the B register.
 Division by zero leaves indeterminate data in registers A and B and sets OV; otherwise OV is
cleared. CY is cleared. AC is unaffected.
 Eg:- DIV AB ; divide data in A by B
Logic :

 The 8051 performs basic logic operations on both bit and byte operands.

a) Single - Operand Operations :

 CLR set A or any directly addressable bit to zero (O).

 SETB sets any directly addressable bit to one (1).
 CPL is used to compliment the contents of the A register without affecting anyflags or any
directly addressable bit location.
 RL, RLC, RR,RRC, SWAP are the five rotate operations that can be performat
on A,
 RL, rotate left,
 RR. rotate right,
 RLC, rotate left through C,
 RRC. Rotate right through C, and
 SWAP, rotate left four.
 For RLC and RRC the CY flag become equal to the last bit rotated out.
 SWAP rotates A left four places to exchange bits through 0 with bits 7 through 4.

b) Two - Operand Operations :

 ANL performs bit wise logical AND of two source operands (for both bit and byte operands) and
returns the result to the location of the first operand.
Eg:- ANL A,B

 ORL performs bit wise logical OR of two source operands (for both bit and byte operands) and
returns the result to the location of the first operand.
Eg:- ORL A,B

 XRL performs bit wise logical XOR of two source operands (byte operands) andreturns the result
to the location of the first operand.

Control Transfer :

 There are three classes of control transfer operations;

 unconditional calls, returns and jumps; conditional jumps, and interrupts.
 All control transfer operations cause, some upon a specific condition, the program execution to
continue at a non-sequential location in program memory.

UNCONDITIONAL CALLS, RETURNS AND JUMPS :

 Unconditional calls, returns and jumps transfer control from the current value of the Program
Counter to the target address. Both direct and indirect transfer are supported.
 ACALL and LCALL push the address of the next instruction onto the stack and then transfer
control to the target address. ACALL is a 2-byte instruction that addresses the full 64K program
space.
 RET transfers control to the return address saved on the stack by a previous call operation and
decrements the SP register by two (2) to adjust the SP for the popped address
 AJMP, LJMP and SJMP transfer control to the target operand. The operation of AJMP and LJMP
are analogous to ACALL and LCALL. The SJMP (short jump) instruction provides for transfer
within a 256-byte range centered about the starting address of the next instruction ( - 128 to
+127)..

.
Conditional Jumps :

 Conditional jumps perform a jump contingent upon a specific condition. The destination will be
within a 256-byte range centered about the starting address of the next instruction (-128 to +127).

 JZ performs a jump if the accumulator is zero.

 JNZ performs a jump if the accumulator is not zero.
 JC performs a jump if the carry flag is set.
 JNC performs a jump if the carry flag is not set.
 JB performs a jump if the Direct Addressed bit is set.
 JNB performs a jump if the Direct Addressed bit is not set.
 JBC performs a jump if the Direct Addressed bit it set and then clears the
 CJNE compares the first operand to the second operand and performs a jump if they are not equal.
CY is set if the first operand is less than the second operand; otherwise it is cleared. Comparisons
can be made between directly addressable bytes in Internal Data Memory of between an
immediate value
 DJNZ decrements the source operand and returns the result to the operand. A jump is performed
if the result is not zero. The source operand of the DJNZ instruction may be any byte in the
Internal Data Memory.

Interrupt Returns :

RET transfers control as does RET, but additionally enables interrupts of the current priority level.

SIMPLE ASSEMBLY LANGUAGE PROGRAMS:-

Program 1 : 8-Bit Addition :

(a) Without Carry:

MOV A, #25 1st data

MOV B, #12 2nd data
ADD A, B
MOV RO, A
RET

(b) With Carry:

MOV A, # data 1
MOV B, # data 2
SETB C
ADDC A, B
MOV RO, A
RET

Program 2: 8-Bit Subtraction :

MOV A, # data 1
MOV B, # data 2
SUBB A, B
MOV RO, A
RET

Program 3: 8-Bit Multiplication :

MOV A, # data 1
MOV B, # data 2
MUL AB
MOV RO,
MOV R1, B
RET

Program 4: 8-Bit Division :

MOV A, # data 1
MOV B, # data 2
DIV AB
MOV RO, A( Quotient)
MOV R1, B (Remainder0
RET

Program 5: l's Complement (NOT Operation) :

MOV A, # data
CPL A
MOV RO, A
RET

Program 6: 2's Complement:

MOV A, # data
CPL A
INCA
MOV RO, A
RET

Program 7: SWAP Operation :

MOV A, # data
SWAP A
MOV RO, A
RET

TIMING & DELAY SUBROUTINES :

The basic principle of delay generation by software means is to load some appropriate value in a
register or register pair. Then a program loop is setup to decrement the register or register pair in each
pass through the loop. The looping continues until the contents of the register or register pair are zero.)
The delay obtained by this process depends on the initial value of the register and the time needed for
executing the instructions within the loop.

Counter :

 It is defined to provide the track of events.

 It is designed by loading an appropriate number into one of the register and using INR or DCR
instructions.
 To update the count and to check the final count, a loop has to be established. This is shown in
figure
Time - delay :

 It is a specific procedure defined by a loaded register with an appropriate number depending

upon the time - delay required.
 Then the register is decremented until it reaches zero. It is shown in the Fig. 2.7. Note that the
loop causes the delays, depending upon the clock period of the system and time required to
execute the instructions in the loop.

Counter with time delay :

By combining the techniques illustrated in the Figure . a counter with time delay can be
designed.It can be used to provide the track of events with an appropriate time interval.

TIME DELAY CALCULATION

A delay subroutine consists of two parts:

1) Setting a counter
2) a loop

 Most of the time delay is performed by the body of the loop.

 For three different 8051 - based systems period of machine cycle is calculated the basis
of crystal frequency as follows
a) 11.0592/12 = 921.6 kHz; Machine Cycle is 1/921.6 kHz = 1.085 microsecond
(b) 16 MHz/12 = 1.333 MHz; Machine Cycle (MC) = 1/1.333 MHz = 0.75 ms
(c) 20 MHz/12 = 1.66 MHz; MC = 1/1.66 MHz = 0.60 ms
LARGEST NUMBER IN AN ARRAY