Thanks to visit codestin.com
Credit goes to www.scribd.com

0% found this document useful (0 votes)
36 views21 pages

S01 - GM Over Id Based Design Methodology

The document presents a gm/ID based design methodology for CMOS analog circuits, focusing on amplifier design procedures and performance metrics. It outlines a general design procedure, including selecting parameters such as channel length and transconductance efficiency, and provides a design example for a common source amplifier. The design example details the calculations for various specifications, including gain and frequency response, using a 45nm process.

Uploaded by

asd2859242119
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
36 views21 pages

S01 - GM Over Id Based Design Methodology

The document presents a gm/ID based design methodology for CMOS analog circuits, focusing on amplifier design procedures and performance metrics. It outlines a general design procedure, including selecting parameters such as channel length and transconductance efficiency, and provides a design example for a common source amplifier. The design example details the calculations for various specifications, including gain and frequency response, using a 45nm process.

Uploaded by

asd2859242119
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

Special Lecture 1

전자회로
- A gm/ID based Design Methodology -

University of Seoul
School of Advanced Fusion Studies

Min-Jae Seo
[email protected]
Common Design Procedure
❑ Single Stage Amplifier
➢ F. Silveira, D. Flandre and P. G. A. Jespers, "A gm/ID based methodology for the
design of CMOS analog circuits and its application to the synthesis of a silicon-on-
insulator micropower OTA," in IEEE Journal of Solid-State Circuits, vol. 31, no. 9, pp.
1314-1319, Sept. 1996, doi: 10.1109/4.535416.

❑ Differential Amplifier
➢ P. R. Gray and R. G. Meyer, "MOS operational amplifier design-a tutorial overview,"
in IEEE Journal of Solid-State Circuits, vol. 17, no. 6, pp. 969-982, Dec. 1982, doi:
10.1109/JSSC.1982.1051851.

2
A gm/ID based
Design Methodology
Introduction
❑ Key Parameters for an Amplifier Design
➢ Conventional → Overdrive voltage

𝑔𝑚 𝐼𝐷
➢ New → VS
𝐼𝐷 𝑊/𝐿

❑ The reason why we use gm/Id design methodology


1. It is strongly related to the performances of analog circuits.
2. It gives an indication of device operating region.
3. It provides a tool for calculating the transistors dimensions.

4
Performance Metrics of Interest
❑ Transit Frequency (𝒘𝒕 , or Unity gain frequency 𝒘𝒖 )
➢ The maximum frequency for amplifying operation
𝒈𝒎
𝒘𝒕 =
𝑪𝒈𝒈

❑ 3-dB Frequency (𝒘−𝟑𝒅𝒃 )


𝟏 𝟏
𝒘−𝟑𝒅𝑩 = 𝒇−𝟑𝒅𝑩 =
𝑹𝒐𝒖𝒕 𝑪𝑳 𝟐𝝅 ∙ 𝑹𝒐𝒖𝒕 ∙ 𝑪𝑳

❑ Intrinsic Gain (𝑨𝟎 )


𝒈𝒎
𝑨𝟎 = 𝒈𝒎 𝒓𝟎 =
𝒈𝒅𝒔

5
Performance Metrics of Interest – ( II )
❑ Transconductance Efficiency
➢ It is the efficiency of the MOS transistor to translate given current into an equivalent
transconductance
𝒈𝒎
[𝐒/𝐀]
𝑰𝑫
❑ Current Density

𝑰𝑫 𝑰𝑫
[𝐀/□] or [𝐀/𝐮𝐦]
𝑾/𝑳 𝑾

6
Design Tradeoff: gm/Id versus wt
❑ Vgs (Vov) sweep

High Power Efficiency High Speed

7
Design Tradeoff: gm/Id versus wt – ( II )
❑ Product of gm/Id and wt
➢ Optimal Point?

8
General Design Procedure
1. Determine gm (from design objectives)

2. Pick L
➢ Short channel → high speed, large mismatch
➢ Long channel → high intrinsic gain, small mismatch

3. Pick gm/ID(or wt)


➢ Large gm/ID → low power, large signal swing
➢ Small gm/ID → high speed

4. Determine ID (from gm and gm/ID)

5. Determine W (from ID/W, current density chart)

9
In Our Lab.. (GPDK 45nm Process)
1. Pick L

2. Pick gm/ID(or wt)

3. Determine gm (from design objectives)

4. Determine ID (from gm and gm/ID)

5. Determine W (from ID/W, current density chart)

10
In Our Lab.. (GPDK 45nm Process) – ( II )
1. Pick L = 0.5um
➢ Considering threshold voltage (Vth) variation

2. Pick gm/ID(or wt) = 10


➢ Considering the operating region(moderate inversion), gain and speed

wt
gm/Id

11
In Our Lab.. (GPDK 45nm Process)
1. Pick L = 0.5um
2. Pick gm/ID(or wt) = 10
3. Determine gm (from design objectives)
𝟏
𝒇−𝟑𝒅𝑩 = , 𝑨 = 𝒈𝒎 𝑹𝒐𝒖𝒕
𝟐𝝅 ∙ 𝑹𝒐𝒖𝒕 ∙ 𝑪𝑳 𝒗
4. Determine ID (from gm and gm/ID)
➢ ID = gm/10 → ‘10’ is our value
5. Determine W (from ID/W, current density chart)
➢ ID/W = 8.3 @ gm/ID = 10
➢ W = ID/8.3

12
Design Example
Design Example
❑ Design Target
➢ Common Source(CS) Amplifier

Specification
Process TT
Voltage (VDD) 1.8V
Temperature 25ºC
Av -5
f-3dB 100MHz
CL 5pF

14
Design Example – ( II )
1. Pick L = 0.5um
2. Pick gm/ID(or wt) = 10
3. Determine gm (from design objectives)

① Rout from 3-dB frequency


𝟏
𝒇−𝟑𝒅𝑩 = = 𝟏𝟎𝟎𝐌𝐇𝐳 @ 𝑪𝑳 = 𝟓𝒑𝑭
𝟐𝝅 ∙ 𝑹𝒐𝒖𝒕 ∙ 𝑪𝑳
𝟏
∴ 𝑹𝒐𝒖𝒕 = = 𝟑𝟏𝟖. 𝟑𝒐𝒉𝒎
𝟐𝝅 ∙ 𝒇−𝟑𝒅𝑩 ∙ 𝑪𝑳

② gm from gain equation

𝑨𝒗 = −𝒈𝒎 𝑹𝒐𝒖𝒕 = −𝟓
𝑨𝒗
∴ 𝒈𝒎 = − = 𝟏𝟓. 𝟕 𝒎𝑺
𝑹𝒐𝒖𝒕

15
Design Example – ( III )
1. Pick L = 0.5um
2. Pick gm/ID(or wt) = 10
3. Determine gm = 15.7 mS
4. Determine ID (from gm and gm/ID)
➢ Because gm/ID is 10 and gm 15.7 mS ➔ ID = 1.57mA
5. Determine W (from ID/W, current density chart) = ID/8.3 = 189um
y축 : ID/W Vgs = Sweep
Vds = 0.9

ID/W = 8.3 @ gm/ID = 10

from SPICE simulation x축 : gm/ID

16
Design Example – ( IV )
1. Pick L = 0.5um
2. Pick gm/ID(or wt) = 10
3. Determine gm = 15.7 mS
4. Determine ID (from gm and gm/ID) = 1.57mA
5. Determine W (from ID/W, current density chart) = 189um

Specification
= 318.3ohm? Process TT
Voltage (VDD) 1.8V
Temperature 25ºC
Av -5
W = 189um f-3dB 100MHz
L = 0.5um
CL 5pF

17
Design Example – ( V )
❑ Determine Rd
➢ Rout ≠ Rd
➢ Rout = 𝑅𝑑 ∥ 𝑟0 = 𝑅𝑑 ∥ 1/𝑔𝑑𝑠 → 318.3 = 𝑅𝑑 ∥ 607𝑘
➢ Rd = 318.5

y축 : ro = 1/gds from SPICE simulation


Vgs = Sweep
Vds = 0.9

607kohm

x축 : gm/ID

18
Design Example – ( VI )
1. Pick L = 0.5um
2. Pick gm/ID(or wt) = 10
3. Determine gm = 15.7 mS
4. Determine ID (from gm and gm/ID) = 1.57mA
5. Determine W (from ID/W, current density chart) = 189um

Specification
= 318.5ohm Process TT
Voltage (VDD) 1.8V
Temperature 25ºC
Vb = 0.6V Av -5

W = 189um f-3dB 100MHz


L = 0.5um CL 5pF

19
Design Results
❑ Schematic & Testbench

20
Design Results – ( II )
❑ Schematic & Testbench

Av = 13.4dB = 4.7
@ Low frequency
Av = 10.6dB
@ -3dB frequency 100MHz

21

You might also like