ECEN474/704: (Analog) VLSI Circuit Design

Spring 2018

Lecture 7: Table-Based (gm/ID) Design

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements & Agenda
• Reading
• gm/ID paper and book reference on website
• Material is only supplementary reference

• Technology characterization for design

• Table-based (gm/ID) design example
• Adapted from Prof. B. Murmann (Stanford)
notes

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How to Design with Modern Sub-Micron
(Nanometer) Transistors?
• Hand calculations with square-law model can deviate
significantly from actual device performance
• However, advanced model equations are too tedious for design

• Tempts designers to dive straight to simulation with little

understanding on circuit performance trade-offs
• “Spice Monkey” approach

• How can we accurately design when hand analysis

models are way off?
• Employ a design methodology which leverages
characterization data from BSIM simulations

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 The Problem

[Murmann]

4
 The Solution

[Murmann]

5
Technology Characterization for Design
• Generate data for the following over a reasonable range
of gm/ID and channel lengths
• Transit frequency (fT)
• Intrinsic gain (gm/gds)
• Current density (ID/W)
• Also useful is extrinsic capacitor ratios
• Cgd/Cgg and Cdd/Cgg
• Parameters are (to first order) independent of transistor
width, which enables “normalized design”
• Do design hand calculations using the generated
technology data
• Still need to understand how the circuit operates for an
efficient design!!!
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gm/ID
• These plots tell us how much
transconductance (gm) we
can get for a given current
(ID)

• The transistor is a more

efficient transconductor at
low overdrive voltages

• A main trade-off will be the

transistor frequency
response (fT)

• We will use gm/ID as the

reference axis to compare
other transistor parameters

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Intrinsic Transistor Gain (gm/go)

• These plots tell us how much intrinsic transistor gain we have

• The transistor has higher intrinsic gain at lower overdrive values due to the
output resistance decreasing faster than the transconductance increases at
higher current levels
• Plotted vs gm/ID shows that a after a certain minimum level, the transistor
gain is somewhat flat 8
Transit Frequency, fT

gm gm
fT  
2 CGS  CGD  2C gg
• The transit frequency is defined as the frequency when the transistor small-signal
current gain goes to unity with the source and drain at AC grounds
• Overall, the ratio of gm to Cgg comes up often in analog circuits, and is a good metric
to compare the device frequency response (speed)
• Transistor fT increases with overdrive voltage and high fT values demand a low gm/ID
• If you need high bandwidth, you have to operate the device at low efficiency
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Current Density, ID/W

• Ultimately, we need to know how to size our devices to get a certain current
• The current density of a transistor increases with increased VGS or overdrive
voltage
• High gm/ID requires low current density, which implies bigger devices for a
given current
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CS Amplifier Design Example

• Specifications
• 0.6m technology
• |Av|  4V/V
• fu  100MHz
• CL = 5pF
• Vdd = 3V

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CS Amplifier Small-Signal Model (No RS)

vo

sC gd  g m R|| rR
, where R||  o L
vi s C L  C gd  Cdb R||  1 ro  RL

gm
z  (located at very high frequency,  T )
C gd
1 1
p   
R|| C L  C gd  Cdb  RL C L
Av   g m R||   g m RL
gm
u  Av p 
CL

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Design Procedure
1. Determine gm from design specifications
a. u in this example
2. Pick transistor L
a. Short channel  high fT (high bandwidth)
b. Long channel  high ro (high gain)
3. Pick gm/ID (or fT)
a. Large gm/ID  low power, large signal swing (low Vov)
b. Small gm/ID  high fT (high speed)
c. May also be set by common-mode considerations
4. Determine ID/W from ID/W vs gm/ID chart
5. Determine W from ID/W

• Other approaches exist

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1. Determine gm (& RL)
• From u and DC gain specification
gm
u  Av p 
CL
g m  u C L  2 100 MHz 5 pF   3.14mA / V
Note, this may be slightly low due to neglecting Cgd and Cdb

Av   g m R||   g m RL
Av
RL 
gm
Adding 20% margin to compensate for ro effects
Av 4.8
RL    1.5k
g m 3.14mA / V

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2. Pick Transistor L
• Need to look at gain and fT plots

• Since amplifier Av4, min channel length (L=0.6m) will

work with gm/ID~>2
• Min channel length provides highest fT at this gm/ID setting
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3. Pick gm/ID (or fT)
• Setting ID for VO=1.5V for large output
swing range
3V  1.5V
ID   1mA
1.5k

g m 3.14mA / V
  3.14V 1
ID 1mA

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Verify Transistor Gain & fT at gm/ID Setting

fT = 6.7GHz
Gain = 30.6

• Transistor gain=30.6 >> amplifier Av4

• Transistor fT=6.7GHz >> amplifier fu=100MHz
• gm/ID setting is acceptable
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4. Determine Current Density (ID/W)

ID/W = 20.2

VGS=1.15V

• gm/ID=3.14V-1 maps to a • Verify current density is

current density of 20.2A/m achievable at a reasonable VGS
• VGS=1.15V is reasonable with
Vdd=3V & VDS=1.5V

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5. Determine Transistor W from ID/W
• From Step 3, we determined that ID=1mA
ID 1mA
W   49.5m
I D W  20.2A / m
• For layout considerations and to comply
with the technology design rules
• Adjust 49.5m to 49.2m and realize with 8
fingers of 6.15m
• This should match our predictions well, as the
charts are extracted with a 6m device
• Although it shouldn’t be too sensitive to exact
finger width
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Simulation Circuit

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Operating Point Information
Design Value
N0:betaeff 9.97E‐03 N0:csg ‐3.68E‐14 N0:qb ‐5.03E‐14
N0:cbb 2.48E‐14 N0:css 4.32E‐14 N0:qbd ‐9.46E‐14
N0:cbd ‐1.28E‐17 N0:cssbi 3.07E‐14 N0:qbi ‐5.03E‐14
N0:cbdbi 5.56E‐14 N0:gbd 0 N0:qbs 0
N0:cbg ‐8.56E‐15 N0:gbs 1.03E‐10 N0:qd ‐3.72E‐15
N0:cbs ‐1.63E‐14 N0:gds 1.02E‐04 N0:qdi ‐8.10E‐15
N0:cbsbi ‐1.63E‐14 N0:gm 3.13E‐03 3.14mA/V N0:qg 8.07E‐14
N0:cdb ‐4.26E‐15 N0:gmbs 7.64E‐04 N0:qgi 7.06E‐14
N0:cdd 1.25E‐14 N0:gmoverid 3.131 3.14V-1 N0:qinv 4.20E‐03
N0:cddbi ‐5.56E‐14 N0:i1 9.99E‐04
N0:qsi ‐1.21E‐14
N0:i3 ‐9.99E‐04
N0:cdg ‐2.87E‐14 N0:qsrco ‐2.66E‐14
N0:i4 ‐8.00E‐14
N0:cds 2.05E‐14 N0:region 2
N0:ibd ‐8.00E‐14
N0:cgb ‐1.42E‐14 N0:reversed 0
N0:ibs 0
N0:cgbovl 0 N0:ron 1.50E+03
N0:ibulk ‐8.00E‐14
N0:cgd ‐1.25E‐14
N0:cgdbi 5.07E‐17
N0:id 9.99E‐04
1mA N0:type 0
N0:ids 9.99E‐04 N0:vbs 0
N0:cgdovl 1.26E‐14 N0:igb 0 N0:vdb 1.502
N0:cgg 7.41E‐14 N0:igcd 0 N0:vds 1.502
N0:cggbi 4.90E‐14 N0:igcs 0 N0:vdsat 3.91E‐01
N0:cgs ‐4.74E‐14 N0:igd 0 N0:vfbeff ‐9.65E‐01
N0:cgsbi ‐3.49E‐14 N0:igidl 0
N0:vgb 1.153
N0:cgsovl 1.26E‐14 N0:igisl 0
N0:cjd 5.56E‐14 N0:vgd ‐3.49E‐01
N0:igs 0
N0:cjs 0 N0:vgs 1.153
N0:is ‐9.99E‐04
N0:csb ‐6.39E‐15 N0:isub 0 N0:vgsteff 5.00E‐01
N0:csd ‐2.60E‐17 N0:pwr 1.50E‐03 N0:vth 6.53E‐01

Total Cgate = Cgg = 74.1fF

Total Cdrain = Cdd + Cjd = 12.5fF + 55.6fF = 68.1fF
Total Csource = Css + Cjs = 43.2fF + 0fF = 43.2fF
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AC Response

Av= 12.2dB = 4.07V/V

fu = 95.5MHz

• Design is very close to specs

• Discrepancies come from neglecting ro and Cdrain
• With design table information we can include estimates of these in
our original procedure for more accurate results
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Next Time
• Single-Stage Amplifiers Frequency Response

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