Short Course On Phase-Locked Loops IEEE Circuit and System Society, San Diego, CA Analog Frequency Synthesizers

Michael H. Perrott September 16, 2009

Copyright 2009 by Michael H. Perrott All rights reserved.

What is a Phase-Locked Loop (PLL)?

ref(t) out(t) e(t) v(t) ref(t) e(t) ref(t) out(t) e(t) v(t) out(t)

Phase Detect

v(t) Analog Loop Filter VCO

de Bellescize Onde Electr, 1932

VCO efficiently provides oscillating waveform with variable frequency PLL synchronizes VCO frequency to input reference frequency through feedback

- Key block is phase detector

Realized as digital gates that create pulsed signals

M.H. Perrott

Integer-N Frequency Synthesizers

ref(t) div(t) e(t) v(t) Fout = N Fref ref(t) Phase Detect e(t) v(t) Analog Loop Filter VCO div(t) Divider N out(t)

Sepe and Johnston US Patent (1968)

Use digital counter structure to divide VCO frequency

- Constraint: must divide by integer values

Use PLL to synchronize reference and divider output

M.H. Perrott

Output frequency is digitally controlled

Integer-N Frequency Synthesizers in Wireless Systems

Zin

From Antenna and Bandpass Filter

PC board trace

Mixer Package Interface RF in LNA LO signal VCO IF out To Filter

Zo

Reference ref(t) Frequency v(t) Frequency Synthesizer

out(t)

ref(t)

e(t) Charge PFD Pump

Loop Filter

v(t)
VCO

out(t)

div(t)

Divider N

Design Issues: low noise, fast settling time, low power

M.H. Perrott
4

Fractional-N Frequency Synthesizers

ref(t) div(t) e(t) v(t) Fout = M.F Fref ref(t) Phase Detect e(t) v(t) Analog Loop Filter VCO div(t) Nsd[k] Modulator Divider N[k] M.F out(t)

Dither divide value to achieve fractional divide values

- PLL loop filter smooths the resulting variations

Very high frequency resolution is achieved

M.H. Perrott
5

Going Digital
ref(t) Phase Detect Analog Loop Filter VCO Divider out(t)

ref(t)

Time -toDigital

Digital Loop Filter DCO Divider

out(t)

Staszewski et. al., TCAS II, Nov 2003

- Time-to-Digital Converter (TDC) - Digitally-Controlled Oscillator (DCO) M.H. Perrott

Digital loop filter: compact area, insensitive to leakage Challenges:

Outline of PLL Short Course

Analog frequency synthesizers

- Integer-N synthesizers and PLL background - Fractional-N synthesizers - Modeling and noise analysis - Time-to-digital conversion

Digital frequency synthesizers

M.H. Perrott

Outline of Integer-N Frequency Synthesizer Talk

Fref ref(t) PFD e(t) v(t)
VCO

Fout = N Fref out(t)

Loop Filter Divider

div(t)

Overview of PLL Blocks System Level Modeling

- Transfer function analysis - Nonlinear behavior - Type I versus Type II systems

8

Noise Analysis
M.H. Perrott

Popular VCO Structures

LC oscillator VCO Amp
Vout C L Rp

-Ramp

Vin

Ring oscillator
Vout Vin

-1

LC Oscillator: low phase noise, large area Ring Oscillator: easy to integrate, higher phase noise
M.H. Perrott
9

Model for Voltage to Frequency Mapping of VCO

LC oscillator VCO Amp
Vout C L Rp

-Ramp

Vin

Fvco
Ring oscillator
Vout Vin

-1

VCO Frequency

fc

Fout slope=Kv

Vbias Input Voltage

vin

M.H. Perrott

10

Model for Voltage to Phase Mapping of VCO

Time-domain frequency relationship (from previous slide) Time-domain phase relationship

Intuition of integral relationship between frequency and phase:

1/Fvco= out(t) out(t) 1/Fvco= +
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Frequency-Domain Model for VCO

Time-domain relationship (from previous slide)

Corresponding frequency-domain model

Laplace-Domain v(t) out(t) v(t) 2Kv s VCO out(t)

Frequency-Domain v(t) Kv jf VCO out(t)

VCO

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Divider
Implementation
N out(t) out(t) div(t) N=6 Counter count value out div(t)

Time-domain model

- Frequency: - Phase:

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Frequency-Domain Model of Divider

Time-domain relationship between VCO phase and divider output phase (from previous slide)

Corresponding frequency-domain model (same as Laplace-domain)

out(t)

Divider

div(t)

out(t)

1 N Divider

div(t)

M.H. Perrott

14

Phase Detector (PD)

XOR structure

- Average value of error pulses corresponds to phase error - Loop filter extracts the average value and feeds to VCO
ref(t) e(t) div(t)

ref(t) div(t)
1

e(t)
-1

M.H. Perrott

15

XOR Phase Detector Characteristic

< ref div < 0
T/2 ref(t) div(t)
1

0 < ref div <

T/2 ref(t) div(t)
1

e(t)
-1 W

e(t)
-1 W

W=-

ref div T/2

W=

ref div T/2

avg{e(t)}
gain = -2/ 1 gain = 2/

/2
-1

/2

ref - div

phase detector range =

M.H. Perrott

16

Frequency-Domain Model of XOR Phase Detector

Assume phase difference confined within 0 to radians

- Phase detector characteristic looks like a constant gain

element
avg{e(t)}
gain = -2/ 1 gain = 2/

/2
-1

/2

ref - div

Corresponding frequency-domain model

ref(t) PD e(t) ref(t) 2 PD gain
17

e(t)

div(t)
M.H. Perrott

div(t)

Loop Filter
Consists of a lowpass filter to extract average of phase detector error pulses Frequency-domain model
Laplace-Domain e(t) Loop Filter v(t) e(t) H(s) H(s) VCO VCO v(t) Frequency-Domain e(t) H(f) v(t)

First order example

e(t) R1 C1
M.H. Perrott
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v(t)

Overall Linearized PLL Frequency-Domain Model

Combine models of individual components
Laplace-Domain Model
XOR PD

Loop Filter

VCO

ref(t)

e(t) H(s)
Divider

v(t)

2Kv s

out(t)

div(t)

1 N Frequency-Domain Model
XOR PD

Loop Filter

VCO

ref(t)

e(t) H(f)
Divider

v(t)

Kv jf

out(t)

div(t)

1 N
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M.H. Perrott

Open Loop versus Closed Loop Response

Frequency-domain model
XOR PD

Loop Filter

VCO

ref(t)

e(t) H(f)
Divider

v(t)

Kv jf

out(t)

div(t)

1 N

Define A(f) as open loop response

Define G(f) as a parameterizing closed loop function

- More details later in this lecture

M.H. Perrott

20

Classical PLL Transfer Function Design Approach

1. Choose an appropriate topology for H(f)
Usually chosen from a small set of possibilities

2. Choose pole/zero values for H(f) as appropriate for the required filtering of the phase detector output
Constraint: set pole/zero locations higher than desired PLL bandwidth to allow stable dynamics to be possible

3. Adjust the open-loop gain to achieve the required bandwidth while maintaining stability
Plot gain and phase bode plots of A(f) Use phase (or gain) margin criterion to infer stability
21

M.H. Perrott

Example: First Order Loop Filter

Overall PLL block diagram
XOR PD

Loop Filter

VCO

ref(t)

e(t) H(f)
Divider

v(t)

Kv jf

out(t)

div(t)

1 N

Loop filter
e(t) R1 C1 v(t)

M.H. Perrott

22

Closed Loop Poles Versus Open Loop Gain

Evaluation of Phase Margin
Open loop gain increased 20log|A(f)|

Closed Loop Pole Locations of G(f)

Im{s} C

Dominant pole pair

0 dB

fp C B A

f A Re{s} 0 A

angle(A(f))
-90
o

-120

PM = 59o for A PM = 45o for B PM = 33o for C

-150o

-180o

Higher open loop gain leads to an increase in Q of closed loop poles

M.H. Perrott

23

Corresponding Closed Loop Response

Frequency Response of G(f)
5 dB 0 dB -5 dB

Step Response of G(f)

1.4

C B A

C B A

0.6

fp

Increase in open loop gain leads to

- Peaking in closed loop frequency response - Ringing in closed loop step response
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M.H. Perrott

The Impact of Parasitic Poles

Loop filter and VCO may have additional parasitic poles and zeros due to their circuit implementation We can model such parasitics by including them in the loop filter transfer function Example: add two parasitic poles to first order filter
e(t) R1 Parasitics C1 v(t)

M.H. Perrott

25

Closed Loop Poles Versus Open Loop Gain

Evaluation of Phase Margin
Open loop gain increased 20log|A(f)|

Closed Loop Pole Locations of G(f)

Im{s} C Dominant pole pair

0 dB

fp fp2fp3 C B A

f Non-dominant poles B A
PM = 72 for A PM = 51o for B
o

angle(A(f))
-90
o

Re{s} 0

A B

-165 o -180 -240

PM = -12 for C

-315

M.H. Perrott

26

Corresponding Closed Loop Response

Closed Loop Frequency Response

C

Closed Loop Step Response

0 dB

B A

Frequency

Time

Increase in open loop gain now eventually leads to instability

- Large peaking in closed loop frequency response - Increasing amplitude in closed loop step response

M.H. Perrott

27

Response of PLL to Divide Value Changes

XOR PD

Loop Filter

VCO

ref(t)

e(t) H(f)
Divider

v(t)

Kv jf

out(t)

div(t)

1 N N+1 N

Change in output frequency achieved by changing the divide value Classical approach provides no direct model of impact of divide value variations

- Treat divide value variation as a perturbation to a linear

system PLL responds according to its closed loop response

M.H. Perrott

28

Response of an Actual PLL to Divide Value Change

Example: Change divide value by one
Synthesizer Response To Divider Step
N (Divide Value)
93 92.8 92.6 92.4 92.2 92 91.8 40 60 80 100 120 140 160 180 200 220 240

Output Frequency (GHz)

1.87

1.86

1.85

1.84

1.83

40

60

80

100

120

140

160

180

200

220

240

Time (microseconds)

- PLL responds according to closed loop response!

M.H. Perrott

29

What Happens with Large Divide Value Variations?

PLL temporarily loses frequency lock (cycle slipping occurs)
Synthesizer Response To Divider Step
96

N (Divide Value)

95 94 93 92 40 60 80 100 120 140 160 180 200 220 240

Output Frequency (GHz)

1.92 1.9 1.88 1.86 1.84 40 60 80 100 120 140 160 180 200 220 240

Time (microseconds)

- Why does this happen?

M.H. Perrott
30

Recall Phase Detector Characteristic

avg{e(t)}
gain = -2/ 1 gain = 2/

/2
-1

/2

ref - div

To simplify modeling, we assumed that we always operated in a confined phase range (0 to )

- Led to a simple PD model

happens to be in

Large perturbations knock us out of that confined phase range

- PD behavior varies depending on the phase range it

31

M.H. Perrott

Cycle Slipping
Consider the case where there is a frequency offset between divider output and reference

- We know that phase difference will accumulate

ref(t) div(t)

Resulting ramp in phase causes PD characteristic to be swept across its different regions (cycle slipping)
avg{e(t)}
gain = -2/ 1 gain = 2/

M.H. Perrott

/2
-1

/2

ref - div

32

Impact of Cycle Slipping

Loop filter averages out phase detector output Severe cycle slipping causes phase detector to alternate between regions very quickly

- Average value of XOR characteristic can be close to zero - PLL frequency oscillates according to cycle slipping - In severe cases, PLL will not re-lock
PLL has finite frequency lock-in range!
XOR DC characteristic
cycle slipping 1 -1 3 n (n+2)

ref - div

M.H. Perrott

33

Back to PLL Response Shown Previously

PLL output frequency indeed oscillates
Synthesizer Response To Divider Step
96

- Eventually locks when frequency difference is small enough

N (Divide Value)
95 94 93 92 40 60 80 100 120 140 160 180 200 220 240

Output Frequency (GHz)

1.92 1.9 1.88 1.86 1.84 40 60 80 100 120 140 160 180 200 220 240

Time (microseconds)

- How do we extend the frequency lock-in range?

M.H. Perrott
34

Phase Frequency Detectors (PFD)

Example: Tristate PFD
1 ref(t)
R

up(t)
D Q Q

e(t)
R

1 div(t)

Q Q

down(t)

Ref(t) Div(t) Up(t) Down(t) E(t)

1 0 -1
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M.H. Perrott

Tristate PFD Characteristic

Calculate using similar approach as used for XOR phase detector avg{e(t)}
1 gain = 1/(2) 2 2

ref - div

1 phase detector range = 4

Note that phase error characteristic is asymmetric about zero phase

- Key attribute for enabling frequency detection

M.H. Perrott

36

PFD Enables PLL to Always Regain Frequency Lock

Asymmetric phase error characteristic allows positive frequency differences to be distinguished from negative frequency differences

- Average value is now positive or negative according to sign of frequency offset - PLL will always relock
Tristate DC characteristic
cycle slipping 1

2n
lock

ref - div

-1

M.H. Perrott

37

Another PFD Structure

XOR-based PFD
D Q R Q

ref(t)

Q Q

ref/2(t)

e(t)

div(t)

Q Q

div/2(t)

D SQ Q

Divide-by-2

Phase Detector

Frequency Detector

ref(t) div(t) ref/2(t) div/2(t) e(t)

1 -1

M.H. Perrott

38

XOR-based PFD Characteristic

Calculate using similar approach as used for XOR phase detector
avg{e(t)}
1 gain = 1/

ref - div

1 phase detector range = 2

Phase error characteristic asymmetric about zero phase

cycle slipping depending on sign of frequency error
M.H. Perrott

- Average value of phase error is positive or negative during

39

Linearized PLL Model With PFD Structures

Assume that when PLL in lock, phase variations are within the linear range of PFD

- Simulate impact of cycle slipping if desired (do not

include its effect in model)

Same frequency-domain PLL model as before, but PFD gain depends on topology used
Tristate: =1 PFD XOR-based: =2

Loop Filter

VCO

ref(t)

e(t) H(f)
Divider

v(t)

Kv jf

out(t)

div(t)

1 N
40

M.H. Perrott

Type I versus Type II PLL Implementations

Type I: one integrator in PLL open loop transfer function

- VCO adds on integrator - Loop filter, H(f), has no integrators - Loop filter, H(f), has one integrator
Tristate: =1 PFD XOR-based: =2

Type II: two integrators in PLL open loop transfer function

Loop Filter

VCO

ref(t)

e(t) H(f)
Divider

v(t)

Kv jf

out(t)

div(t)

1 N
41

M.H. Perrott

VCO Input Range Issue for Type I PLL Implementations

DC output range of gain block versus integrator
Gain Block 0 0 Integrator K s

Issue: DC gain of loop filter often small and PFD output range is limited
VDD

- Loop filter output fails to cover full input range of VCO

No Integrator
Gnd

Output Range of Loop Filter

ref(t) PFD

e(t)

Loop Filter

v(t)

out(t)

VCO Divider N[k]

M.H. Perrott

42

Options for Achieving Full Range Span of VCO

Type I

- Add a D/A converter to provide coarse tuning

Adds power and complexity Steady-state phase error inconsistently set

Type II

- Integrator automatically provides DC level shifting

Low power and simple implementation Steady-state phase error always set to zero
Type I
Course Tune Output Range of Loop Filter

Type II
Output Range of Loop Filter
VDD

D/A
VDD

No Integrator
Gnd

Contains Integrator
Gnd

e(t) C.P.

Loop Filter

v(t)

e(t) C.P.

Loop Filter

v(t)
43

M.H. Perrott

A Common Loop Filter for Type II PLL Implementation

Use a charge pump to create the integrator

- Current onto a capacitor forms integrator - Add extra pole/zero using resistor and capacitor

Gain of loop filter can be adjusted according to the value of the charge pump current Example: lead/lag network
e(t) Charge Pump i(t) v(t) R1 C2

C1

M.H. Perrott

44

Charge Pump Implementations

Switch currents in and out:
Single-Ended Differential

Icp up(t) Iout(t) down(t) Icp

Icp

Icp Iout(t)

e(t)

e(t)

2Icp

M.H. Perrott

45

Modeling of Loop Filter/Charge Pump

Charge pump is gain element Loop filter forms transfer function
Charge Pump Loop Filter

e(t)

Icp

v(t) H(s)

Example: lead/lag network from previous slide

M.H. Perrott

46

PLL Design with Lead/Lag Filter

Overall PLL block diagram
Tristate: =1 PFD XOR-based: =2

Charge Pump Loop Filter

VCO

ref(t)

e(t)

Icp

v(t) H(f)

Kv jf

out(t)

div(t)

Divider

1 N

Loop filter

Set open loop gain to achieve adequate phase margin

- Set f lower than and f

z

higher than desired PLL bandwidth

47

M.H. Perrott

Closed Loop Poles Versus Open Loop Gain

Evaluation of Phase Margin
Open loop gain increased 20log|A(f)|

Closed Loop Pole Locations of G(f)

Im{s} C

B
0 dB

Dominant pole pair A

f fz fp C B A angle(A(f)) Non-dominant pole A

PM = 54o for B PM = 53o for A PM = 55o for C

Re{s} BC A 0

120

-140

-160

-180

Open loop gain cannot be too low or too high if reasonable phase margin is desired
M.H. Perrott
48

Impact of Parasitics When Lead/Lag Filter Used

We can again model impact of parasitics by including them in loop filter transfer function
e(t) i(t) Parasitics C1 R1 C2 v(t)

Charge Pump

Example: include two parasitic poles with the lead/lag transfer function

M.H. Perrott

49

Closed Loop Poles Versus Open Loop Gain

Evaluation of Phase Margin
Open loop gain increased 20log|A(f)|

Closed Loop Pole Locations of G(f)

Im{s} Dominant pole pair C

B
0 dB

f fz fp fp2 fp3 C B A Non-dominant poles A A

PM = 46o for A PM = 38o for B
o

A Re{s} BC 0

angle(A(f))
120
o

-140

-160

-180

PM = -7o for C

Closed loop response becomes unstable if open loop gain is too high
M.H. Perrott
50

Negative Issues For Type II PLL Implementations

|G(f)|
fcp fz 1 Peaking caused by undesired pole/zero pair Step Responses for a Second Order G(f) implemented as a Bessel Filter 1.4 Type II: fz/fo = 1/3
Type II: fz/fo = 1/8

Normalized Amplitude

1
Type I

0.6

fz fo Frequency (Hz)

1 2 3 Normalized time: t*fo

Parasitic pole/zero pair causes

- Peaking in the closed loop frequency response - Extended settling time due to parasitic tail response
Bad for wireless systems demanding fast settling time
51

M.H. Perrott

Summary of Integer-N Dynamic Modeling

Linearized models can be derived for each PLL block

- Resulting transfer function model of PLL is accurate for small perturbations in PLL - Linear PLL model breaks down for large perturbations
on PLL, such as a large step change in frequency Cycle slipping is key nonlinear effect

Key issues for designing PLL are

- Achieve stable operation with desired bandwidth - Allow full range of VCO with a simple implementation
Type II PLL is very popular to achieve this

M.H. Perrott

52

Frequency Synthesizer Noise in Wireless Systems

Zin

From Antenna and Bandpass Filter

PC board trace

Mixer Package Interface RF in LNA LO signal VCO IF out To Filter

Zo

Reference Frequency

Frequency Synthesizer

Phase Noise f

fo

Synthesizer noise has a negative impact on system

- Receiver lower sensitivity, poorer blocking performance - Transmitter increased spectral emissions (output spectrum
must meet a mask requirement)
53

Noise is characterized in frequency domain

M.H. Perrott

Phase Noise Versus Spurious Noise

Phase noise is non-periodic
Sout(f) dBc/Hz -fo fo 1

Sout(f) f

- Described as a spectral density relative to carrier power

Spurious noise is periodic
Sout(f) dBc -fo 1 f fspur 1 dspur 2 2 fspur fo

- Described as tone power relative to carrier power

M.H. Perrott
54

Sources of Noise in Frequency Synthesizers

Reference Jitter Reference Feedthrough Charge Pump Noise VCO Noise -20 dB/dec f T ref(t) 1/T f f f

e(t) Charge PFD Pump

Loop Filter

v(t)
VCO

div(t) Divider Jitter

Divider

N f

Extrinsic noise sources to VCO

- Reference/divider jitter and reference feedthrough - Charge pump noise

55

M.H. Perrott

Modeling the Impact of Noise on Output Phase of PLL

Divider/Reference Jitter S jit(f) Reference Feedthrough S Espur(f) Charge Pump Noise S cpn(f) VCO Noise S vn(f) -20 dB/dec
0

1/T

jit[k] ref [k]

PFD

espur(t) e(t) Icp

cpn(t)
v(t)

vn(t) H(f)
Loop Filter KV jf VCO

out(t)

div[k]

Charge Pump

1
N Divider

Determine impact on output phase by deriving transfer function from each noise source to PLL output phase
M.H. Perrott

- There are a lot of transfer functions to keep track of!

56

Simplified Noise Model

PFD-referred Noise S En(f) VCO-referred Noise S vn(f) -20 dB/dec
0

1/T

en(t) ref [k]

PFD

vn(t) e(t)
v(t)

Icp

H(f)
Loop Filter

KV jf VCO

out(t)

div[k]

Charge Pump

1
N Divider

Refer all PLL noise sources (other than the VCO) to the PFD output

- PFD-referred noise corresponds to the sum of these

noise sources referred to the PFD output

M.H. Perrott

57

Impact of PFD-referred Noise on Synthesizer Output

PFD-referred Noise S En(f) VCO-referred Noise S vn(f) -20 dB/dec
0

1/T

en(t) ref [k]

PFD

vn(t) e(t)
v(t)

Icp

H(f)
Loop Filter

KV jf VCO

out(t)

div[k]

Charge Pump

1
N Divider

Transfer function derived using Blacks formula

M.H. Perrott

58

Impact of VCO-referred Noise on Synthesizer Output

PFD-referred Noise S En(f) VCO-referred Noise S vn(f) -20 dB/dec
0

1/T

en(t) ref [k]

PFD

vn(t) e(t)
v(t)

Icp

H(f)
Loop Filter

KV jf VCO

out(t)

div[k]

Charge Pump

1
N Divider

Transfer function again derived from Blacks formula

M.H. Perrott

59

A Simpler Parameterization for PLL Transfer Functions

PFD-referred Noise S En(f) VCO-referred Noise S vn(f) -20 dB/dec
0

1/T

en(t) ref [k]

PFD

vn(t) e(t)
v(t)

Icp

H(f)
Loop Filter

KV jf VCO

out(t)

div[k]

Charge Pump

1
N Divider

Define G(f) as

Always has a gain of one at DC

- A(f) is the open loop transfer function of the PLL

M.H. Perrott
60

Parameterize Noise Transfer Functions in Terms of G(f)

PFD-referred noise

VCO-referred noise

M.H. Perrott

61

Parameterized PLL Noise Model

PFD-referred Noise S En(f) VCO-referred Noise S vn(f) -20 dB/dec
0

1/T

en(t)
N G(f)

vn(t)
1-G(f)

fo

fo

npfd(t) n(t)
Divider Control c(t) of Frequency Setting (assume noiseless for now)

nvco(t) out(t)

PFD-referred noise is lowpass filtered VCO-referred noise is highpass filtered Both filters have the same transition frequency values

- Defined as f

M.H. Perrott

62

Impact of PLL Parameters on Noise Scaling

Radians2/Hz
PFD-referred Noise S En(f) VCO-referred Noise S vn(f) -20 dB/dec
0

N S e n (f)

S vn(f) f
0

1/T

en(t)
N G(f)

vn(t)
1-G(f)

fo

fo

npfd(t) n(t)
Divider Control c(t) of Frequency Setting (assume noiseless for now)

nvco(t) out(t)

PFD-referred noise is scaled by square of divide value and inverse of PFD gain VCO-referred noise is not scaled (only filtered)
M.H. Perrott

- High divide values lead to large multiplication of this noise

63

Optimal Bandwidth Setting for Minimum Noise

Radians2/Hz
PFD-referred Noise S En(f) VCO-referred Noise S vn(f) -20 dB/dec
0

N S e n (f)

S vn(f) f
0

1/T

en(t)
N G(f)

vn(t) (fo)opt
1-G(f)

fo

fo

npfd(t) n(t)
Divider Control c(t) of Frequency Setting (assume noiseless for now)

nvco(t) out(t)

Optimal bandwidth is where scaled noise sources meet

- Higher bandwidth will pass more PFD-referred noise - Lower bandwidth will pass more VCO-referred noise

M.H. Perrott

64

Resulting Output Noise with Optimal Bandwidth

Radians2/Hz
PFD-referred Noise S En(f) VCO-referred Noise S vn(f) -20 dB/dec
0

N S e n (f)

S vn(f) f
0

1/T

en(t)
N G(f)

vn(t) (fo)opt
1-G(f)

fo

fo

npfd(t) n(t)
Divider Control c(t) of Frequency Setting (assume noiseless for now)

nvco(t) out(t)

Radians2/Hz

S npfd(f) S nvco(f)

f
0

(fo)opt

PFD-referred noise dominates at low frequencies

- Corresponds to close-in phase noise of synthesizer

65

- Corresponds to far-away phase noise of synthesizer M.H. Perrott

VCO-referred noise dominates at high frequencies

Summary of Noise Analysis of Integer-N Synthesizers

Key PLL noise sources are

- VCO noise - PFD-referred noise

Charge pump noise, reference noise, etc.

Setting of PLL bandwidth has strong impact on noise

- High PLL bandwidth suppresses VCO noise - Low PLL bandwidth suppresses PFD-referred noise

M.H. Perrott

66

Fractional-N Frequency Synthesis

Fref ref(t) e(t) Charge PFD Pump v(t)
VCO

Fout = M.F Fref out(t)

Loop Filter

div(t) Nsd[k]

Divider Dithering N[k] Modulator M+1 M

Kingsford-Smith US Patent 3,928,813 1974 (filing date)

M.F

Divide value is dithered between integer values Fractional divide values can be realized!

Very high frequency resolution

M.H. Perrott
67

Outline of Fractional-N Synthesizers

Traditional Approach Sigma-Delta Concepts Synthesizer Noise Analysis

M.H. Perrott

68

Classical Fractional-N Synthesizer Architecture

ref(t)
e(t)
Loop Filter N/N+1

PFD

out(t)

div(t)
frac[k]
Accumulator

1-bit

carry_out[k] Nsd[k] = N + frac[k]

Use an accumulator to perform dithering operation

- Fractional input value fed into accumulator - Carry out bit of accumulator fed into divider

M.H. Perrott

69

Accumulator Operation
clk(t) frac[k]
Accumulator M-bit 1-bit M-bit

residue[k] carry_out[k]

residue[k] frac[k] =.25 carry_out[k]

Carry out bit is asserted when accumulator residue reaches or surpasses its full scale value

- Accumulator residue increments by input fractional

value each clock cycle

M.H. Perrott

70

Fractional-N Synthesizer Signals with N = 4.25

carry_out(t) out(t) div(t) ref(t) e(t) phase error(t)

Divide value set at N = 4 most of the time

- Resulting frequency offset causes phase error to accumulate - Reset phase error by swallowing a VCO cycle
Achieved by dividing by 5 every 4 reference cycles
71

M.H. Perrott

The Issue of Spurious Tones

ref(t)
e(t)
Loop Filter N/N+1

PFD

out(t)

div(t)
frac[k]
Accumulator

1-bit

carry_out[k] Nsd[k] = N + frac[k]

PFD error is periodic

- Note that actual PFD waveform is series of pulses the

sawtooth waveform represents pulse width values over time

Periodic error signal creates spurious tones in synthesizer output

- Ruins noise performance of synthesizer

M.H. Perrott

72

The Phase Interpolation Technique

e(t)

ref(t)

PFD

Loop Filter N/N+1

out(t)

div(t)
D/A

frac[k]
M-bit

M-bit Accumulator residue[k] 1-bit

carry_out[k]

Phase error due to fractional technique is predicted by the instantaneous residue of the accumulator
M.H. Perrott

- Cancel out phase error based on accumulator residue

73

The Problem With Phase Interpolation

e(t)

ref(t)

PFD

Loop Filter N/N+1

out(t)

div(t)
D/A

frac[k]
M-bit

M-bit Accumulator residue[k] 1-bit

carry_out[k]

Gain matching between PFD error and scaled D/A output must be extremely precise
M.H. Perrott

- Any mismatch will lead to spurious tones at PLL output

74

Is There a Better Way?

A Better Dithering Method: Sigma-Delta Modulation

Time Domain

M-bit Input

Digital Modulator

1-bit D/A

Analog Output

Frequency Domain
Digital Input Spectrum Quantization Noise Analog Output Spectrum

Input

Sigma-Delta dithers in a manner such that resulting quantization noise is shaped to high frequencies
M.H. Perrott
76

Linearized Model of Sigma-Delta Modulator

r[k] NTF Hn(z)
1

S r(ej2fT)= 1

12

z=ej2fT

STF x[k] y[k] x[k] Hs(z)

z=ej2fT

q[k] y[k]

S q(ej2fT)= 1 |H n(ej2fT)| 2
12

Composed of two transfer functions relating input and noise to output

- Signal transfer function (STF) Filters input (generally undesirable) - Noise transfer function (NTF)

Filters (i.e., shapes) noise that is assumed to be white

M.H. Perrott
77

Example: Cutler Sigma-Delta Topology

x[k] u[k] y[k]

H(z) - 1

e[k]

Output is quantized in a multi-level fashion Error signal, e[k], represents the quantization error Filtered version of quantization error is fed back to input
1 -1 2 -2

- H(z) is typically a highpass filter whose first tap value is 1 i.e., H(z) = 1 + a z + a z L - H(z) 1 therefore has a first tap value of 0
Feedback needs to have delay to be realizable
78

M.H. Perrott

Linearized Model of Cutler Topology

r[k] x[k] u[k] y[k] x[k] u[k] y[k]

H(z) - 1

e[k]

H(z) - 1

e[k]

Represent quantizer block as a summing junction in which r[k] represents quantization error

- Note:

It is assumed that r[k] has statistics similar to white noise

M.H. Perrott

- This is a key assumption for modeling often not true!

79

Calculation of Signal and Noise Transfer Functions

r[k] x[k] u[k] y[k] x[k] u[k] y[k]

H(z) - 1

e[k]

H(z) - 1

e[k]

Calculate using Z-transform of signals in linearized model

- NTF: - STF:
M.H. Perrott

Hn(z) = H(z) Hs(z) = 1

80

A Common Choice for H(z)

m=3

Magnitude

m=2

m=1

0 0 Frequency (Hz) 1/(2T)

M.H. Perrott

81

Example: First Order Sigma-Delta Modulator

Choose NTF to be
x[k] u[k] y[k]

H(z) - 1

e[k]

Plot of output in time and frequency domains with input of

1
Magnitude (dB)

Amplitude

Sample Number

200

Frequency (Hz)

1/(2T)

M.H. Perrott

82

Example: Second Order Sigma-Delta Modulator

Choose NTF to be
x[k] u[k] y[k]

H(z) - 1

e[k]

Plot of output in time and frequency domains with input of

2

-1

Sample Number

200

Magnitude (dB)
0

Amplitude

Frequency (Hz)

1/(2T)

M.H. Perrott

83

Example: Third Order Sigma-Delta Modulator

Choose NTF to be
x[k] u[k] y[k]

H(z) - 1

e[k]

Plot of output in time and frequency domains with input of

4 3 2 1 0 -1 -2 -3 0 Sample Number 200 0 Frequency (Hz) 1/(2T)

Magnitude (dB)

Amplitude

M.H. Perrott

84

Observations
Low order Sigma-Delta modulators do not appear to produce shaped noise very well

- Reason: low order feedback does not properly

scramble relationship between input and quantization noise Quantization noise, r[k], fails to be white

Higher order Sigma-Delta modulators provide much better noise shaping with fewer spurs
more complex interaction between input and quantization noise

- Reason: higher order feedback filter provides a much

M.H. Perrott

85

Warning: Higher Order Modulators May Still Have Tones

Quantization noise, r[k], is best whitened when a sufficiently exciting input is applied to the modulator

- Varying input and high order helps to scramble

interaction between input and quantization noise

Worst input for tone generation are DC signals that are rational with a low valued denominator

- Examples (third order modulator with no dithering):

x[k] = 0.1 x[k] = 0.1 + 1/1024
Magnitude (dB) Magnitude (dB)
Frequency (Hz)

1/(2T)

Frequency (Hz)

1/(2T)

M.H. Perrott

86

Fractional Spurs Can Be Theoretically Eliminated

See:

- M. Kozak, I. Kale, Rigorous Analysis of Delta-Sigma

Modulators for Fractional-N PLL Frequency Synthesis, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 51, no. 6, pp. 1148-1162, June 2004.

- S. Pamarti, I. Galton, "LSB Dithering in MASH Delta

Sigma D/A Converters", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779 790, April 2007.

M.H. Perrott

87

MASH topology
x[k] M1[k] r1[k]
M

M2[k]

r2[k]
1

M3[k]

y1[k]

y2[k] 1-z-1 u[k]

y3[k]

(1-z-1)2
y[k]

Cascade first order sections Combine their outputs after they have passed through digital differentiators Advantage over single loop approach

- Allows pipelining to be applied to implementation

High speed or low power applications benefit
88

M.H. Perrott

Calculation of STF and NTF for MASH topology (Step 1)

x[k] M1[k] r1[k]
M

M2[k]

r2[k]
1

M3[k]

y1[k]

y2[k] 1-z-1 u[k]

y3[k]

(1-z-1)2
y[k]

Individual output signals of each first order modulator

Addition of filtered outputs

M.H. Perrott

89

Calculation of STF and NTF for MASH topology (Step 1)

x[k] M1[k] r1[k]
M

M2[k]

r2[k]
1

M3[k]

y1[k]

y2[k] 1-z-1 u[k]

y3[k]

(1-z-1)2
y[k]

Overall modulator behavior

- STF: H (z) = 1 - NTF: H (z) = (1 z )

s n

-1 3

M.H. Perrott

90

Sigma-Delta Frequency Synthesizers

Fref ref(t) e(t) Charge PFD Pump Loop Filter v(t)
VCO

Fout = M.F Fref out(t)

div(t) Nsd[m]

Divider N[m] Modulator M+1 M

Riley et. al., JSSC, May 1993

Quantization Noise

Use Sigma-Delta modulator rather than accumulator to perform dithering operation

- Achieves much better spurious performance than

classical fractional-N approach

M.H. Perrott

91

The Need for A Better PLL Model

PFD-referred Noise S En(f) f VCO-referred Noise S vn(f) -20 dB/dec
0

1/T

en(t) ref [k]

PFD

vn(t) out(t)

e(t)

v(t)

Icp

H(f)

KV jf VCO

div[k]

Charge Loop Pump Divider Filter

1
N N[k]

Classical PLL model

- Predicts impact of PFD and VCO referred noise sources - Does not allow straightforward modeling of impact due
to divide value variations This is a problem when using fractional-N approach
92

M.H. Perrott

Fractional-N PLL Model

PFD-referred Noise S En(f) f VCO-referred Noise S vn(f) -20 dB/dec
0

Tristate: =1 PFD XOR: =2

1/T

en(t) e(t)

ref [k]

C.P. Icp

Loop Filter H(f) v(t)

VCO
KV jf

vn(t) out(t)

div[k]
S q(e Quantization Noise
0
j2fT

Divider 1
Nnom )
1 T

d [k] n[k]
f

z 1 - z-1

-1

Perrott et. al. JSSC, Aug. 2002

z=e
j2fT

Closed loop dynamics parameterized by

M.H. Perrott

93

Parameterized PLL Noise Model

PFD-referred Noise S En(f) f VCO-referred Noise S vn(f) -20 dB/dec
0

Quantization Noise S q(ej2fT)

1/T

En(t)
2 NnomG(f)

vn(t)
1-G(f)

fo

fo

n[k]

n z-1 2 1 - z-1 z=ej2fT

[k]

T G(f)
fo

div(t)

tn,pll(t)

out(t)

Design revolves around choice of and G(f)

- We will focus on G(f) design here

M.H. Perrott

94

A Well Designed Sigma-Delta Synthesizer

fo = 84 kHz
-60 -70

Spectral Density (dBc/Hz)

-80 -90 -100 -110 -120 -130 -140 -150 -160 10 kHz

PFD-referred noise

out,En

(f)

noise

VCO-referred noise

out,

(f)

out,vn

(f)

100 kHz

1 MHz

10 MHz

f0

Frequency

1/T

Order of G(f) is set to equal to the Sigma-Delta order

- Sigma-Delta noise falls at -20 dB/dec above G(f) bandwidth

95

Bandwidth of G(f) is set low enough such that synthesizer noise is dominated by intrinsic PFD and VCO noise
M.H. Perrott

Impact of Increased PLL Bandwidth

fo = 84 kHz
-60 -60 -70

fo = 160 kHz
-70 -80 -90 -100 -110 -120 -130 -140 -150

Spectral Density (dBc/Hz)

-80 -90 -100 -110 -120 -130 -140 -150 -160 10 kHz

Spectral Density (dBc/Hz)

PFD-referred noise

PFD-referred noise

out,En

(f)

out,En

(f)
noise

noise

VCO-referred noise

S
VCO-referred noise

out,

(f)

out,

(f)

out,vn

(f)

out,vn

(f)

100 kHz

1 MHz

10 MHz

-160 10 kHz

100 kHz

1 MHz

10 MHz

f0

Frequency

1/T

f0

Frequency

1/T

Allows more PFD noise to pass through Allows more Sigma-Delta noise to pass through Increases suppression of VCO noise
M.H. Perrott
96

Impact of Increased Sigma-Delta Order

m=2
-60 -70 -60

m=3
-70

Spectral Density (dBc/Hz)

-80 -90 -100 -110 -120 -130 -140 -150 -160 10 kHz

Spectral Density (dBc/Hz)

PFD-referred noise

out,En

(f)

-80 -90 -100 -110 -120 -130 -140 -150

PFD-referred noise

out,En

(f)
VCO-referred noise

noise

VCO-referred noise

out,

(f)

out,vn

(f)

noise

S (f)

out,vn

(f)

out,

100 kHz

1 MHz

10 MHz

-160 10 kHz

100 kHz

1 MHz

10 MHz

f0

Frequency

1/T

f0

Frequency

1/T

PFD and VCO noise unaffected Sigma-Delta noise no longer attenuated by G(f) such that a -20 dB/dec slope is achieved above its bandwidth
M.H. Perrott
97

Impact of Quantization Noise on Synth. Output

Ref PFD Div N/N+1 Loop Filter

Out

Frequency Selection

M-bit

Modulator

1-bit

Quantization Noise Spectrum

Output Spectrum

Noise

Frequency Selection
PLL dynamics

Fout

Lowpass action of PLL dynamics suppresses the shaped - quantization noise

M.H. Perrott
98

Impact of Increasing the PLL Bandwidth

Ref PFD Div N/N+1 Loop Filter

Out

Frequency Selection

M-bit

Modulator

1-bit

Quantization Noise Spectrum

Output Spectrum

Noise

Frequency Selection
PLL dynamics

Fout

Higher PLL bandwidth leads to less quantization noise suppression

Tradeoff: Noise performance vs PLL bandwidth

M.H. Perrott
99

A Cancellation Method for Reducing Quantization Noise

ref(t) PFD

Charge Pump

e(t)

r(t) Loop v(t) Filter

VCO

out(t)

div(t) q[k] Nsd[k] Modulator N[k] DAC

Divider Quantization Noise Suppression

Pamarti et. al., TCAS II, Nov 2003

Key idea: quantization noise can be predicted within the digital modulator structure Issue: cancellation is limited by analog matching
M.H. Perrott

- Achieves < 20 dB cancellation in practice

100

Improved Cancellation Through Inherent Matching

ref(t) PFD/DAC

r(t)

Loop Filter Divider

v(t)
VCO

out(t)

div(t) q[k] Nsd[k] Modulator N[k]

Quantization Noise Suppression

Meninger et. al., TCAS II, Nov 2003

Combined PFD/DAC structure achieves inherent matching between error and cancellation signal

- > 29 dB quantization noise cancellation achieved

M.H. Perrott

101

Improved Cancellation Through Continuous Calibration

ref(t) PFD

Charge Pump

e(t)

r(t) Loop v(t) Filter

VCO

out(t)

div(t) q[k] Nsd[k] Modulator DAC gain

Divider Quantization Noise Suppression N[k] f

Gupta et. al., ISSCC, Feb 2006

LMS Algorithm

- > 30 dB noise cancellation achieved M.H. Perrott

Gain of DAC is adjusted in an adaptive manner using LMS algorithm

102

Summary of Fractional-N Frequency Synthesizers

Fractional-N synthesizers allow very high resolution to be achieved with relatively high reference frequencies
of divider

- Cost is introduction of quantization noise due to dithering - Quantization noise cancellation was attempted

Classical fractional-N synthesizers used an accumulator for dithering Sigma-Delta fractional-N synthesizers improve quantization noise by utilizing noise shaping techniques

- Key tradeoff: PLL bandwidth versus phase noise - Quantization noise cancellation has made a comeback

M.H. Perrott

103