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Reg. No. :
Question Paper Code : 40490
B.E./B.Tech. DEGREE EXAMINATIONS, NOVEMBER/DECEMBER 2021.
Fourth Semester
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Electrical and Electronics Engineering
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EE 8451 — LINEAR INTEGRATED CIRCUITS AND APPLICATIONS
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(Common to : B.E. Electronics and Instrumentation Engineering and
Instrumentation and Control Engineering)
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(Regulations 2017)
Time : Three hours
or Maximum : 100 marks
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Answer ALL questions.
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PART A — (10 × 2 = 20 marks)
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1. What is meant by dielectric isolation?
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2. How does FET fabrication differ from BJT?
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3. Find the maximum frequency for a sine wave output voltage of 5 V peak with
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an OP-AMP whose slew rate is 2V/μs.
4. Design an adder circuit using Op-amp to get the output expression as
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V0 = − (0.1 V1 + V2 + 10 V3 ) where V1 ,V2 ,V3 are inputs
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5. A basic step of a 9-bit DAC is 10.3 mV. If 000000000 represents 0V, what
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output is produced if the input is 101101011?
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6. What is the use of Sample and Hold circuit in A/D Converter?
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7. Find the change in output frequency for input change of 1.2V to 1.5V with
voltage to frequency conversion factor is 30 × 103 Hz/V.
8. Why pin4 is connected to Vcc in a 555 timer?
9. The unregulated input voltage of the three terminal regulator is 8V. Find the
output voltage.
10. Compare the linear and switching regulator.
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PART B — (5 × 13 = 65 marks)
11. (a) Describe the Epitaxial Growth, Oxidation, Photolithography and
Diffusion processes in Silicon Planar technology with relevant diagrams.
(13)
Or
(b) Explain in detail the different fabricating methods involved in Integrated
Resistors and diodes with neat diagrams. (13)
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12. (a) Discuss any two DC and AC characteristics of OPAMP with their
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importance. (13)
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Or
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(b) (i) Explain the operation of practical differentiator with neat
diagrams. or (8)
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(ii) Design an op-amp differentiator that will differentiate an input
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signal with fmax = 500 Hz. Assume, C = 0.01 μF. (5)
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13. (a) (i) Derive the output expression of an Instrumentation amplifier with
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neat diagram. (8)
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(ii) Design a second order Butterworth Low pass filter for a higher
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cut-off frequency of 5 kHz. Assume, C = 0.1μF and feedback resistor
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is 10 kΩ. (5)
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Or
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(b) (i) Derive and design a RC-Phase shift oscillator with the frequency of
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oscillations equal to 2 KHz. Assume, C = 0.01 μF and Rf = 5 kΩ. (8)
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(ii) Obtain the output of R-2R ladder DAC with binary data d1d2d3 is
101. Assume, VR = –5V and d1 is the MSB bit. (5)
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14. (a) (i) Draw the block Diagram of IC 566 Voltage Controlled Oscillator
and explain its operation and derive its free running frequency. (10)
(ii) Explain the application of PLL as AM detection. (3)
Or
(b) Explain the internal circuit of 555 timer and explain the design of
monostable multivibrator using 555 timer. (13)
2 40490
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15. (a) (i) Describe the operations of AD623 Instrumentation amplifier and
mention its applications. (7)
(ii) With neat diagram, explain the operation of High voltage regulator
using IC 723. (6)
Or
(b) Explain the operation of Switched mode power supply with relevant
diagrams. (13)
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PART C — (1 × 15 = 15 marks)
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16. (a) (i) Design an Astable Multivibrator using Op-Amp with the frequency
of 3 KHz. Assume C = 0.1 μF, R1 = 2 KΩ, β = 0.3. (8)
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(ii) Design and explain the triangular waveform generator using
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Op-Amp. (7)
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Or
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(b) (i) Calculate the free running frequency, Lock-range and capture
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range of a 565 PLL if RT = 6.2 kΩ, CT = 0.001 μF and filter capacitor
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is 1 μF. The supply voltage is ±6V. (8)
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(ii) Explain the construction of 4 bit D/A converter using Op-Amp. (7)
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s:
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3 40490
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