Computer Architecture
Lecture 6.
. Input/Output.
Instructors
Elena Boldyreva, Associate Professor [email protected]
GOALS OF THIS LECTURE: PLAN:
1. get terminology about 1. Input/Output Problems
input/output computer 2. How external memory works
features 3. Why external memory works
2. more details about 4. external design basics
input/output function,
modules and implementation
©. Stallings, William. Computer organization and architecture : designing for performance 2
Input/Output Problems
• Computers have a wide variety of peripherals.
– Delivering different amounts of data, at
different speeds, in different formats.
• Many are not connected directly to system or
expansion bus.
• Most peripherals are slower than CPU and RAM;
a few are faster.
• Word length for peripherals may vary from the
CPU.
• Data format may vary (e.g., one word might
include parity bits).
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Input/Output Module
• Peripheral communications are handled
with I/O modules.
• Two major functions:
– Interface to processor or memory via
bus or central link.
– Interface to one or more peripherals
via tailored data links.
Generic Model of I/O Module
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External Devices
• Human readable (human interface).
– Screen, printer, keyboard, mouse.
• Machine readable.
– Disks, tapes.
• Functional view of disks as part of
memory hierarchy.
• Structurally part of I/O system.
– Sensors, actuators.
– Monitoring and control.
• Communications.
– Modem.
– Network Interface Card (NIC).
– Wireless Interface card.
External Device Block Diagram
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I/O Module Function
• Major requirements or functions of an I/O
module are:
– Control & Timing.
– CPU Communication.
– Device Communication.
– Data Buffering.
– Error Detection.
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Device Communication
• On the other side the I/O module has to
communicate with the device.
– Commands
– Status information
– Data
• Buffering is often essential.
• Handles the speed mismatch between memory and
the device.
– Low speed devices need to have data from
memory buffered.
– High speed devices need to have data going
to memory buffered.
– With any interrupt-driven device, data may
be buffered pending interrupt handler
servicing.
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Error Detection and Reporting
• Mechanical and Electrical malfunction (damages).
– E.g. Out of paper, paper jam, bad disk sector.
• Data communication errors.
– Typically detected with parity bits.
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Typical I/O Control Steps
Communication goes across the bus:
• CPU checks I/O module device status.
• I/O module returns status.
• If ready, CPU requests data transfer.
• I/O module gets data from device.
• I/O module transfers data to CPU.
• Variations for output, DMA, etc.
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I/O Module Decisions
• Hide or reveal device properties to CPU.
– Ex. Disks: LBA (logical block addressing) physical address CHS addressing
(cylinder/head/sector) is hidden from CPU.
– But older disks expose CHS addressing.
• Support multiple or single device.
– Most disk controllers handle 2 devices.
• Control device functions or leave for CPU.
– Ex: Video adapters with Direct Draw interface.
– But tape drives expose direct control to CPU.
• Also OS decisions.
– e.g. Unix treats everything it can as a file.
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Terminology
• Device or I/O Controller.
– Relatively simple, detailed control left to CPU.
• I/O Processor or I/O Channel.
– Presents high-level interface to CPU.
– Often controls multiple devices.
– Has processing capability.
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Input Output Techniques
• Programmed I/O.
o CPU controls the entire
process.
o Can waste CPU time.
• Interrupt driven.
o Processor issues command.
o Device proceeds and leaves
processor free.
• Direct Memory Access (DMA).
o Device exchanges data
directly with memory.
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Programmed I/O
• CPU has direct control over I/O: • CPU requests I/O operation.
– Sensing status. • I/O module performs operation.
– Read/write commands. • I/O module sets status bits.
• CPU checks status bits periodically.
– Transferring data. • I/O module does not inform CPU
• CPU waits for I/O module to complete directly.
operation. • I/O module does not interrupt CPU.
• Wastes CPU time. • CPU may wait or come back later.
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Types of I/O Commands
• CPU issues address:
– Identifies module (& device if >1 per module).
• CPU issues command:
– Control - telling module what to do.
• e.g. spin up disk.
– Test - check status.
• e.g. power? Error?
– Read/Write.
• Module transfers data via buffer from/to device.
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Addressing I/O Devices
• Under programmed I/O data transfer is very like memory access
(CPU viewpoint).
• Each device given unique identifier.
• CPU commands contain identifier (address).
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I/O Mapping
• Memory mapped I/O:
– Devices and memory share an address space.
– I/O looks just like memory read/write.
– No special commands for I/O.
• Large selection of memory access commands available.
– Ex: Motorola 68000 family
• Isolated I/O:
– Separate address spaces.
– Need I/O or memory select lines.
– Special commands for I/O.
• Limited set.
• Ex: Intel 80x86 family has IN and OUT commands.
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I/O Mapping
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Interrupt Driven I/O
Basic Operation
• Overcomes CPU waiting and preventing
that to happen.
• No repeated CPU checking of device.
• I/O module interrupts when ready.
• CPU issues read command.
• I/O module gets data from peripheral
while CPU does other work.
• I/O module interrupts CPU.
• CPU requests data.
• I/O module transfers data.
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CPU Viewpoint
• Issue read command.
• Do other work.
• Check for interrupt at end of each instruction cycle.
• If interrupted:
– Save content (registers).
– Process interrupt.
• Fetch data & store.
• See Operating Systems notes.
• How do you identify the module issuing the interrupt?
• How do you deal with multiple interrupts?
– i.e. an interrupt handler being interrupted.
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Identifying Interrupting Module
• Different line for each module. • Daisy Chain or Hardware poll:
– Don’t want to devote a lot of bus or – Interrupt Acknowledge sent down a chain.
CPU pins to interrupt lines. – Module responsible places vector on bus.
– Limits number of devices. – CPU uses vector to identify handler routine.
– But lines can be shared between • Bus Master:
devices, and these will use one of the – Module must claim the bus before it can
following techniques. raise interrupt.
• Software poll. – e.g. PCI & SCSI.
– CPU asks each module in turn, or – Processor responds with Interrupt
checks status register in each Acknowledge.
module. – Module can then place vector on bus.
– Slow.
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Multiple Interrupts
• Each interrupt line has a priority.
• Higher priority lines can interrupt lower priority lines.
• If bus mastering only current master can interrupt.
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Direct Memory Access
• Interrupt driven and programmed I/O require active CPU
intervention.
– Transfer rate is limited.
– CPU is tied up.
• DMA is the answer.
• Additional Module (hardware) on bus.
• DMA controller takes over from CPU for I/O.
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DMA Operation
• CPU tells DMA controller:
– Read/Write.
– Device address.
– Starting address of memory
block for data.
– Amount of data to be transferred.
• CPU carries on with other work.
• DMA controller deals with transfer.
• DMA controller sends interrupt when
finished.
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DMA Transfer Cycle Stealing
• DMA controller takes over bus for a cycle.
• Transfer of one word of data.
• Not an interrupt.
– CPU does not switch context.
• CPU suspended just before it accesses bus.
– i.e. before an operand or data fetch or a data write.
• Slows down CPU but not as much as CPU doing transfer.
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DMA Configurations
• Single Bus, Detached DMA controller.
• Each transfer uses bus twice.
– I/O to DMA then DMA to memory.
• CPU is suspended twice.
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Fly-By
• While DMA using buses processor idle.
• Processor using bus, DMA idle.
– Known as fly-by DMA controller.
• Data does not pass through and is not
stored in DMA chip.
– DMA only between I/O port and
memory.
– Not between two I/O ports or two
memory locations.
• Can do memory to memory via register.
• 8237 contains four DMA channels.
– Programmed independently.
– Any one active.
– Numbered 0, 1, 2, and 3.
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I/O Channels
• I/O devices getting more sophisticated.
• e.g. 3D graphics cards.
• CPU instructs I/O controller to do transfer.
• I/O controller does entire transfer.
• Improves speed.
– Takes load off CPU.
– Dedicated processor is faster. Interfacing
• Connecting devices together.
• Bit of wire?
• Dedicated processor/memory/buses?
• E.g. FireWire, InfiniBand.
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Evolution of the I/O Function
1.The CPU directly controls a peripheral 4.The I/O module is given direct access to memory
device. via DMA. It can now move a block of data to or
2.A controller or I/O module is added. from memory without involving the CPU, except
The CPU uses programmed I/O at the beginning and end of the transfer.
without interrupts. 5.The I/O module is enhanced to become a
3.Same configuration as in step 2 is processor in its own right, with a specialized
used, but now interrupts are
instruction set tailored for I/O
employed. The CPU need not spend
time waiting for an I/O operation to 6.The I/O module has a local memory of its own
be performed, thus increasing and is, in fact, a computer in its own right. With
efficiency. this architecture a large set of I/O devices can be
controlled with minimal CPU involvement.
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Conclusion
• External devices – Direct memory access
– Drawbacks of programmed and
– Keyboard/monitor interrupt-driven I/O
– Disk drive – DMA function
• I/O modules – Intel 8237A DMA controller
– Module function – I/O channels and processors
– I/O module structure – The evolution of the I/O function
• Programmed I/O – Characteristics of I/O channels
– Overview of programmed I/O – The external interface
– I/O commands – Types of interfaces
– I/O instructions – Point-to-point and multipoint
configurations
• Interrupt-driven I/O – Thunderbolt
– Interrupt processing – InfiniBand
– Design issues
– Intel 82C59A interrupt controller
– Intel 82C55A programmable peripheral
interface
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