+
William Stallings
Computer Organization
and Architecture
9th Edition
+
Chapter 7
Input/Output
+
Generic
Model
of an I/O
Module
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External Devices
Provide a means of
Three categories:
exchanging data between Human readable
the external environment Suitable for communicating with
and the computer the computer user
Video display terminals (VDTs),
Attach to the computer by a printers
link to an I/O module
Machine readable
The link is used to exchange
Suitable for communicating with
control, status, and data
equipment
between the I/O module and
Magnetic disk and tape systems,
the external device
sensors and actuators
peripheral device Communication
An external device Suitable for communicating with
connected to an I/O module remote devices such as a
terminal, a machine readable
device, or another computer
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External
Device
Block
Diagram
+ Most common means of
computer/user interaction
Keyboard/Monitor User provides input through
the keyboard
The monitor displays data
International Reference provided by the computer
Alphabet (IRA)
Basic unit of exchange is the Keyboard Codes
character
Associated with each character is a code When the user depresses a key it
generates an electronic signal that is
Each character in this code is
represented by a unique 7-bit binary interpreted by the transducer in the
code keyboard and translated into the bit
pattern of the corresponding IRA code
128 different characters can be
represented This bit pattern is transmitted to the
I/O module in the computer
Characters are of two types:
Printable On output, IRA code characters are
Alphabetic, numeric, and special transmitted to an external device
characters that can be printed on paper from the I/O module
or displayed on a screen
Control
The transducer interprets the code
Have to do with controlling the printing
and sends the required electronic
signals to the output device either to
or displaying of characters
display the indicated character or
Example is carriage return
perform the requested control
Other control characters are concerned function
with communications procedures
I/O Modules
Module Function
I/O Module Structure
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Programmed I/O
Three techniques are possible for I/O operations:
Programmed I/O
Data are exchanged between the processor and the I/O module
Processor executes a program that gives it direct control of the
I/O operation
When the processor issues a command it must wait until the I/O
operation is complete
If the processor is faster than the I/O module this is wasteful of
processor time
Interrupt-driven I/O
Processor issues an I/O command, continues to execute other
instructions, and is interrupted by the I/O module when the latter
has completed its work
Direct memory access (DMA)
The I/O module and main memory exchange data directly without
processor involvement
Table 7.1
I/O Techniques
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+
I/O Commands
There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:
1) Control
- used to activate a peripheral and tell it what to do
2) Test
- used to test various status conditions associated with an I/O
module and its peripherals
3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer
4) Write
- causes the I/O module to take an item of data from the data
bus and subsequently transmit that data item to the peripheral
Three
Techniques
for Input of
a
Block of
Data
I/O Instructions
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I/O Mapping Summary
Memory mapped I/O
Devices and memory share an address space
I/O looks just like memory read/write
No special commands for I/O
Large selection of memory access commands available
Isolated I/O
Separate address spaces
Need I/O or memory select lines
Special commands for I/O
Limited set
Memory
Mapped
I/O
Isolated
I/O
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Interrupt-Driven I/O
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Simple Interrupt
Processing
+
Changes
in Memory
and Registers
for an
Interrupt
Design Issues
+
Device Identification
Four general categories of techniques are in
common use:
Multiple interrupt lines
Between the processor and the I/O modules
Most straightforward approach to the problem
Consequently even if multiple lines are used, it is likely that each line will have multiple
I/O modules attached to it
Software poll
When processor detects an interrupt it branches to an interrupt-service routine whose job
is to poll each I/O module to determine which module caused the interrupt
Time consuming
Daisy chain (hardware poll, vectored)
The interrupt acknowledge line is daisy chained through the modules
Vector – address of the I/O module or some other unique identifier
Vectored interrupt – processor uses the vector as a pointer to the appropriate device-
service routine, avoiding the need to execute a general interrupt-service routine first
Bus arbitration (vectored)
An I/O module must first gain control of the bus before it can raise the interrupt request
line
When the processor detects the interrupt it responds on the interrupt acknowledge line
Then the requesting module places its vector on the data lines
+
Intel
82C59A
Interrupt
Controller
+ Intel 82C55A
Programmable Peripheral Interface
+
Keyboard/Displa
y Interfaces to
82C55A
Drawbacks of Programmed and
Interrupt-Driven I/O
Both forms of I/O suffer from two inherent
drawbacks:
1) The I/O transfer rate is limited by the
speed with which the processor can test
and service a device
2) The processor is tied up in managing an
I/O transfer; a number of instructions
must be executed for each I/O transfer
+
When large volumes of data are to be moved a
more efficient technique is direct memory access
(DMA)
+
Typical DMA
Module Diagram
DMA
DMA
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DMA Operation
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Alternative
DMA
Configurations
8237 DMA Usage of System Bus
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Fly-By DMA Controller
Table 7.2
Intel
8237A
Registers
E/D =
enable/disable
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Evolution of the I/O Function
1. The CPU directly controls
4. The I/O module is given direct
a peripheral device. access to memory via DMA. It can
now move a block of data to or from
2. A controller or I/O module memory without involving the CPU,
is added. The CPU uses except at the beginning and end of
programmed I/O without the transfer.
interrupts.
5. The I/O module is enhanced to
become a processor in its own right,
3. Same configuration as in
with a specialized instruction set
step 2 is used, but now
tailored for I/O
interrupts are employed.
The CPU need not spend 6. The I/O module has a local memory
time waiting for an I/O of its own and is, in fact, a computer
operation to be in its own right. With this
performed, thus architecture a large set of I/O
increasing efficiency. devices can be controlled with
minimal CPU involvement.
+
I/O
Channel
Architecture
+
Parallel
and
Serial
I/O
Point-to-Point and Multipoint
Configurations
+
Thunderbolt
Provides up to 10 Gbps throughput
Most recent and fastest in each direction and up to 10 Watts
of power to connected peripherals
peripheral connection
technology to become A Thunderbolt-compatible
available for general-purpose peripheral interface is considerably
use more complex than a simple USB
device
Developed by Intel with
collaboration from Apple
First generation products are
primarily aimed at the
The technology combines professional-consumer market
data, video, audio, and power such as audiovisual editors who
into a single high-speed want to be able to move large
connection for peripherals volumes of data quickly between
such as hard drives, RAID storage devices and laptops
arrays, video-capture boxes, Thunderbolt is a standard feature
and network interfaces of Apple’s MacBook Pro laptop and
iMac desktop computers
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Computer Configuration with Thunderbolt
+
Thunderbolt
Protocol
Layers
+
InfiniBand
Recent I/O specification aimed at the high-end server market
First version was released in early 2001
Standard describes an architecture and specifications for
data flow among processors and intelligent I/O devices
Has become a popular interface for storage area networking
and other large storage configurations
Enables servers, remote storage, and other network devices
to be attached in a central fabric of switches and links
The switch-based architecture can connect up to 64,000
servers, storage systems, and networking devices
InfiniBand Switch Fabric
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InfiniBand Operation
Each physical link between a The InfiniBand switch maps
switch and an attached traffic from an incoming
interface can support up to lane to an outgoing lane to
16 logical channels, called route the data between the
virtual lanes desired end points
One lane is reserved for
fabric management and A layered protocol
the other lanes for data architecture is used,
transport
consisting of four layers:
A virtual lane is temporarily Physical
dedicated to the transfer of Link
data from one end node to Network
another over the InfiniBand
fabric Transport
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Table 7.3
InfiniBand Links and Data
Throughput Rates
InfiniBand Communication Protocol
Stack
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zEnterprise 196
Introduced in 2010
IBM’s latest mainframe computer offering
System is based on the use of the z196 chip
5.2 GHz multi-core chip with four cores
Can have a maximum of 24 processor chips (96 cores)
Has a dedicated I/O subsystem that manages all I/O operations
Of the 96 core processors, up to 4 of these can be dedicated for I/O
use, creating 4 channel subsystems (CSS)
Each CSS is made up of the following elements:
System assist processor (SAP)
Hardware system area (HSA)
Logical partitions
Subchannels
Channel path
Channel
I/O System Organization
IBM z196 I/O System Structure
+ Summary
Input/Output
Chapter 7
Direct memory access
External devices
Drawbacks of programmed and
interrupt-driven I/O
Keyboard/monitor DMA function
Disk drive Intel 8237A DMA controller
I/O modules
Module function I/O channels and processors
I/O module structure The evolution of the I/O function
Programmed I/O Characteristics of I/O channels
Overview of programmed I/O
The external interface
I/O commands
Types of interfaces
I/O instructions
Point-to-point and multipoint
Interrupt-driven I/O configurations
Interrupt processing Thunderbolt
Design issues InfiniBand
Intel 82C59A interrupt controller
Intel 82C55A programmable
IBM zEnterprise 196 I/O
peripheral interface structure
