DATASHEET

Quantus Extraction Solution

Next-generation tool with the fastest performance and scalability, best- in-class accuracy
using smart solvers, and in-design and signoff parasitic extraction that customers trust

The Cadence ® Quantus™ Extraction Solution is a next-generation parasitic extraction tool for
digital and custom/analog flows. Providing the fastest single-corner and multi-corner runtimes
compared to competitive products, the tool features massively parallel architecture for performance
and scalability across hundreds of CPUs. Its high-accuracy modeling engine delivers impeccable
accuracy that has been silicon proven over thousands of tapeouts to support FinFET and all other
designs. It uses one unified, foundry-qualified “qrctechfile” for both digital and transistor extraction.
The solution, employing a robust 3D modeling framework, is certified by TSMC for all nodes
down to 3nm. In addition, the Quantus Extraction Solution is certified for all nodes at all other
leading foundries.

Overview signoff flow turnaround time. It is also tightly integrated with

the Voltus™-Fi Custom Power Integrity Solution for electromi-
As advanced-process geometries continue to shrink, gration (EM) and IR drop analysis, ensuring accuracy for
parasitic extraction has become critical throughout the FinFET designs.
design implementation flow and the signoff phase. The
Quantus solution is a production-proven signoff extraction
tool ideal for all nodes including advanced nodes and FinFET
Key Benefits
designs. The solution includes a built-in 3D capacitance f Best-in-class accuracy for FinFET designs versus
foundry golden
random-walk field solver, Quantus FS. Its objective includes
modeling physical effects to ensure that extracted parasitics f 5G-ready to support all design types
match those on silicon. By delivering higher accuracy f Tighter accuracy against field solver, with a near-zero mean
parasitics, the tool helps you to reduce overall design
f Highly accurate critical net extraction with integrated field
cycle times and significantly enhances the quality of
solver, Quantus FS
silicon in complex designs. Integrated with the Cadence
Innovus™ Implementation System and Cadence Virtuoso® f High performance and scalability with massively parallel
custom IC design platform, the Quantus solution is the architecture, supporting a linear gain when the number
of CPUs used is doubled
most complete and efficient path to accurate parasitic
extraction for all mainstream and advanced-node designs, f Scalability for single- and multi-corner extraction runs,
with up to 3X faster performance in multi-corner runs
including FinFET. Furthermore, it is tightly integrated with the
Cadence Tempus™ Timing Signoff Solution to provide the f Accurate and fastest runtimes for functional ECOs via
fastest convergence and up to 3X reduction in overall timing automated incremental extraction
 Quantus Extraction Solution

f Unmatched accuracy and a significantly reduced netlist that Massively parallel technology
enables faster simulation and characterization runtimes
The Quantus solution is built with massively parallel technology
for FinFET designs
to extract multi-million gate chips efficiently. The extraction
f Faster and better design convergence with integration with tasks are distributed across multiple CPUs and/or machines
the Innovus environment and Virtuoso ADE Product Suite for execution in parallel. Thus, the tool, which scales easily
f Supports OpenAccess and hierarchical extraction for to hundreds of CPUs, can deliver a linear performance gain
both flows when the number of CPUs used is doubled.

Features RF Analog
Mixed
Signal
Custom
Digital
Cell

f Quantus Smart View—the next-generation Extracted

View in the Virtuoso environment, delivering up to 10X Model-Based CMP and Litho

Reduction
Multi-Corner / Statistical
best-in-class performance

Distributed Processing

Manufacturing Effects
Hierarchical Extraction
ɢ Up to 7X faster than Extracted View
Field Solver
ɢ Up to 7X smaller netlist size than Extracted View

Substrate
ɢ 10X faster netlisting within the Virtuoso ADE Product Suite L and K Extraction

ɢ Provides key post-layout simulation verification R and C Extraction

functionality, such as in-context cross-probing,
back annotation, and single Smart View for multiple
process corners
ɢ Same usability, interface, and integration to support
the Virtuoso ADE Product Suite’s parasitic resimulation
methodology
ɢ DSPF file format output allows direct support Figure 2: Key functionalities of Quantus Extraction Solution
for FastSPICE tools such as Spectre ® eXtensive
Partitioning Simulator (XPS) Multi-corner/temperature extraction
With the rapidly increasing number of process corners at
ɢ Enables faster verification and simulation runtimes
with Spectre X Simulator and Spectre Accelerated advanced nodes, design convergence is becoming a bottleneck
Parallel Simulator (APS) in the design flow process.
For example, signal integrity issues can occur at high-tem-
Design Convergence perature conditions, requiring efficient multi-corner extraction
Silicon Virtual Prototype performance including temperature corners. The Quantus
Early Prototyping solution extracts multiple corners simultaneously while
Default Extraction
Power-Grid Synthesis significantly reducing overall runtime without compromising
on accuracy. In fact, the tool delivers 3X faster performance
Integrated Quantus Extraction Solution

Placement
in multi-corner runs versus single-corner runs done in
Power Routing
parallel. This functionality is available for both digital and
transistor extraction flows. In fact, on the transistor extraction,
Clock-Tree Synthesis the Quantus solution’s Extracted View output can support
multiple process corners in one file, which allows designers to
Post-CTS Optimization perform circuit debugging faster in the Virtuoso ADE Product
Suite and improve productivity—a highly differentiated
Routing
functionality.
Post-Route Post-Route Optimization
+ SI Optimization
Timing/SI Optimization Support for 3nm FinFET processes
Incremental The Quantus solution is fully certified for the 7nm+, 5nm, and
Signoff Extraction
Extraction/ECO
3nm FinFET processes at TSMC. These process nodes
Timing, SI, Power Signoff introduce their own set of parasitic challenges including
Signoff Extraction
multi-patterning (MPT) and accurate modeling of pillar
Figure 1: Enabling in-design in the Innovus environment and bridge vias in addition to other MEOL/FEOL and BEOL
features. All these features have significant impact, if not

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 Quantus Extraction Solution

modeled accurately, for static timing analysis (STA), signal Tight integration with Voltus and Voltus-Fi solutions
EM and IR analysis, and place and route implementation.
For advanced nodes and specifically for FinFET designs,
The Quantus solution has accurately modeled these foundry- there are very complex design rules in EM checks, such
mandated features and passed certification criteria with as complex wire shapes, special width definition, heavy
tighter correlation of RCs to the foundry golden values. direction dependence, via shape rules for fracturing, local
inter- connect M0 rules, etc. It is imperative for FinFET
designs for a parasitic extractor to accurately model these
effects and provide resistance values for accurate EM
checks. In addition to the complex design rules, there is
w/o substrate also a self-heating-effect (SHE) flow at TSMC that requires
a tighter handshake between the parasitic extraction tool
n-well and the EMIR analysis tool. The Quantus and Voltus-Fi
VDD
p-substrate solutions provide such a differentiated flow to our customers
to accurately perform both signal and power net EM-IR. In
Vss fact, it’s the only flow solution available in the market that
provides the level of accuracy and know-how required for
n-well accurate EM and IR analysis.
p-substrate

Figure 3: RF interconnect loss

Lightly doped substrate, Lightly doped substrate Heavily doped substrate,

Better design convergence via integration no guard ring with guard ring connected no guard ring
with Innovus and Virtuoso platforms to ideal power supply

As an integral part of the silicon analysis function inside Figure 4: What-if analysis with noise contour map
the Virtuoso custom IC design platform, the Quantus solution
Integrated Virtual Metal Fill
provides critical parasitic information for optimizing chip
performance and yield. For 28nm and above, metal fill used to be added very late in
the design cycle after timing was closed, which meant that
Essentially, the extraction tool brings the physics of inter-
any additional capacitance that resulted was simply ignored.
connect parasitics into the Virtuoso environment for designing,
This methodology is neither sufficient nor recommended for
characterizing, and optimizing chip layouts. Through the tool’s
FinFET designs. Designers must consider and understand
integration with the Innovus environment, you benefit from
the impact of metal fill during implementation rather than
a seamless solution for timing, IR, EM, signal integrity analysis,
waiting to insert and analyze during signoff. For example,
and power verification. The integration of the two tools equips
at 40nm, the difference in capacitance of not considering
you to reduce design turnaround time by performing incremental
metal fill during implementation and signoff was about 1%.
extraction, use integrated virtual metal fill for faster convergence,
Since then it has grown to more than 4% for 16FF designs,
and to reach timing closure faster by using signoff-accurate
and it is expected that for 10/7nm and below, the impact
extraction data for timing and noise optimization.
will be even higher. Designers started realizing this impact
for their FinFET designs and started mitigating by considering
Tight integration with Tempus solution
metal fill during implementation—signoff metal fill. However,
At advanced nodes with multi-million instance designs, it’s the net impact of this methodology had significant impact
critical to prevent parasitic load, read, and analysis turnaround on runtimes since signoff metal fill in GDS consumes design
time from becoming a bottleneck. The Quantus solution provides closure turnaround time, especially when you have few ECOs
a binary interface and format, RCDB, with the Tempus solution in your optimization phase. The Quantus solution offers
and Innovus environment. RCDB is a random-access format integrated virtual metal fill (IVMF) both in-design in the
that reduces memory footprint. The format offers up to 120X Innovus environment and in the standalone signoff version.
better performance while reading in the SPEF file into the
Tempus solution. In addition, the Quantus solution also offers Advanced parasitic netlist reduction
multi-corner values SPEF, which significantly reduces
One of the challenges introduced due to the introduction of
output generation times, read-in times in the Tempus
FinFET designs is a huge increase in the netlist size. This bloating
solution, and reduction of the SPEF file size. This flow
is due to an increase in number of parasitics and specifically
provides up to 3X overall performance improvement for
R and fin coupling cap (Cc). There is a new modeling layer; the
timing signoff flow, i.e., extraction and STA analysis.
middle interconnect layer or M0VO, which introduces additional

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 Quantus Extraction Solution

interconnect vias that result in an increasing number of Rs. Specifications

The increase in the netlist size significantly impacts simulation
runtimes, which is a costly proposition both in terms of perfor- Packaging
mance and cost of acquisition. The current built-in reduction
capabilities in the parasitic extraction tool needed to be
f Available in L and XL configurations for basic extraction
enhanced significantly to meet the new challenges. The
Quantus solution’s new reduction algorithm is available Foundry
as a built-in capability and as a standalone version that Quantus techfiles (qrctechfile) are:
can reduce netlist size from any third-party parasitic f Certified and supported by TSMC and other foundries
extraction DSPF file.
worldwide

Inductance extraction for GDS and LEF/DEF flows f Flow tested and qualified with foundry process design
kits (PDKs)
Clock distribution networks employ wide wire routing to span
large areas of the die that can lower clock latency and improve f Complemented by development services
performance. Examples of such common routing structures (available from Cadence)
are H-tree, mesh, and fishbone routing. At advanced-process
nodes, clock frequencies are commonly above 1GHz with Format support
ever-faster clock edges. These exacerbate the impact of f Design input: GDSII, LEF/DEF, DFII, OpenAccess
inductance by inducing overshoot and undershoot on clock
waveforms and impact edge rates and shapes. Clock nets f LVS data: Cadence Assura® Physical Verification, Cadence
routed on thick, higher layers are driven by very strong Physical Verification System, Cadence Pegasus™ Verification
buffers, which cause edge rates to go high, indicated by System, and Mentor Graphics Calibre platform
ringing in the signal due to inductance. Inductance effects f Design output: Smart View, Extracted View, DSPF, xDSPF,
bring uncertainty for hold timing and can result in chip failures. SPICE, SPEF, xSPEF, SSPEF
The Quantus solution is a market leader in providing a RLCK
f Direct binary interface to Tempus solution: RCDB and
for GDS flow for transmission lines, and has extended that
multi-corner value SPEF
modeling to LEF/DEF flow for SoC designs.

Platforms
Advanced substrate modeling capability
f Linux 64 bit
RF designers need a tool that extracts parasitic inductance
accurately and evaluates the impact of substrate parasitics on
their designs. Substrate noise coupling is a growing concern Cadence Services and Support
due to higher frequencies, higher integration, smaller feature f Cadence application engineers can answer your technical
sizes, and lower supply voltages. Including the p-substrate questions by telephone, email, or internet—they can also
and n-well as part of the substrate model affects the extract provide technical assistance and custom training.
result and leads to RF interconnect loss. The Quantus solution
f Cadence-certified instructors teach more than 70 courses
includes a full 3D substrate model with full-chip and block-
and bring their real-world experience into the classroom.
level views for accurate simulation and analysis of RFIC
circuits, and equips you to perform what-if analysis for f More than 25 Internet Learning Series (iLS) online
substrate noise distribution. courses allow you the flexibility of training at your own
computer via the internet.
Support for all design types f Cadence Online Support gives you 24x7 online access
With its built-in, advanced functionality, the Quantus solution to a knowledgebase of the latest solutions, technical
supports all design types, including custom/analog and RF, documentation, software downloads, and more.
SerDes, IP/SRAM/ bitcell characterization, memory, power f For more information, please visit www.cadence.com/
MOSFETs, LCD/TFT, and image sensors.
support for support and www.cadence.com/training
for training.

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System Design strategy to turn design concepts into reality. Cadence customers are the world’s
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to boards to systems for the most dynamic market applications. www.cadence.com

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