K153/1886/2021

Waweru Morgan Githiri.

CAT I - EEE 427 ICs

1. Define an integrated circuit (IC). What are the advantages of ICs over discrete
circuits? (4 Marks)
Answer:
An integrated circuit (IC) is a set of electronic components (e.g., resistors, capacitors, transistors)
fabricated on a single semiconductor substrate, typically silicon, to perform a specific function
within one package.
Advantages over discrete circuits:
 Small size: ICs are compact, occupying ~10% of discrete circuit space.
 Low power consumption: More efficient due to integrated design.
 High reliability: Fewer connections reduce failure points.
 Low cost: Mass production on a single wafer.
 Portability: Lightweight and versatile for various applications.
2. Describe the challenges involved with ICs. (4 Marks)
Answer:
 Non-repairable: If one component fails, the entire IC must be replaced.
 Limited power handling: Typically <10 W, unsuitable for high-power applications.
 Fabrication complexity: Requires advanced techniques (e.g., photolithography),
increasing cost.
 Passive component limitations: Capacitors >30 pF and inductors cannot be fabricated
on-chip, requiring external components.
 Leakage currents: Close component proximity causes interference.
 Parameter inflexibility: Fixed values are hard to modify post-fabrication.
3. What are its advantages over discrete circuits? Describe the classification of ICs.
(5 Marks)
Answer:
Advantages: (Repeated from Q1 for clarity) Small size, low power, high reliability, low cost,
portability.
Classification of ICs:
 By Fabrication Technique:
o Monolithic: All components on a single substrate (e.g., silicon). Most common,
uses photolithography.
 o Thin Film: Conductive material deposited on a substrate (e.g., ceramic), suitable
for passive components.
o Thick Film: Similar to thin film but fused in a furnace, used for high-power
passive components.
o Hybrid: Combines monolithic, thin, and thick film, handles analog/digital signals
(5–50 W).
 By Scale of Integration:
o SSI: <100 components (e.g., gates, amplifiers).
o MSI: 100–3,000 components (e.g., filters, registers).
o LSI: 3,000–100,000 components (e.g., microprocessors).
o VLSI: 10,000–1M components (e.g., signal processors).
o ULSI: >1M components (e.g., advanced processors).
 By Application:
o Linear (Analog): Processes continuous signals (e.g., op-amps, filters).
o Digital: Processes binary signals (e.g., logic gates, processors).
o Mixed-Signal: Combines analog and digital (e.g., ADCs, DACs).
4. What are the main components of a monolithic IC? How are they fabricated on a
single chip? (4 Marks)
Answer:
Main Components:
 Active: Transistors (e.g., BJT, MOSFET), diodes.
 Passive: Resistors, capacitors (small, <30 pF).
Fabrication:
 Substrate: A p-type silicon wafer (~200 µm thick) is used.
 Epitaxial Layer: A thin n-type layer (~10 µm) is grown via epitaxy.
 Insulation: SiO₂ layer (~1 µm) is deposited for protection.
 Component Formation:
o Diodes: Formed by diffusing n-type and p-type materials to create a p-n junction.
o Transistors: Sequential diffusion of p-type and n-type materials.
o Resistors: p-type diffusion into n-type regions.
o Capacitors: SiO₂ as dielectric between n-type and metallic plates.
 Interconnections: Metallic deposits (e.g., aluminum) connect components via
photolithography.
 Etching: Removes SiO₂ to expose areas for doping.
5. Describe various levels of integration of ICs, giving examples of each? (6
Marks)
Answer:
  Small Scale Integration (SSI): <100 components. Examples: Logic gates, single-stage
amplifiers, multiplexers.
 Medium Scale Integration (MSI): 100–3,000 components. Examples: Filters, registers,
counters.
 Large Scale Integration (LSI): 3,000–100,000 components. Examples:
Microprocessors, memory chips.
 Very Large Scale Integration (VLSI): 10,000–1M components. Examples: Signal
processors, computer processors.
 Ultra Large Scale Integration (ULSI): >1M components. Examples: Advanced
microprocessors (e.g., Intel Core i7), complex signal processors.
6. Outline the basic steps in the fabrication of a silicon-based integrated circuit. (10
Marks)
Answer:
1. Wafer Preparation:
o Silicon is purified and formed into wafers using Czochralski or Float Zone
methods.
o Wafers are sliced (~200 µm thick), polished for smooth surfaces.
2. Deposition:
o Thin films (e.g., SiO₂, metals) are deposited via chemical (CVD, epitaxy) or
physical (sputtering, evaporation) methods.
3. Oxidation:
o SiO₂ is formed via dry (Si + O2 → SiO2 ) or wet (Si + 2H2 O → SiO2 + 2H2 )
oxidation to insulate/protect.
4. Photolithography:
o Photoresist is applied, patterned using a mask, and exposed to UV light to transfer
circuit patterns.
o Steps: Cleaning, photoresist application, soft bake, mask alignment, exposure,
development, hard bake.
5. Etching:
o Unwanted material is removed via wet (chemical solutions) or dry (reactive ion,
sputtering) etching.
6. Diffusion:
o Dopants (e.g., boron, phosphorus) are introduced to form p-type or n-type regions,
governed by Fick’s Law.
7. Ion Implantation:
o High-energy dopants are implanted (1 keV–1 MeV), followed by annealing to
repair lattice damage.
8. Metallization:
o Aluminum or copper is deposited to form interconnects via evaporation or
sputtering.
9. Testing:
 o Functional and electrical tests ensure chip performance.
10. Packaging:
o Chips are encased in ceramic or plastic packages (e.g., DIP, TO-5) to protect and
enable connections.
7. What is photolithography, and why is it important in IC manufacturing? (3
Marks)
Answer:
Photolithography is the process of transferring circuit patterns onto a wafer using a light-
sensitive photoresist and a mask. A photoresist is applied, exposed to UV light through a mask,
and developed to create patterns for etching or doping.
Importance:
 Enables precise patterning of microscopic components.
 Critical for defining circuit geometry in monolithic ICs.
 Supports high-density integration (e.g., VLSI, ULSI).
8. Explain the role of doping in IC fabrication. What are the differences between p-
type and n-type semiconductors? (4 Marks)
Answer:
Role of Doping:
 Doping introduces impurities (dopants) to alter the electrical properties of silicon,
creating p-type or n-type semiconductors.
 Enables formation of active components (e.g., transistors, diodes) and passive
components (e.g., resistors).
Differences:
 p-type:
o Dopants: Group III elements (e.g., boron).
o Charge carriers: Holes (positive).
o Conductivity: 𝜎𝑝 ≈ 𝑞𝜇𝑝 𝑁𝐴 , where 𝑁𝐴 is acceptor concentration.
 n-type:
o Dopants: Group V elements (e.g., phosphorus).
o Charge carriers: Electrons (negative).
o Conductivity: 𝜎𝑛 ≈ 𝑞𝜇𝑛 𝑁𝐷 , where 𝑁𝐷 is donor concentration.
9. Compare planar technology with trench isolation technology in IC design. (4
Marks)
Answer:
 Planar Technology:
o Components are fabricated on a flat silicon surface using diffusion and oxidation.
 o Isolation: Achieved via p-n junction isolation (reverse-biased junctions).
o Advantages: Simple, cost-effective, widely used in monolithic ICs.
o Disadvantages: Larger area, parasitic capacitances due to junctions.
 Trench Isolation Technology:
o Trenches are etched into the silicon and filled with insulators (e.g., SiO₂).
o Isolation: Physical separation by insulating trenches.
o Advantages: Reduces parasitic capacitances, enables higher density, better for
VLSI/ULSI.
o Disadvantages: More complex, higher fabrication cost.
10. What is an Operational Amplifier? Why it is called so? Describe the equivalent
circuit of an op-amp. (3 Marks)
Answer:
Operational Amplifier (Op-Amp): An IC with high gain, used to perform mathematical
operations (e.g., amplification, integration) in analog circuits.
Why Called So: Named for its ability to perform operations like addition, subtraction, and
amplification in analog computing.
Equivalent Circuit Description:
 Inputs: Two high-impedance inputs (inverting (-), non-inverting (+)).
 Voltage Source: Dependent source with gain 𝐴𝑣 (𝑉+ − 𝑉− ), where 𝐴𝑣 is large (~10^5).
 Output: Low-impedance output with voltage 𝑉out = 𝐴𝑣 (𝑉+ − 𝑉− ).
 Resistances: Input resistance (high, ~MΩ), output resistance (low, ~Ω).
Equivalent Circuit Description:
 Two inputs: Inverting (-) and Non-inverting (+), connected to a differential amplifier.
 A dependent voltage source with gain A_v (typically 10^5) amplifies the difference (V_+
- V_-).
 Input resistance (R_in, ~MΩ) between inputs and ground.
 Output resistance (R_out, ~Ω) in series with the output voltage V_out.
 V_out = A_v (V_+ - V_-).
11. What are the characteristics of an Ideal Op-amp? (4 Marks)
Answer:
 Infinite Open-Loop Gain: 𝐴𝑣 → ∞, so small input differences produce large outputs.
 Infinite Input Impedance: 𝑍in → ∞, drawing no current.
 Zero Output Impedance: 𝑍out = 0, delivering maximum current.
 Infinite Bandwidth: Responds to all frequencies without distortion.
 Zero Offset Voltage: Output is zero when inputs are equal.
 Infinite CMRR: Rejects common-mode signals completely.
  Zero Noise: No internal noise contribution.
12. Draw the equivalent circuit and the pin diagram of a 741 op-amp. (6 Marks)
Answer:
Equivalent Circuit
 Inverting and non-inverting inputs with high input resistance.
 A dependent voltage source with high gain 𝐴𝑣 .
 Low output resistance at the output terminal.
Pin Diagram Description:
 The 741 op-amp is an 8-pin IC, typically in a DIP package.
 Pin Configuration:
o Pin 1: Offset Null
o Pin 2: Inverting Input (-)
o Pin 3: Non-Inverting Input (+)
o Pin 4: V- (Negative Supply)
o Pin 5: Offset Null
o Pin 6: Output
o Pin 7: V+ (Positive Supply)
o Pin 8: No Connection (NC)
Pin Diagram Description:
 8-pin DIP package.
 Pin 1: Offset Null (adjusts input offset voltage).
 Pin 2: Inverting Input (-) (signal input for inverted amplification).
 Pin 3: Non-Inverting Input (+) (signal input for non-inverted amplification).
 Pin 4: V- (negative power supply, e.g., -15V).
 Pin 5: Offset Null (second pin for offset adjustment).
 Pin 6: Output (amplified signal output).
 Pin 7: V+ (positive power supply, e.g., +15V).
 Pin 8: NC (no connection).
13. Distinguish among linear ICs, digital ICs, and mixed-signal ICs. Provide
examples of each. (5 Marks)
Answer:
 Linear (Analog) ICs:
o Process continuous signals with linear input-output relationships.
o Examples: Operational amplifiers (e.g., 741), analog filters, voltage regulators
(e.g., LM317).
 Digital ICs:
 o Process discrete binary signals (0s and 1s) using logic gates or flip-flops.
o Examples: Microprocessors (e.g., Intel 8086), counters, logic gates (e.g., 7400
series).
 Mixed-Signal ICs:
o Combine analog and digital circuits, often using Bi-CMOS technology.
o Examples: Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters
(DACs), mobile phone ICs.
14. Describe the following popular techniques for IC package? (i. Dual-in-line
Pack, ii. Flat Pack, iii. Metal Can Pack, iv. TO Pack)
Answer:
 Dual-in-Line Pack (DIP):
o Rectangular package with two parallel rows of pins (e.g., 14 pins, 7 per side).
o Suitable for PCBs, widely used (e.g., 741 op-amp).
 Flat Pack:
o Thin, rectangular package with pins extending from two sides (e.g., 14 pins).
o Used in compact, high-density applications.
 Metal Can Pack (TO-5):
o Circular metal can resembling a transistor, with 8–12 pins at the bottom.
o Hermetic, used for high-reliability applications.
 TO Pack:
o Similar to Metal Can but includes variations like TO-3 (for power devices).
o Robust, used for ICs requiring heat dissipation.
15. Describe the function of a 555 timer IC. How is it configured in astable mode?
(4 Marks)
Answer:
Function: The 555 timer IC generates precise timing pulses, used as an oscillator or delay
generator in monostable or astable modes.
Astable Mode Configuration:
 Components: Two resistors (𝑅1 , 𝑅2 ), a capacitor (𝐶), and the 555 IC.
 Connections:
o Pin 1: Ground.
o Pin 2 (Trigger): Connected to Pin 6 (Threshold) and capacitor 𝐶.
o Pin 3: Output.
o Pin 4: Reset (connected to Vcc for normal operation).
o Pin 5: Control Voltage (usually bypassed with a 0.01 µF capacitor to ground).
o Pin 6: Connected to 𝐶 and 𝑅2 .
o Pin 7 (Discharge): Connected to junction of 𝑅1 and 𝑅2 .
o Pin 8: Vcc (supply voltage, 5–15 V).
 o 𝑅1 connects Vcc to Pin 7, 𝑅2 connects Pin 7 to Pin 6, 𝐶 connects Pin 6 to ground.
 Operation: Capacitor charges through 𝑅1 + 𝑅2 and discharges through 𝑅2 , producing
continuous pulses.
1.44
 Frequency: 𝑓 = (𝑅 .
1 +2𝑅2 )𝐶

Astable Mode Circuit Description:

 555 IC with 8 pins.
 Pin 1 to ground.
 Pin 2 (Trigger) and Pin 6 (Threshold) connected to capacitor C.
 Pin 3 is the output.
 Pin 4 to Vcc.
 Pin 5 to ground via 0.01 µF capacitor.
 Pin 7 (Discharge) to junction of R1 and R2.
 Pin 8 to Vcc (5–15 V).
 R1 connects Vcc to Pin 7, R2 connects Pin 7 to Pin 6, C connects Pin 6 to ground.
 Frequency: f = 1.44 / [(R1 + 2R2)C].
16. Explain the working of a voltage regulator IC, such as the 7805. What are its
main applications? (3 Marks)
Answer:
Working of 7805:
 The 7805 is a linear voltage regulator IC that provides a fixed +5V output from a higher
input voltage (7–35 V).
 It uses a reference voltage, error amplifier, and pass transistor to maintain a stable output,
compensating for input variations or load changes.
 Includes thermal overload and short-circuit protection.
Applications:
 Power supplies for microcontrollers, sensors, and digital circuits.
 Battery-powered devices requiring stable voltage.
 Embedded systems and consumer electronics.
17. Why is power dissipation a concern in ICs? Explain methods to reduce it. (3
Marks)
Answer:
Why a Concern:

 Power dissipation generates heat, raising chip temperature (𝑇chip = 𝑇ambient +

(𝜃𝑗𝑐 + 𝜃𝑐𝑎 )𝑃𝑑 ), which can degrade performance or cause failure.
 Limits battery life in portable devices.
Methods to Reduce:
 Use low-power technologies (e.g., CMOS instead of BJT).
 Optimize circuit design to minimize switching activity.
 Implement power management (e.g., sleep modes).
 Use efficient packaging with heat sinks or thermal vias.
18. Describe the role of heat sinks and thermal vias in IC packaging. (2 Marks)
Answer:
 Heat Sinks: Metal structures attached to IC packages to dissipate heat, reducing chip
temperature and preventing thermal damage.
 Thermal Vias: Conductive pathways in PCBs that transfer heat from the IC to a heat
sink or ground plane, enhancing thermal management.
19. What are MEMS (Micro-Electro-Mechanical Systems)? How are they used in
ICs? (3 Marks)
Answer:
MEMS: Miniature devices combining mechanical and electrical components on a single chip,
fabricated using IC techniques.
Use in ICs:
 Sensors: Accelerometers (e.g., in smartphones), gyroscopes, pressure sensors.
 Actuators: Micro-mirrors in projectors, microfluidic pumps.
 Integration: Combined with analog/digital ICs for signal processing (e.g., in IoT
devices).
20. Discuss the concept of 3D ICs. What are the benefits and challenges of this
technology? (3 Marks)
Answer:
Concept: 3D ICs stack multiple silicon layers vertically, interconnected via through-silicon vias
(TSVs), increasing density and performance.
Benefits:
 Higher integration density, reducing footprint.
 Shorter interconnects, improving speed and reducing power.
 Enables heterogeneous integration (e.g., logic + memory).
Challenges:
 Complex fabrication, increasing cost.
 Thermal management issues due to stacked layers.
 Testing and reliability concerns for TSVs.
21. Explain Moore's Law. How has it influenced IC design and manufacturing? (3
Marks)
Answer:
Moore’s Law: The number of transistors on an IC doubles approximately every 2 years, leading
to exponential increases in performance and efficiency.
Influence:
 Design: Drives miniaturization, enabling VLSI/ULSI with millions of transistors (e.g.,
Intel Core i7).
 Manufacturing: Spurs advancements in photolithography, doping, and packaging to
achieve smaller feature sizes.
 Applications: Enables complex devices (e.g., smartphones, AI processors) at lower costs.
K153/1886/2021
Waweru Morgan Githiri.

CAT II - EEE 427 ICs

1. What is a multiplexer IC? Design a 4-to-1 multiplexer using logic gates. (2
Marks)
Answer:
Multiplexer IC: A digital IC that selects one of multiple input signals and forwards it to a single
output based on select lines.
4-to-1 Multiplexer Design:
 Inputs: 4 data inputs (I0, I1, I2, I3), 2 select lines (S0, S1).
 Output: Single output (Y).
 ‾ ⋅ 𝑆0
Logic: 𝑌 = (𝐼0 ⋅ 𝑆1 ‾ ) + (𝐼1 ⋅ 𝑆1‾ ⋅ 𝑆0) + (𝐼2 ⋅ 𝑆1 ⋅ 𝑆0 ‾ ) + (𝐼3 ⋅ 𝑆1 ⋅ 𝑆0).
 Gates: Uses AND gates for input-select combinations, OR gate for output.
4-to-1 Multiplexer Logic Diagram Description:
 Inputs: I0, I1, I2, I3 (data), S0, S1 (select).
 Four 3-input AND gates:
o AND1: Inputs I0, ~S1, ~S0.
o AND2: Inputs I1, ~S1, S0.
o AND3: Inputs I2, S1, ~S0.
o AND4: Inputs I3, S1, S0.
 One 4-input OR gate: Combines outputs of AND1, AND2, AND3, AND4 to produce Y.
 Output: Y = (I0.~S1.~S0) + (I1.~S1.S0) + (I2.S1.~S0) + (I3.S1.S0).
2. Explain how ICs are used in communication systems, such as in modulation and
demodulation. (3 Marks)
Answer:
 Modulation:
o ICs like op-amps (e.g., 741) or specialized RF ICs perform amplitude, frequency,
or phase modulation.
o Example: An op-amp-based modulator mixes a baseband signal with a carrier
wave.
 Demodulation:
o ICs (e.g., PLL ICs like 565) extract baseband signals from modulated carriers.
o Example: A PLL IC locks onto the carrier frequency to recover the original
signal.
 Role: ICs provide compact, reliable, low-power solutions for signal processing in radios,
mobile phones, and satellite systems.
3. Discuss the application of ICs in microcontrollers and their role in embedded
systems. (3 Marks)
Answer:
 Microcontrollers:
o ICs integrating CPU, memory (RAM, ROM), and I/O peripherals on a single chip
(e.g., 8051, PIC16F).
o Perform tasks like data processing, control, and communication.
 Role in Embedded Systems:
o Control: Execute firmware to control devices (e.g., washing machines,
automotive ECUs).
o Signal Processing: Handle sensor data (e.g., temperature, motion).
o Communication: Enable interfaces like UART, SPI for IoT devices.
 Benefits: Compact, low-power, programmable for diverse applications.
4. A material layer has a sheet resistivity of 𝑅𝑠 = 50𝛺/square, and the layer
dimensions are 𝐿 = 200𝜇𝑚, 𝑊 = 100𝜇𝑚. Calculate the number of squares in the
layer and determine the total resistance of the layer. (5 Marks)
Answer:
𝐿 200𝜇𝑚
 Number of Squares: Number of squares = 𝑊 = 100𝜇𝑚 = 2.
𝐿
 Total Resistance: 𝑅 = 𝑅𝑠 ⋅ 𝑊 = 50𝛺/square ⋅ 2 = 100𝛺.

Calculation:
 Number of squares = L / W = 200 µm / 100 µm = 2.
 Total resistance = R_s * (L / W) = 50 Ω/square * 2 = 100 Ω.

5. A composite layer consists of two segments in series: Segment 1 (𝑅𝑠 =

60𝛺/square, 𝐿1 = 100𝜇𝑚, 𝑊1 = 50𝜇𝑚), Segment 2 (𝑅𝑠 = 80𝛺/square, 𝐿2 =
200𝜇𝑚, 𝑊2 = 100𝜇𝑚). Find the resistance of each segment and the total
resistance of the composite layer. (4 Marks)
Answer:
 Segment 1:
𝐿 100𝜇𝑚
o Number of squares: 𝑊1 = = 2.
1 50𝜇𝑚
𝐿
o Resistance: 𝑅1 = 𝑅𝑠1 ⋅ 𝑊1 = 60𝛺/square ⋅ 2 = 120𝛺.
1
 Segment 2:
𝐿 200𝜇𝑚
o Number of squares: 𝑊2 = 100𝜇𝑚 = 2.
2
𝐿
o Resistance: 𝑅2 = 𝑅𝑠2 ⋅ 𝑊2 = 80𝛺/square ⋅ 2 = 160𝛺.
2
  Total Resistance (series): 𝑅total = 𝑅1 + 𝑅2 = 120𝛺 + 160𝛺 = 280𝛺.
Calculation:
 Segment 1:
o Number of squares = L1 / W1 = 100 µm / 50 µm = 2.
o R1 = R_s1 * (L1 / W1) = 60 Ω/square * 2 = 120 Ω.
 Segment 2:
o Number of squares = L2 / W2 = 200 µm / 100 µm = 2.
o R2 = R_s2 * (L2 / W2) = 80 Ω/square * 2 = 160 Ω.
 Total resistance = R1 + R2 = 120 Ω + 160 Ω = 280 Ω.
6. A material's sheet resistivity 𝑅𝑠 = 𝑅𝑠0 (1 + 𝛼𝑇), where 𝑅𝑠0 = 50𝛺/square at
𝑇 = 25∘ 𝐶. Calculate 𝑅𝑠 at 𝑇 = 75∘ 𝐶. (3 Marks)
Answer:
 Assume 𝛼 (temperature coefficient) is typical for silicon resistors (~0.001/°C, as not
provided).
 Temperature change: 𝛥𝑇 = 75∘ 𝐶 − 25∘ 𝐶 = 50∘ 𝐶.
 𝑅𝑠 = 𝑅𝑠0 (1 + 𝛼𝛥𝑇) = 50(1 + 0.001 ⋅ 50) = 50(1 + 0.05) = 50 ⋅ 1.05 =
52.5𝛺/square.
Calculation:
 α = 0.001/°C (assumed for silicon).
 ΔT = 75°C - 25°C = 50°C.
 R_s = R_s0 * (1 + α * ΔT) = 50 * (1 + 0.001 * 50) = 50 * 1.05 = 52.5 Ω/square.
7. Define wafer yield and explain its significance in integrated circuit
manufacturing. (4 Marks)
Answer:
Wafer Yield: The percentage of defect-free chips (dies) produced from a wafer, typically 10–
90%.
Significance:
 Cost Efficiency: Higher yield reduces wasted resources, lowering production costs.
 Process Optimization: Guides improvements in fabrication techniques (e.g., reducing
defect density).
 Production Planning: Predicts the number of functional ICs, aiding inventory and
pricing.
 Quality Control: Reflects manufacturing reliability, critical for high-density ICs (e.g.,
VLSI).
8. What is defect density, and how does it affect wafer yield? (3 Marks)
Answer:
Defect Density (D): The number of defects per unit area, expressed as defects/cm².
Effect on Wafer Yield:
 Higher defect density increases the likelihood of defects per chip, reducing yield.
 Yield models (e.g., Poisson: 𝑌 = 𝑒 −𝐴𝐷 ) show yield decreases exponentially with 𝐷 ⋅ 𝐴
(chip area).
 Example: For 𝐷 = 0.02 defects/cm2 , 𝐴 = 1 cm2 , yield is lower than for 𝐷 =
0.01 defects/cm2 .
9. Differentiate between random defects and systematic defects in wafer
manufacturing. (3 Marks)
Answer:
 Random Defects:
o Occur unpredictably due to process variations (e.g., dust particles, impurities).
o Modeled by statistical models (e.g., Poisson).
o Example: Photoresist contamination.
 Systematic Defects:
o Result from equipment or process design flaws, occurring consistently.
o Can be mitigated by process optimization.
o Example: Misaligned masks in photolithography.
10. Describe the Poisson model for defect density and its assumptions. (3 Marks)
Answer:
Poisson Model: 𝑌 = 𝑒 −𝐴𝐷 , where 𝑌 is yield, 𝐴 is chip area, 𝐷 is defect density.
Assumptions:
 Defects are randomly distributed across the wafer.
 Defects are independent (one defect does not influence another).
 Defect density is uniform across the wafer.
 All defects cause chip failure.
11. What are the limitations of the Poisson defect density model? (3 Marks)
Answer:
 Assumes uniform defect distribution, which may not hold for systematic defects.
 Overestimates yield for small chips or low defect densities.
 Ignores defect clustering, common in real processes.
 Assumes all defects are fatal, but some may be benign.
  Less accurate for complex processes with non-uniform defect patterns.
12. Explain the difference between the Poisson, Murphy’s, and Seeds models of
wafer yield prediction. (5 Marks)
Answer:
 Poisson Model: 𝑌 = 𝑒 −𝐴𝐷 .
o Assumes random, uniform defects; simple but overestimates yield for small chips.
 Murphy’s Model:
1−𝑒 −2𝐴𝐷
o First equation: 𝑌 = .
2𝐴𝐷
2
1−𝑒 −𝐴𝐷
o Second equation: 𝑌 = ( ) .
𝐴𝐷
o Accounts for defect clustering, providing a more realistic yield estimate,
especially for larger chips.
 Seeds Model: 𝑌 = 𝑒 −√𝐴𝐷 .
o Assumes defects scale with the square root of chip area, conservative estimate.
o Better for processes with clustered defects but less optimistic than Poisson.
Key Difference: Poisson is simplest but least accurate for complex processes; Murphy’s
balances realism and complexity; Seeds is conservative, accounting for defect clustering.

13. What factors influence the defect density of a wafer during manufacturing? (4
Marks)
Answer:
 Material Quality: Impurities in silicon or dopants increase defects.
 Process Complexity: More steps (e.g., photolithography, etching) raise defect risk.
 Equipment Condition: Worn masks or miscalibrated tools cause systematic defects.
 Environmental Control: Dust or temperature variations introduce random defects.
 Etching/Oxidation: Poor control leads to uneven surfaces or contamination.
 Testing/Packaging: Mishandling can introduce defects post-fabrication.
14. Using the Poisson model, calculate the yield of a wafer that contains 𝑁 = 500
chips each with an area of 𝐴𝑐 = 1 cm2 . The defect density is 𝐷 =
0.02 defects/cm2 . (3 Marks)
Answer:
 Poisson model: 𝑌 = 𝑒 −𝐴𝑐𝐷 .
 𝐴𝑐 𝐷 = 1 ⋅ 0.02 = 0.02.
 𝑌 = 𝑒 −0.02 ≈ 0.9802 = 98.02%.
 Number of functional chips: 500 ⋅ 0.9802 ≈ 490.
Calculation:
 A_c * D = 1 cm² * 0.02 defects/cm² = 0.02.
 Y = e^(-0.02) ≈ 0.9802 = 98.02%.
 Functional chips = 500 * 0.9802 ≈ 490.
15. If the defect density of a manufacturing process improves from 𝐷 =
0.05 defects/cm2 to 𝐷 = 0.01 defects/cm2 . How does the yield change for a chip
area of 2 cm2 using Poisson model? (4 Marks)
Answer:
 Initial Yield:
o 𝐴𝑐 𝐷 = 2 ⋅ 0.05 = 0.1.
o 𝑌1 = 𝑒 −0.1 ≈ 0.9048 = 90.48%.
 Improved Yield:
o 𝐴𝑐 𝐷 = 2 ⋅ 0.01 = 0.02.
o 𝑌2 = 𝑒 −0.02 ≈ 0.9802 = 98.02%.
 Yield Change: 𝑌2 − 𝑌1 = 98.02% − 90.48% = 7.54% increase.
Calculation:
 Initial: A_c * D = 2 cm² * 0.05 defects/cm² = 0.1, Y_1 = e^(-0.1) ≈ 0.9048 = 90.48%.
 Improved: A_c * D = 2 cm² * 0.01 defects/cm² = 0.02, Y_2 = e^(-0.02) ≈ 0.9802 =
98.02%.
 Yield increase = 98.02% - 90.48% = 7.54%.
16. A wafer contains 100 chips, of which 75 are functional. The total wafer area is
300 cm² and each chip occupies 3 cm². Calculate the defect density D using yield
data and the Poisson model. (4 Marks)
Answer:
Functional chips 75
 Yield: 𝑌 = = 100 = 0.75.
Total chips
 Poisson Model: 𝑌 = 𝑒 −𝐴𝑐𝐷 .
 𝐴𝑐 = 3 cm2 .
 0.75 = 𝑒 −3𝐷 .
 ln(0.75) = −3𝐷.
 −0.2877 = −3𝐷.
0.2877
 𝐷= ≈ 0.0959 defects/cm2 .
3

Calculation:
 Y = 75 / 100 = 0.75.
 Y = e^(-A_c * D), A_c = 3 cm².
  0.75 = e^(-3D).
 ln(0.75) = -3D, -0.2877 = -3D.
 D = 0.2877 / 3 ≈ 0.0959 defects/cm².

17. For a chip size 𝐴𝑐 = 1 cm2 and 𝐷 = 0.02 defects/cm2 , calculate and compare
the yield predictions using: i. Poisson model, ii. Murphy’s model, iii. Seeds model.
(5 Marks)
Answer:

 Given: 𝐴𝑐 = 1 cm2 , 𝐷 = 0.02 defects/cm2 , so 𝐴𝑐 𝐷 = 1 ⋅ 0.02 = 0.02.

 Poisson Model: 𝑌 = 𝑒 −𝐴𝑐𝐷 = 𝑒 −0.02 ≈ 0.9802 = 98.02%.
1−𝑒 −2𝐴𝑐 𝐷 1−𝑒 −0.04 1−0.9608 0.0392
 Murphy’s Model (First Equation): 𝑌 = = ≈ = =
2𝐴𝑐 𝐷 0.04 0.04 0.04
0.98 = 98.00%.
 Seeds Model: 𝑌 = 𝑒 −√𝐴𝑐𝐷 = 𝑒 −√0.02 ≈ 𝑒 −0.1414 ≈ 0.8681 = 86.81%.
 Comparison:
o Poisson: 98.02% (most optimistic).
o Murphy’s: 98.00% (slightly lower, accounts for clustering).
o Seeds: 86.81% (most conservative, assumes defect clustering).
Calculation:
 A_c * D = 1 cm² * 0.02 defects/cm² = 0.02.
 Poisson: Y = e^(-0.02) ≈ 0.9802 = 98.02%.
 Murphy’s: Y = (1 - e^(-20.02)) / (20.02) = (1 - 0.9608) / 0.04 = 0.98 = 98.00%.
 Seeds: Y = e^(-sqrt(0.02)) ≈ e^(-0.1414) ≈ 0.8681 = 86.81%.
18. What is a 555 timer IC, and what are its primary applications? (3 Marks)
Answer:
555 Timer IC: A versatile IC used for generating accurate timing pulses in monostable (one-
shot) or astable (oscillator) modes.
Primary Applications:
 Oscillators: Generates square waves for clocks or signals.
 Timers: Produces delays in control circuits.
 Pulse Generators: Used in PWM for motor control.
 Applications: Timers in appliances, frequency dividers, LED flashers.
19. Draw the internal block diagram of a 555 timer IC and explain the function of
each block. (3 Marks)
Answer:
Block Diagram Description:
  Comparators (2): Compare trigger (Pin 2) and threshold (Pin 6) voltages with reference
voltages (1/3 Vcc, 2/3 Vcc).
 Flip-Flop: Stores state, controls discharge transistor and output.
 Discharge Transistor: Discharges external capacitor in astable/monostable modes.
 Output Stage: Drives the output (Pin 3) high or low.
 Voltage Divider: Divides Vcc into 1/3 Vcc and 2/3 Vcc for comparators.
Block Diagram Description:
 Two comparators: Compare Pin 2 (Trigger) with 1/3 Vcc, Pin 6 (Threshold) with 2/3
Vcc.
 Flip-Flop: Receives comparator outputs, sets/resets to control discharge transistor and
output.
 Discharge Transistor: Connected to Pin 7, discharges external capacitor.
 Output Stage: Pin 3, delivers high/low signal.
 Voltage Divider: Three resistors divide Vcc into 1/3 Vcc and 2/3 Vcc for comparators.
20. List the pin configuration of a 555 timer IC and describe the function of each
pin. (4 Marks)
Answer:
 Pin 1 (Ground): Connects to circuit ground.
 Pin 2 (Trigger): Initiates timing cycle when voltage falls below 1/3 Vcc.
 Pin 3 (Output): Delivers high/low output signal.
 Pin 4 (Reset): Resets timer when pulled low; tie to Vcc for normal operation.
 Pin 5 (Control Voltage): Adjusts comparator thresholds (usually bypassed with 0.01 µF
capacitor).
 Pin 6 (Threshold): Monitors capacitor voltage, ends timing cycle when >2/3 Vcc.
 Pin 7 (Discharge): Connects to external capacitor to discharge it.
 Pin 8 (Vcc): Supply voltage (5–15 V).
21. Explain the significance of the control voltage pin in a 555 timer IC. (3 Marks)
Answer:
 Control Voltage Pin (Pin 5): Modifies the reference voltages of the internal comparators
(normally 1/3 Vcc and 2/3 Vcc).
 Significance:
o Allows external voltage to adjust timing characteristics (e.g., pulse width,
frequency) in astable/monostable modes.
o Enables modulation (e.g., PWM) by varying comparator thresholds.
o Typically bypassed with a 0.01 µF capacitor to ground to stabilize against noise.
Notes
 All calculations and diagrams are based on the provided documents and standard IC
principles.
 For questions requiring diagrams (e.g., multiplexer, 555 timer), I provided textual
descriptions within <xaiArtifact/> tags, as image generation requires confirmation.
 If you need further clarification, specific calculations, or actual image generation (after
confirmation), please let me know!