Digital Electronics and µ-processors
(EC2L006)
Lecture 11: Synchronous Sequential Logic
SR Latch---Recap
• Under normal conditions, both inputs of the latch remain at 0
unless the state has to be changed.
• The application of a momentary 1 to the S input causes the
latch to go to the set state.
• The S input must go back to 0 before any other changes take
place.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 2
SR Latch---Recap
• After both inputs return to 0, it is then possible to shift to the
reset state by momentary applying a 1 to the R input. The 1
can then be removed from R, where upon the circuit remains
in the reset state.
• Thus, when both inputs S and R are equal to 0, the latch can
be in either the set or the reset state, depending on which
input was most recently a 1.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 3
SR Latch / S’R’ Latch
• SR latch with NAND gates requires a 0 signal to change its
state.
• The inputs signals for the NAND-latch are the complement
values used for the NOR latch.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 4
SR Latch with control input
• The outputs of the NAND gates stay at the logic-1 level as
long as the enable signal remains at 0.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 5
D Latch (Transparent Latch)
• How is D-latch structurally different than the SR latch?
• D latch eliminates the undesirable condition of the
indeterminate state that occurs in the SR latch (Q = Q’ = 1).
If D = 1, Q = 1 -> ‘set’ state
If D = 0, Q = 0 -> ‘reset’ state
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 6
D Latch (Contd.)
• The D latch receives that designation from its ability to hold data in
its internal storage.
• The output follows changes in the data input as long as the enable
input is asserted. This situation provides a path from input D to the
output, and for this reason, the circuit is often called a transparent
latch.
• When the enable input signal is de-asserted, the binary information
that was present at the data input at the time the transition occurred
is retained (i.e., stored) at the Q output until the enable input is
asserted again.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 7
Graphic Symbols for Latches
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 8
Flip-Flops
• A flip-flop is a state of a latch that can be switched by
momentary change in the control input.
• This momentary change is called a trigger and the transition it
causes is said to trigger the flip-flop.
• The D-latch is a flip-flop that is triggered every time the pulse
goes to a high or logic level 1.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 9
Edge-Triggered Flip-Flop
• The circuit samples the D input and changes its output at the negative edge
of the clock, Clk.
• When the clock is 0, the output of the inverter is 1. The slave latch is
enabled and its output Q is equal to the master output Y. The master latch
is disabled (Clk = 0).
• When the Clk changes to high, D input is transferred to the master latch.
The slave remains disabled as long as En is low. Any change in the input
changes Y, but not Q.
• The output of the flip-flop can change when CLK makes a transition 1 0
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 10
Edge-Triggered Flip-Flop: Graphic Symbols
• The most economical and efficient flip-flop constructed is the
edge-triggered D flip-flop since it requires the smallest
number of gates.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 11
JK Flip-Flop
• When J = 1 and K = 0, D = 1 next clock edge sets output to 1.
• When J = 0 and K = 1, D = 0 next clock edge resets output to 0.
• When J = 1 and K = 1, D= Q’ next clock edge complements
output.
• When J = 0 and K = 0, D= Q next clock edge leaves output
unchanged.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 12
T Flip-Flop
• The T (toggle) flip-flop is a complementing flip-flop and can be
obtained from a JK flip-flop when inputs J and K are tied
together.
• When T = 0 (J = K = 0), a clock edge does not change the
output. When T = 1 (J = K = 1), a clock edge complements
the output.
• The T flip-flop can also be constructed with a D flip-flop and
an exclusive-OR gate.
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 13
Characteristic Tables and Equations
[12/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 14
Thank you!!!
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