CIT 314 MODULE 2

MODULE 2 MEMORY ADDRESSING AND

HIERARCHY SYSTEMS

2.1 INTRODUCTION

A memory address is a unique identifier used by a device or CPU for

data tracking. This binary address is defined by an ordered and finite
sequence allowing the CPU to track the location of each memory byte.
Addressing modes are an aspect of the instruction set architecture in
most central processing unit (CPU) designs. The various addressing
modes that are defined in a given instruction set architecture define how
the machine language instructions in that architecture identify
the operand(s) of each instruction. An addressing mode specifies how to
calculate the effective memory address of an operand by using
information held in registers and/or constants contained within a
machine instruction or elsewhere.

In computer programming, addressing modes are primarily of interest to

those who write in assembly languages and to compiler writers. For a
related concept see orthogonal instruction set which deals with the
ability of any instruction to use any addressing mode.

This module is divided into three units. The first unit explains memory
addressing and the various modes available. Unit two explains the
elements of memory hierarchy while the last unit takes on virtual
memory control systems. All these are given below.

UNIT ONE: Memory Addressing

UNIT TWO: Elements of Memory Hierarchy
UNIT THREE: Virtual Memory Control System

UNIT 1 MEMORY ADDRESSING

CONTENTS

1.0 Introduction
2.0 Intended Learning Outcomes (ILOS)
3.0 Main Contents
3.1.1 What is memory addressing mode?
3.1.2 Modes of addressing
3.1.3 Number of addressing modes
3.1.4 Advantages of addressing modes
3.1.5 Uses of addressing modes
4.0 Self-Assessment Exercises
5.0 Conclusion
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CIT314 COMPUTER ARCHITECTURE AND ORGANIZATION II

6.0 Summary
7.0 References/Further Reading

1.0 INTRODUCTION

In computing, a memory address is a reference to a specific memory

location used at various levels by software and hardware. Memory
addresses are fixed-length sequences of digits conventionally displayed
and manipulated as unsigned integers. Such numerical semantic bases
itself upon features of CPU, as well upon use of the memory like an
array endorsed by various programming languages. There are many
ways to locate data and instructions in primary memory and these
methods are called “memory address modes”.

Memory address modes determine the method used within the program
to access data either from the Cache or the RAM.

2.0 INTENDED LEARNING OUTCOMES (ILOs)

The objectives of this module include;

 To ensure students have adequate knowledge of memory addressing

systems
 To aid students know how to deal with various modes of addressing
 To help students understand basic calculations involving memory
addresses

3.1.1 What is memory addressing mode?

Memory addressing mode is the method by which an instruction

operand is specified. One of the functions of a microprocessor is to
execute a sequence of instructions or programs stored in a computer
memory (register) in order to perform a particular task. The way the
operands are chosen during program execution is dependent on the
addressing mode of the instruction. The addressing mode specifies a rule
for interpreting or modifying the address field of the instruction before
the operand is actually referenced. This technique is used by the
computers to give programming versatility to the user by providing such
facilities as pointers to memory, counters for loop control, indexing of
data, and program relocation. And as well reduce the number of bits in
the addressing field of the instruction.

However, there are basic requirement for the operation to take effect.
First, the must be an operator to indicate what action to take and
secondly, there must be an operand that portray the data to be executed.
For instance; if the numbers 5 and 2 are to be added to have a result, it
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could be expressed numerically as 5 + 2. In this expression, our operator

is (+), or expansion, and the numbers 5 and 2 are our operands. It is
important to tell the machine in a microprocessor how to get the
operands to perform the task. The data stored in the operation code is the
operand value or the result. A word that defines the address of an
operand that is stored in memory is the effective address. The
availability of the addressing modes gives the experienced assembly
language programmer flexibility for writing programs that are more
efficient with respect to the number of instructions and execution time.

3.1.2 Modes of addressing

There are many methods for defining or obtaining the effective address
of an operators directly from the register. Such approaches are known as
modes of addressing. The programmes are usually written in a high-
level language, as it is a simple way to describe the variables and
operations to be performed on the variables by the programmer. The
following are the modes of addressing;

ADDRESSING EXAMPLE MEANING WHEN TO

MODES INSTRUCTION USED
Register ADD R4, R3 R4 <- R4 + R3 When a value
is in a register
Immediate ADD R4, #3 R4 <- R4 + R3 For constants
indexed ADD R3, (R1 + R3 <- R3 + M When
R2) [R1 + R2] addressing
array;
R1 = base of
array
R2 = index
amount
Register Indirect ADD R4, (R1) R4 <- R4 + M Accessing
[R1] using a
pointer or a
computed
address
Auto Increment ADD R1, (R2)+ R1 <- R1 + M Use for
[R2] stopping
R2 <- R2 + d through array
in a loop.
R2 = start of
array
D = size of an
element
Auto Decrement ADD R1, - (R2) R2 <- R2 – d Same as auto
R1 <- R1 + M increment.
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[R2] Both can also

be used to
implement a
stack push
and pop
Direct ADD R1, (1001) R1 <- R1 + M Useful in
[1001] accessing
static data

Note :
< - = assignment
M = the name for memory: M[R1] refers to contents of memory location
whose address is given by the contents of R1

3.1.3 Number of addressing modes

The number of addressing modes are as follow;

a. Register Addressing Mode

In this mode the operands are in registers that reside within the
CPU. The particular register is selected from a register field in
the instruction. A k-bit field can specify any one of 2' registers.

b. Direct Addressing Mode and Indirect Address mode

In Direct Address Mode, the effective address is equal to the
address part of the instruction. The operand resides in memory
and its address is given directly by the address field of the
instruction. In a branch-type instruction the address field specifies
the actual branch address. But in the Indirect Address Mode, the
address field of the instruction gives the address where the
effective address is stored in memory. Control fetches the
instruction from memory and uses its address part to access
memory again to read the effective address. A few addressing
modes require that the address field of the instruction be added to
the content of a specific register in the CPU. The effective
address in these modes is obtained from the following
computation:

Effective address = address part of instruction + content of

CPU register.
The CPU register used in the computation may be the program
counter, an index register, or a base register. In either case we
have a different addressing mode which is used for a different
application.

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c. Immediate Addressing Mode

In this mode the operand is specified in the instruction itself. In
other words, an immediate-mode instruction has an operand field
rather than an address field. The operand field contains the actual
operand to be used in conjunction with the operation specified in
the instruction. Immediate-mode instructions are useful for
initializing registers to a constant value. It was mentioned
previously that the address field of an instruction may specify
either a memory word or a processor register. When the address
field specifies a processor register, the instruction is said to be in
the register mode.

d. Register Indirect Addressing Mode

In this mode the instruction specifies a register in the CPU whose
contents give the address of the operand in memory. In other
words, the selected register contains the address of the operand
rather than the operand itself. Before using a register indirect
mode instruction, the programmer must ensure that the memory
address of the operand is placed in the processor register with a
previous instruction. A reference to the register is then equivalent
to specifying a memory address. The advantage of a register
indirect mode instruction is that the address field of the
instruction uses fewer bits to select a register than would have
been required to specify a memory address directly.

e. Indexed Addressing Mode

In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address. The
index register is a special CPU register that contains an index
value. The address field of the instruction defines the beginning
address of a data array in memory. Each operand in the array is
stored in memory relative to the beginning address. The distance
between the beginning address and the address of the operand is
the index value stored in the index register. Any operand in the
array can be accessed with the same instruction provided that the
index register contains the correct index value. The index register
can be incremented to facilitate access to consecutive operands.
Note that if an index type instruction does not include an address
field in its format, the instruction converts to the register indirect
mode of operation. Some computers dedicate one CPU register to
function solely as an index register. This register is involved
implicitly when the index-mode instruction is used. In computers
with many processor registers, any one of the CPU registers can
contain the index number. In such a case the register must be
specified explicitly in a register field within the instruction
format.
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f. Auto Increment Mode and Auto Decrement Mode

This is similar to the register indirect mode except that the
register is incremented or decremented after (or before) its value
is used to access memory. When the address stored in the register
refers to a table of data in memory, it is necessary to increment or
decrement the register after every access to the table. This can be
achieved by using the increment or decrement instruction.
However, because it is such a common requirement, some
computers incorporate a special mode that automatically
increments or decrements the content of the register after data
access. The address field of an instruction is used by the control
unit in the CPU to obtain the operand from memory. Sometimes
the value given in the address field is the address of the operand,
but sometimes it is just an address from which the address of the
operand is calculated. To differentiate among the various
addressing modes it is necessary to distinguish between the
address part of the instruction and the effective address used by
the control when executing the instruction. The effective address
is defined to be the memory address obtained from the
computation dictated by the given addressing mode. The effective
address is the address of the operand in a computational type
instruction. It is the address where control branches in response to
a branch-type instruction.

g. Relative Addressing Mode:

In this mode the content of the program counter is added to the
address part of the instruction in order to obtain the effective
address. The address part of the instruction is usually a signed
number which can be either positive or negative. When this
number is added to the content of the program counter, the result
produces an effective address whose position in memory is
relative to the address of the next instruction. For instance, let’s
assume that the program counter contains the number 682 and the
address part of the instruction contains the number 21. The
instruction at location 682 is read from memory during the fetch
phase and the program counter is then incremented by one to 683.
The effective address computation for the relative address mode
is 683 + 21 = 704. This is 21 memory locations forward from the
address of the next instruction. Relative addressing is often used
with branch-type instructions when the branch address is in the
area surrounding the instruction word itself. It results in a shorter
address field in the instruction format since the relative address
can be specified with a smaller number of bits compared to the
number of bits required to designate the entire memory address.

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3.1.4 Advantages of addressing modes

The advantages of using the addressing mode are as follow;

a. To provide the user with programming flexibility by offering

such facilities as memory pointers, loop control counters, data
indexing, and programme displacement.
b. To decrease the counting of bits in the instruction pointing area.

3.1.5 Uses of addressing modes

Some direction set models, for instance, Intel x86 and its substitutions,
had a pile ground-breaking area direction. This plays out an assessment
of the fruitful operand location, anyway rather following up on that
memory territory, it stacks the area that might have been gotten in the
register. This may be significant during passing the area of a display part
to a browse mode. It can similarly be a fairly precarious strategy for
achieving a greater number of includes than average in one direction; for
example, using such a direction with the keeping an eye on mode “base+
index+ balance” (unequivocal underneath) licenses one to assemble two
registers and a consistent into a solitary unit in one direction.

4.0 Self-Assessment Exercises

1. Why do you need memory addressing?

2. What are the existent modes for memory addressing?
3. Using a tabular format, show various addressing modes, meaning
and their meanings.

4.0 CONCLUSION

The computer register is defined as the small subset of the data that has
fast accessible memory in the central processing unit. For the execution
of different computer instructions and programs type of registers are
used. There are numerous categories of computer registers that are
available for the execution of instructions. The registers can be
categorized by their size, functions, or names. These registers are used
to store the data temporarily and perform the execution of computer
instructions and can be also used to store results in it. The processing
speed of registers is the fastest to another data set.

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6.0 SUMMARY

In this unit, you learnt that;

For the central processing unit, there are various type of computer
registers defined that has some specific role during the execution of the
instruction. All these registers have some particular role like data-related
operations, fetching or storing of data, and many more operations. And
the instructions stored in the register are executed by the processor of
the central processing unit.

7.0 REFERENCES/FURTHER READING

John L. Hennessy and David A. Patterson (2012) Computer

Architecture; A Qualitative Approach. Fifth (Ed.), Library of
Congress Cataloging in Publication Data. URL:
https://www.academia.edu/22618699/Computer_Architecture_A_
Quantitative_Approach_5th_edition_

Keith R. Mobley (2004) Maintenance Fundamentals. 2nd (Ed.), Elsevier

Butterworth Heinemann. URL:
https://www.elsevier.com/books/maintenance-
fundamentals/mobley/978-0-7506-7798-1

Mostafa Abd-El-Barr and Hesham El-Rewini (2005) Fundamentals of

Computer Organization and Architecture. A John Wiley and Sons,
Inc Publication. URL:
https://books.google.com/books/about/Fundamentals_of_Computer
_Organization_an.html?id=m6uFlL41TlIC
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UNIT 2 ELEMENTS OF MEMORY HIERARCHY

CONTENTS

1.0 Introduction
2.0 Intended Learning Outcomes (ILOS)
3.0 Main ContentsWhat is memory hierarchy
3.2.1 Memory hierarchy diagram
3.2.2 Characteristics of memory diagram
3.2.3 Memory hierarchy design
3.2.4 Advantages of memory hierarchy

4.0 Self-Assessment Exercises

5.0 Conclusion
6.0 Summary
7.0 References/Further Reading

1.0 INTRODUCTION

In the design of the computer system, a processor, as well as a large

amount of memory devices, has been used. However, the main problem
is, these parts are expensive. So the memory organization of the system
can be done by memory hierarchy. It has several levels of memory with
different performance rates. But all these can supply an exact purpose,
such that the access time can be reduced. The memory hierarchy was
developed depending upon the behavior of the program.

2.0 INTENDED LEARNING OUTCOMES (ILOs)

 To carefully study through the elements of memory hierarchy

 To guide students on how to understand basic memory issues in
computing based on the hierarchies learnt

3.2.1 What is memory hierarchy?

Memory is one of the important units in any computer system. Its serves
as a storage for all the processed and the unprocessed data or programs
in a computer system. However, due to the fact that most computer users
often stored large amount of files in their computer memory devices, the
use of one memory device in a computer system has become inefficient
and unsatisfactory. This is because only one memory cannot contain all
the files needed by the computer users and when the memory is large, it
decreases the speed of the processor and the general performance of the
computer system.
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Therefore, to curb this challenges, memory unit must be divided into

smaller memories for more storage, speedy program executions and the
enhancement of the processor performance. The recently accessed files
or programs must be placed in the fastest memory. Since the memory
with large capacity is cheap and slow and the memory with smaller
capacity is fast and costly. The organization of smaller memories to hold
the recently accessed files or programs closer to the CPU is term
memory hierarchy. These memories are successively larger as they
move away from the CPU.

The strength and performance of memory hierarchy can be measured

using the model below;

Memory_Stall_Cycles = IC*Mem_Refs * Miss_Rate * Miss_Penalty

Where,
IC = Instruction Count
Mem_Refs = Memory References per Instruction
Miss_Rate = Fraction of Accesses that are not in the
cache
Miss_Penalty = Additional time to service the Miss

The memory hierarchy system encompasses all the storage devices used
in a computer system. Its ranges from the cache memory, which is
smaller in size but faster in speed to a relatively auxiliary memory which
is larger in size but slower in speed. The smaller the size of the memory
the costlier it becomes.

The element of the memory hierarchy includes

a. Cache memory,
b. Main memory and
c. Auxiliary memory

 The cache memory is the fastest and smallest memory. It is

easily accessible by the CPU because it closer to the CPU. Cache
memory is very costly compare to the main memory and the
auxiliary memory.

 The main memory also known as primary memory,

communicates directly to the CPU. Its also communicates to the
auxiliary memory through the I/O processor. During program
execution, the files that are not currently needed by the CPU are
often moved to the auxiliary storage devices in order to create
space in the main memory for the currently needed files to be
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stored. The main memory is made up of Random Access Memory

(RAM) and Read Only Memory (ROM).

 The auxiliary memory is very large in size and relatively slow

in speed. Its includes the magnetic tapes and the magnetic disks
which are used for the storage and backup of removable files.
The auxiliary memories store programs that are not currently
needed by the CPU. They are very cheap when compare to the
both cache and main memories.

3.2.2 Memory hierarchy diagram

The memory hierarchy system encompasses all the storage devices used
in a computer system. Its ranges from fastest but smaller in size (cache
memory) to a relatively fast but small in size (main memory) and more
slowly but larger in size (auxiliary memory). The cache memory is the
smallest and fastest storage device, it is place closer to the CPU for easy
accessed by the processor logic. More so, cache memory is helps to
enhance the processing speed of the system by making available
currently needed programs and data to the CPU at a very high speed. Its
stores segment of programs currently processed by the CPU as well as
the temporary data frequently needed in the current calculation

The main memory communicates directly to the CPU. It also very fast in
speed and small in size. Its communicates to the auxiliary memories
through the input/ output processor. The main memory provides a
communication link between other storage devices. It contains the
currently accessed data or programs. The unwanted data are transferred
to the auxiliary memories to create more space in the main memory for
the currently needed data to be stored. If the CPU needs a program that
is outside the main memory, the main memory will call in the program
from the auxiliary memories via the input/output processor. The main
difference between cache and main memories is the access time and
processing logic. The processor logic is often faster than that of the main
memory access time.

The auxiliary memory is made up of the magnetic tape and the magnetic
disk. They are employ in the system to store and backup large volume of
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Main Cache
Memor Memor

I/O
Processo CPU

data or programs that are not currently needed by the processor. In

summary, the essence of dividing this memory into different levels of
memory hierarchy is to make storage more efficient, reliable and
economical for the users. As the storage capacity of the memory
increases, the cost per bit for storing binary information decreases and
the access time of the memory becomes longer. The diagram of a
memory hierarchy in presented in Figure 2.1

2.3 Characteristics of Memory Hierarchy

There are numbers of parameters that characterized memory hierarchy.

They stand as the principle on which all the levels of the memory
hierarchy operate. These characteristics are;

a. Access type,
b. Capacity,
c. Cycle time,
d. Latency,
e. Bandwidth, and
f. Cost

a. Access Time: refers to the action that physically takes place

during a read or write operation. When a data or program is
moved from the top of the memory hierarchy to the bottom , the
access time automatically increases. Hence, the interval of time at
which the data are request to read or write is called Access time.
b. Capacity: the capacity of a memory hierarchy often increased
when a data is moved from the top of the memory hierarchy to
the bottom. The capacity of a memory hierarchy is the total
amount of data a memory can store. The capacity of a memory
level is usually measured in bytes.
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c. Cycle time: is defined as the time elapsed from the start of a read
operation to the start of a subsequent read.

d. Latency: is defined as the time interval between the request for

information and the access to the first bit of that information.

e. Bandwidth: this measures the number of bits that can be

accessed per second.

f. Cost: the cost of a memory level is usually specified as dollars

per megabytes. When the data is moved from bottom of the
memory hierarchy to top, the cost for each bit increases
automatically. This means that an internal memory is expensive
compared to external memory.

3.2.4 Memory Hierarchy Design

The memory in a computer can be divided into five hierarchies based on

the speed as well as use. The processor can move from one level to
another based on its requirements. The five hierarchies in the memory
are registers, cache, main memory, magnetic discs, and magnetic tapes.
The first three hierarchies are the primary memory (volatile memories)
which mean when there is no power, and then automatically they lose
their stored data. The last two hierarchies are the secondary memories
(nonvolatile) which means they store the data permanently. Generally, a
memory element is a set of storage devices that stores binary in bits.
This set of storage devices can be classified into two categories such as;
the primary memory and the secondary memory. The primary memory
is directly accessible by the processor, it is also known as internal
memory. This memory includes main, cache, as well as CPU registers.
Furthermore, the secondary memory can only be accessed by the
processor through an input/output module, and it is also known as
external memory. This memory includes an optical disk, magnetic disk,
and magnetic tape. The memory hierarchy design is presented in Figure
2.2 below.

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Increase in capacity & access time

CPU Level 0
Register
Cache Memory

Increase in cost per bit

Level 1
(SRAM)
Main Memory
Level 2
(DRAM)

Magnetic Disk Level 3

(Disk storage)
Optical Disk
Level 4
Magnetic Tape

Figure 2.2.2: Memory hierarchy design

1. operation. Normally, a complex instruction set computer uses

many registers to accept main memory.
2. Cache Memory: Cache memory can also be found in the
processor, however rarely it may be another integrated circuit
(IC) which is separated into levels. The cache holds the chunk of
data which are frequently used from main memory. When the
processor has a single core then it will have two (or) more cache
levels rarely. Present multi-core processors will be having three,
2-levels for each one core, and one level is shared.
3. Main Memory: This is the memory unit that communicate
directly to the CPU. It is the primary storage unit in a computer
system. the main stores data or program currently used by the
CPU during operation. It is very fast in terms of access time and
it is made up of RAM and ROM.
4. Magnetic Disks: The magnetic disks is a circular plates
fabricated of plastic or metal by magnetized material. Frequently,
two faces of the disk are utilized as well as many disks may be
stacked on one spindle by read or write heads obtainable on every
plane. All the disks in computer turn jointly at high speed. The
tracks in the computer are nothing but bits which are stored
within the magnetized plane in spots next to concentric circles.
These are usually separated into sections which are named as
sectors.
5. Magnetic Tape: This tape is a normal magnetic recording which
is designed with a slender magnetizable covering on an extended,
plastic film of the thin strip. This is mainly used to back up huge
data. Whenever the computer requires to access a strip, first it
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will mount to access the data. Once the data is allowed, then it
will be unmounted. The access time of memory will be slower
within magnetic strip as well as it will take a few minutes for
accessing a strip.

3.2.5 Advantages of Memory Hierarchy

The advantages of a memory hierarchy include the following.

a. Memory distributing is simple and economical

b. Removes external destruction
c. Data can be spread all over
d. Permits demand paging & pre-paging
e. Swapping will be more proficient

4.0 CONCLUSION

In the design of the computer system, a processor, as well as a large

amount of memory devices, has been used. However, the main problem
is, these parts are expensive. So, the memory organization of the system
can be done by memory hierarchy. It has several levels of memory with
different performance rates. But all these can supply an exact purpose,
such that the access time can be reduced. The memory hierarchy was
developed depending upon the behavior of the program.

5.0 SUMMARY

In this unit, you learnt that;

Memory hierarchy is a multi-level structure that as the distance from the
processor increases, the size of the memories and the access time both
increase. Performance is the key reason for having a memory hierarchy.
The faster memories are more expensive per bit and thus tend to be
smaller. The goal is to present the user with as much memory as is
Computer Architecture 2019/2020 #8 : Memory Hierarchy 2 available in
the cheapest technology, while providing access at the speed offered by
the fastest memory. The data is similarly hierarchical – a level closer to
the processor is generally a subset of any level further away, and all the
data is stored at the lowest memory level.

6.0 SELF-ASSESSMENT EXERCISES

1. What is a memory hierarchy?

2. Give the design, characteristics and advantages of a memory
hierarchy
3. Give the difference between cache memory and main memory
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7.0 REFERENCES/FURTHER READING

Ailamaki AG, DeWitt DJ., Hill MD, Wood DA. DBMSs on a modern
processor: where does time go? In: Proceedings of the 25th
International Conference on Very Large Data Bases; 1999. p.
266–77. URL: https://www.semanticscholar.org/paper/DBMSs-
on-a-Modern-Processor%3A-Where-Does-Time-Go-Ailamaki-
DeWitt/54b92179ede08158e2cf605f5e9f264ca06c01ff

Denning PJ. The working set model for program behaviour. Commun
ACM. 1968;11(5):323–33. URL:
https://denninginstitute.com/pjd/PUBS/WSModel_1968.pdf

Manegold S. Understanding, modeling, and improving main-memory

database performance. PhD thesis, Universiteit van Amsterdam,
Amsterdam, The Netherlands; 2002. URL:
https://ir.cwi.nl/pub/14301/14301B.pdf

Shatdal A, Kant C, Naughton J. Cache conscious algorithms for

relational query processing. In: Proceedings of the 20th
International Conference on Very Large Data Bases; 1994. p.
510–2. URL https://www.semanticscholar.org/paper/Cache-
Conscious-Algorithms-for-Relational-Query-Shatdal-
Kant/12c2693c5e27a301a030933822c1c6da1558c267
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UNIT 3 VIRTUAL MEMORY CONTROL SYSTEMS

CONTENTS

1.0 Introduction
2.0 Intended Learning Outcomes (ILOS)
3.0 Main Contents
3.3.1 Memory management systems
3.3.2 Paging
3.3.3 Address mapping using paging
3.3.4 Address mapping using segments
3.3.5 Address mapping using segmented paging
3.3.6 Multi-programming
3.3.7 Virtual machines/memory and protection
3.3.8 Hierarchical memory systems
3.3.9 Drawbacks that occur in virtual memories
4.0 Self-Assessment Exercises
5.0 Conclusion
6.0 Summary
7.0 References/Further Reading

1.0 INTRODUCTION

Virtual memory is a memory management technique where secondary

memory can be used as if it were a part of the main memory. Virtual
memory is a common technique used in a computer's operating system
(OS). Virtual memory uses both hardware and software to enable a
computer to compensate for physical memory shortages, temporarily
transferring data from random access memory (RAM) to disk storage.
Mapping chunks of memory to disk files enables a computer to treat
secondary memory as though it were main memory.

2.0 INTENDED LEARNING OUTCOMES (ILOs)

 To analyze virtual control systems

 To understand system pagination and memory protection
methods

3.3.1 Memory management systems

In a multiprogramming system, there is a need for a high capacity

memory. This is because most of the programs are often stored in the
memory. The programs must be moved around the memory to change
the space of memory used by a particular program and as well prevent a
program from altering other programs during read and write. Hence, the
memory management system becomes necessary. The movement of
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these programs from one level of memory hierarchy to another is known

as memory management. Memory management system encompasses
both the hardware and the software in its operations. It is the collection
of hardware and software procedures for managing all the programs
stored in the memory. The memory management software is part of the
main operating system available in many computers. In this study, we
are concerned with the hardware unit of the memory management
system.

Components of memory management system:

The principal components of the memory management system are;

a. A facility for dynamic storage relocation that maps logical

memory references into physical memory addresses.
b. A provision for sharing common programs stored in memory by
different users.
c. Protection of information against unauthorized access between
users and preventing users from changing operating system
functions. The dynamic storage relocation hardware is a mapping
process similar to the paging system

3.3.2 Paging

In memory management, paging can be described as a storage

mechanism that allows operating system (OS) to retrieve processes from
the secondary storage into the main memory in the form of pages. It is a
function of memory management where a computer will store and
retrieve data from a device’s secondary storage to the primary storage.
Memory management is a crucial aspect of any computing device, and
paging specifically is important to the implementation of virtual
memory. In the Paging method, the main memory is divided into small
fixed-size blocks of physical memory, which is called frames. The size
of a frame should be kept the same as that of a page to have maximum
utilization of the main memory and to avoid external fragmentation.
Paging is used for faster access to data, and it is a logical concept. For
instance, if the main memory size is 16 KB and Frame size is 1 KB.
Here, the main memory will be divided into the collection of 16 frames
of 1 KB each. There are 4 separate processes in the system that is A1,
A2, A3, and A4 of 4 KB each. Here, all the processes are divided into
pages of 1 KB each so that operating system can store one page in one
frame. At the beginning of the process, all the frames remain empty so
that all the pages of the processes will get stored in a contiguous way. A
typical paging process is presented in Figure 2.3.1.

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Main memory 1 Frame = 1KB

Process A 1 16KB
(Collection of frames) Frame size = Page size
A1 A 1
Paging
A
A11
A1 Paging
A
A12 Process
A2 A2
A1
A
A 2 A2
A1 A3
Process A22
A2
A3 A
A33
A2
A3 A 3 Process A 4
A
A34 A4
A3
A
A44 A4
A3
A4 A4
Figure 2.3.1: Paging process A4

From the above diagram you can see that A2 and A4 are moved to the
waiting state after some time. Therefore, eight frames become empty,
and so other pages can be loaded in that empty blocks. The process A5
of size 8 pages (8 KB) are waiting in the ready queue.

In conclusion, paging is a function of memory management where a

computer will store and retrieve data from a device’s secondary storage
to the primary storage. Memory management is a crucial aspect of any
computing device, and paging specifically is important to the
implementation of virtual memory.

3.3.2.1 Paging Protection

The paging process should be protected by using the concept of insertion

of an additional bit called Valid/Invalid bit. Paging Memory protection
in paging is achieved by associating protection bits with each page.
These bits are associated with each page table entry and specify
protection on the corresponding page.

3.3.2.2 Advantages and Disadvantages of Paging

Advantages

The following are the advantages of using Paging method:

a. No need for external Fragmentation

b. Swapping is easy between equal-sized pages and page frames.
c. Easy to use memory management algorithm

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Disadvantages

The following are the disadvantages of using Paging method

a. May cause Internal fragmentation

b. Page tables consume additional memory.
c. Multi-level paging may lead to memory reference overhead.

3.3.3 Address mapping using paging

The table implementation of the address mapping is simplified if the

information in the address space and the memory space are each divided
into groups of fixed size. The physical memory is broken down into
groups of equal size called blocks, which may range from 64 to 4096
words each. The term page refers to groups of address space of the same
size. For example, if a page or block consists of 1K words, address
space is divided into 1024 pages and main memory is divided into 32
blocks. Although both a page and a block are split into groups of 1K
words, a page refers to the organization of address space, while a block
refers to the organization of memory space. The programs are also
considered to be split into pages. Portions of programs are moved from
auxiliary memory to main memory in records equal to the size of a page.
The term page frame is sometimes used to denote a block.

For instance, if a computer has an address space of 8K and a memory

space of 4K. If we split each into groups of 1K words we obtain eight
pages and four blocks. At any given time, up to four pages of address
space may reside in main memory in any one of the four blocks. The
mapping from address space to memory space is facilitated if each
virtual address is considered to be represented by two numbers: a page
number address and a line within the page. In a computer with '1! words
per page, p bits are used to specify a line address and the remaining
high-order bits of the virtual address specify the page number. a virtual
address has 13 bits. Since each page consists of 210 = 1024 words, the
high order three bits of a virtual address will specify one of the eight
pages and the low-order 10 bits give the line address within the page.
Note that the line address in address space and memory space is the
same; the only mapping required is from a page number to a block
number. The organization of the memory mapping table in a paged
system is shown in Figure 3.1. The memory-page table consists of eight
words, one for each page. The address in the page table denotes the page
number and the content of the word gives the block number where that
page is stored in main memory. The table shows that pages 1, 2, 5, and 6
are now available in main memory in blocks 3, 0, 1, and 2, respectively.
A presence bit in each location indicates whether the page has been
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transferred from auxiliary memory into main memory. A 0 in the

presence bit indicates that this page is not available in main memory.
The CPU references a word in memory with a virtual address of 13 bits.
The three high-order bits of the virtual address specify a page number
and also an address for the memory-page table. The content of the word
in the memory page table at the page number address is read out into the
memory table buffer register. If the presence bit is a 1, the block number
thus read is transferred to the two high-order bits of the main memory
address register. The line number from the virtual address is transferred
into the 10 low-order bits of the memory address register. A read signal
to main memory transfers the content of the word to the main memory
buffer register ready to be used by the CPU. If the presence bit in the
word read from the page table is 0, it signifies that the content of the
word referenced by the virtual address does not reside in main memory.
A call to the operating system is then generated to fetch the required
page from auxiliary memory and place it into main memory before
resuming computation.

Page no.
101 0 1 Line
0 1 0No.
10011 Virtual Address
Presence bit
Table 000 0
Address
001
010 11
00 11
Block 0
011 01 0101010011
100 00 Block 1
Main Memory
101
110
111 01
10 110 Block 2
Address Register
Block 3
01 1
Memory Page Table

Figure 2.3.2. Memory Table in Paged System MBR

3.3.4 Address mapping using segments

Another mapping process similar to paging system is the dynamic

storage relocation hardware. Due to the large size of program and its
logical structures, the fixed page size employ in the virtual memory
system has really pose a lot of challenges in memory management.
During program execution, the speed of the processor is usually
affected. However, it is very appropriate to disintegrate these programs
and data into segments for effective management and execution. A
segment is a set of logically related instructions or data elements
associated with a given name. Its can be generated by the operating
system or by the programmer. Examples of segments include an array of
data, a subroutine, a table of symbols, or a user's program.
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The address generated by a segmented program is called a logical

address. This is similar to a virtual address except that logical address
space is associated with variable-length segments rather than fixed-
length pages. The logical address may be larger than the physical
memory address as in virtual memory, but it may also be equal, and
sometimes even smaller than the length of the physical memory address.
In addition to relocation information, each segment has protection
information associated with it. Shared programs are placed in a unique
segment in each user's logical address space so that a single physical
copy can be shared. The function of the memory management unit is to
map logical addresses into physical addresses similar to the virtual
memory mapping concept.

3.3.5 Address mapping using segmented paging

One of the properties of logical space is that it uses variable-length

segments. The length of each segment is allowed to grow and contract
according to the needs of the program being executed. One way of
specifying the length of a segment is by associating with it a number of
equal-size pages. To see how this is done, consider the logical address
shown in Figure2.3.3. The logical address is partitioned into three fields.
The segment field specifies a segment number. The page field specifies
the page within the segment and the word field gives the specific word
within the page. A page field of k bits can specify up to 2' pages. A
segment number may be associated with just one page or with as many
as 1!-pages. Thus the length of a segment would vary according to the
number of pages that are assigned to it.
Logical Address
Segment Page Word

Segment Table

Block Word

Figure 2.3.3 Address mapping using segmented paging

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The mapping of the logical address into a physical address is done by

means of two tables, as shown in Figure 3.3. The segment number of the
logical address specifies the address for the segment table. The entry in
the segment table is a pointer address for a page table base. The page
table base is added to the page number given in the logical address. The
sum produces a pointer address to an entry in the page table. The value
found in the page table provides the block number in physical memory.
The concatenation of the block field with the word field produces the
final physical mapped address. The two mapping tables may be stored in
two separate small memories or in main memory. In either case, a
memory reference from the CPU will require three accesses to memory:
one from the segment table, one from the page table, and the third from
main memory. This would slow the system significantly when compared
to a conventional system that requires only one reference to memory. To
avoid this speed penalty, a fast associative memory is used to hold the
most recently referenced table entries. This type of memory is
sometimes called a translation look aside buffer, abbreviated TLB. Thus
the mapping process is first attempted by associative search with the
given segment and page numbers. If it succeeds, the mapping delay is
only that of the associative memory. If no match occurs, the slower table
mapping of Figure 3.3 is used and the result transformed into the
associative memory for future reference.

3.3.6 Multi-programming

Multiprogramming is the basic form of parallel processing in which

several programs are run at the same time on a single processor. Since
there is only one processor, there can be no true simultaneous execution
of different programs. Instead, the operating system executes part of one
program, then part of another, and so on. To the user it appears that all
programs are executing at the same time. More so, if the machine has
the capability of causing an interrupt after a specified time interval, then
the operating system will execute each program for a given length of
time, regain control, and then execute another program for a given
length of time, and so on. When this mechanism is not in place, the
operating system has no choice but to begin to execute a program with
the expectation, but not the certainty, that the program will eventually
return control to the operating system.

If the machine has the capability of protecting memory, then a bug in

one program may interfere with the execution of other programs. In a
system without memory protection, one program can change the
contents of storage assigned to other programs or even the storage
assigned to the operating system. The resulting system crashes are not
only disruptive, they may be very difficult to debug since it may not be
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obvious which of several programs is at fault. Multiprogramming

operating system has the ability to execute multiple programs using one
processor machine. For example, a user can use MS-Excel , download
apps, transfer data from one point to another point, Firefox or Google
Chrome browser, and more at a same time. Multiprogramming operating
system allows to execute multiple processes by monitoring their process
states and switching in between processes. It executes multiple programs
to avoid CPU and memory underutilization. It is also called as
Multiprogram Task System. It is faster in processing than Batch
Processing system

3.3.6.1. Advantages and Disadvantages of Multiprogramming

Below are the Advantages and disadvantages of Multiprogramming

Advantages of Multiprogramming:

a. CPU never becomes idle

b. Efficient resources utilization
c. Response time is shorter
d. Short time jobs completed faster than long time jobs
e. Increased Throughput

Disadvantages of Multiprogramming:

a. Long time jobs have to wait long

b. Tracking all processes sometimes difficult
c. CPU scheduling is required
d. Requires efficient memory management
e. User interaction not possible during program execution

3.3.7 Virtual machines/memory and protection

Memory protection can be assigned to the physical address or the logical

address. The protection of memory through the physical address can be
done by assigning to each block in memory a number of protection bits
that indicate the type of access allowed to its corresponding block.
Every time a page is moved from one block to another it would be
necessary to update the block protection bits. A much better place to
apply protection is in the logical address space rather than the physical
address space. This can be done by including protection information
within the segment table or segment register of the memory
management hardware. The content of each entry in the segment table or
a segment register is called a descriptor. A typical descriptor would
contain, in addition to a base address field, one or two additional fields
for protection purposes. A typical format for a segment descriptor is
shown in Figure 3.2. The base address field gives the base of the page
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table address in a segmented-page organization or the block base

address in a segment register organization. This is the address used in
mapping from a logical to the physical address. The length field gives
the segment size by specifying the maximum number of pages assigned
to the segment. The length field is compared against the page number in
the logical address. A size violation occurs if the page number falls
outside the segment length boundary. Thus a given program and its data
cannot access memory not assigned to it by the operating system.

Base address Length Protection

Figure 2.3.4: Format of a typical segment description

The protection field in a segment descriptor specifies the access rights

available to the particular segment. In a segmented-page organization,
each entry in the page table may have its own protection field to
describe the access rights of each page. The protection information is set
into the descriptor by the master control program of the operating
system. Some of the access rights of interest that are used for protecting
the programs residing in memory are:

 Full read and write privileges

 Read only (write protection)
 Execute only (program protection)
 System only (operating system protection)

Full read and write privileges are given to a program when it is

executing its own instructions. Write protection is useful for sharing
system programs such as utility programs and other library routines.
These system programs are stored in an area of memory where they can
be shared by many users. They can be read by all programs, but no
writing is allowed. This protects them from being changed by other
programs. The execute-only condition protects programs from being
copied. It re-stricts the segment to be referenced only during the
instruction fetch phase but not during the execute phase. Thus it allows
the users to execute the segment program instructions but prevents them
from reading the instructions as data for the purpose of copying their
content. Portions of the operating system will reside in memory at any
given time. These system programs must be protected by making them
inaccessible to unauthorized users. The operating system protection
condition is placed in the descriptors of all operating system programs to
prevent the occasional user from accessing operating system segments.

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3.3.8 Hierarchical memory systems

In the Computer System Design, Memory Hierarchy is used to enhance

the organization of memory such that it can minimize the access time. It
was developed based on a program behavior known as locality of
references. Hierarchical memory system is the collection of storage units
or devices together. The memory unit stores the binary information in
the form of bits. Generally, memory/storage is classified into 2
categories:

 External Memory or Secondary Memory: This is a permanent

storage (non-volatile) and does not lose any data when power is
switched off. It is made up of Magnetic Disk, Optical Disk,
Magnetic Tape i.e. peripheral storage devices which are
accessible by the processor via I/O Module.
 Internal Memory or Primary Memory: This memory is
volatile in nature. it loses its data, when power is switched off. It
is made up of Main Memory, Cache Memory & CPU registers.
This is directly accessible by the processor.

Properties of Hierarchical Memory Organization

There are three important properties for maintaining consistency in the

memory hierarchy these three properties are;

 Inclusion
 Coherence and
 Locality.

3.3.9 Drawbacks that occur in virtual memories

The following are the drawbacks of using virtual memory:

 Applications may run slower if the system is using virtual

memory.
 Likely takes more time to switch between applications.
 Offers lesser hard drive space for your use.
 It reduces system stability.

SELF-ASSESSMENT EXERCISE

1. What are the properties of hierarchical memory organization?

2. Explain the concept of memory protection
3. How do you perform address mapping using segments?

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4.0 CONCLUSION

The memory hierarchy system encompasses all the storage devices used
in a computer system. Its ranges from fastest but smaller in size (cache
memory) to a relatively fast but small in size (main memory) and slower
but larger in size (auxiliary memory). A memory element is a set of
storage devices that stores binary in bits. They include; register, cache
memory, main memory, magnetic disk and magnetic tape. This set of
storage devices can be classified into two categories such as; the primary
memory and the secondary memory.

5.0 SUMMARY

In this unit, you learnt that;

 Memory addresses act just like the indexes of a normal array. The
computer can access any address in memory at any time (hence
the name "random access memory").
 It can also group bytes together as it needs to form larger
variables, arrays, and structures.
 Memory hierarchy is the hierarchy of memory and storage
devices found in a computer system.
 It ranges from the slowest but high capacity auxiliary memory to
the fastest but low capacity cache memory.
 Memory hierarchy is employed to balance this trade-off.

6.0 TUTOR MARKED ASSIGNMENT

1. What is an effective address?

2. Explain Auto increment and decrement modes as related to
memory addressing
3. Give concise explanations of the modes of addressing available
4. Explain memory hierarchy with the aid of a diagram
5. Explain on the parameters that characterize memory hierarchy
6. Explain address mapping using paging
7. What is multi-programming?

7.0 REFERENCES/FURTHER READING

Rob Williams (2006) Computer System Architecture; ANetwork

Approach. 2 (Ed.), Prentice Hall. URL:
https://dokumen.pub/computer-systems-architecture-a-
networking-approach-with-cd-rom-2nd-ed-9780321340795-
0321340795-9781405890588-1405890584.html
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William Stallings (2003) Computer Organization Architecture;

Designing for Performance Six Ed. Prentice Hall. URL
http://williamstallings.com/ComputerOrganization/

William Stallings (2019) Computer Organization and Architecture;

Designing for Performance. 11 (Ed.), Pearson. URL:
https://www.pearson.com/us/higher-education/program/Stallings-
Pearson-e-Text-for-Computer-Organization-and-Architecture-Access-
Code-Card-11th-Edition/PGM2043621.html.

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