DIRECT MEMORY ACCESS
Dr. Gargi Alavani
Department of CS & IS
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Direct Memory Access (DMA)
● DMA I/O technique provides direct access to the memory
while the microprocessor is temporarily disabled.
● Allows data to be transferred between memory and the
I/O device at a rate that is limited only by the speed of the
memory components in the system or the DMA controller.
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Why DMA?
● CPU initiates the transfer and can go back to executing other instructions
while the DMA controller handles the transfer.
● Since DMA can work in parallel with the CPU (depending on system
architecture), overall system throughput improves.
● Transferring data between RAM and:
○ Disk drives
○ Audio cards
○ Network interface cards
○ GPUs or other peripherals
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BASIC DMA OPERATION
● HOLD is sampled in any clocking cycle
● When the processor recognizes the hold, it stops
executing software and enters hld cycles
● HOLD input has higher priority than INTR or NMI
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BASIC DMA OPERATION
● HLDA becomes active to indicate processor has placed its
buses at high impedance state
○ There are a few clock cycles between the time that HOLD
changes and until HLDA changes.
● HLDA output is a signal to the external requesting device that
the microprocessor has relinquished control of its memory and
I/O space.
● HOLD input -> a DMA request input
● HLDA output -> a DMA grant signal.
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BASIC DMA OPERATION
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Basic DMA Definitions
● Direct memory accesses normally occur between an I/O device
and memory without the use of the microprocessor.
○ A DMA read transfers data from the memory to the I/O
device.
○ A DMA write transfers data from an I/O device to memory.
● Memory and I/O are controlled simultaneously.
○ which is why the system contains separate memory and I/O
control signals.
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Basic DMA Definitions
● A DMA read causes both the 𝑀𝑅𝐷𝐶 and 𝐼𝑂𝑊𝐶 signals to activate
simultaneously
○ transferring data from the memory to the I/O device.
● A DMA write causes the MWTC and 𝐼𝑂𝑅𝐶 signals to both activate.
● These control bus signals are available to all microprocessors in the Intel
family except the 8086/8088 system.
● The 8086/8088 require their generation with either a system controller or a
circuit shown in next slide for control bus signal generation.
● The DMA controller provides the memory with its address and a signal from
the controller 𝐷𝐴𝐶𝐾 selects the I/O device during the DMA transfer.
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Basic DMA Definitions
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Basic DMA Definitions
● Data transfer speed is determined by speed of memory device or a
DMA controller.
○ If memory speed is 50 ns, DMA transfers occur at rates up to 1/50
ns or 20M Bytes per second
○ If DMA controller functions at a maximum rate of 15MHz with
50ns memory, maximum transfer rate is 15 MHz because the
DMA controller is slower than the memory
● In many cases, the DMA controller slows the speed of the system
when transfers occur.
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Basic DMA Definitions
● The switch to serial data transfers in modern computer systems, DMA is
becoming less important.
● The PCI Express bus, which is serial, transfers data at rates that exceed
DMA transfers.
● Even the SATA (serial ATA) interface for disk drives uses serial transfers at
the rate of 300 Mbps, which has replaced DMA transfers for hard disk drives.
● Serial transfers on main-boards (motherboards) between components that use
serial techniques can approach 20 Gbps for the PCI Express connection.
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The 8237 DMA Controller
● The 8237 DMA controller supplies the memory and I/O
with control signals and memory address information
during the DMA transfer.
● The 8237 is actually a special-purpose microprocessor
whose job is high-speed data transfer between memory
and the I/O.
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The 8237 DMA Controller
● The 8237 is a four-channel device that is compatible with the 8086/8088
microprocessors.
● The 8237 can be expanded to include any number of DMA channel inputs,
although four channels seem to be adequate for many small systems.
● The 8237 is capable of DMA transfers at rates of up to 1.6M bytes per
second.
● Each channel is capable of addressing a full 64K-byte section of memory and
can transfer up to 64K bytes with a single programming.
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The 8237 DMA Controller Pin-out
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8237A-5 programmable DMA controller
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The 8237 DMA Controller Pin-out
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The 8237 DMA Controller Pin-out
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The 8237 DMA Controller Pin-out
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The 8237 DMA Controller Pin-out
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The 8237 DMA Controller Pin-out
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The 8237 DMA Controller Pin-out
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Internal Registers
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Internal Registers
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Command Register
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Mode Register
● The mode register programs the
mode of operation for a channel.
Note that each channel has its
own mode register, as selected
by bit positions 1 and 0.
● The remaining bits of the mode
register select the operation,
auto-initialization,
increment/decrement, and mode
for the channel
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Mode Register
● Demand mode transfers data until an
external EOP is input or until the DREQ
input becomes inactive.
● Single mode releases the HOLD after
each byte of data is transferred. If the
DREQ pin is held active, the 8237 again
requests a DMA transfer through the
DRQ line to the microprocessor’s HOLD
input.
● Block mode automatically transfers the
number of bytes indicated by the count
register for the channel. DREQ need not
be held active through the block mode
transfer.
● Cascade mode is used when more than
one 8237 is present in a system.
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Bus request register
● The bus request register
is used to request a DMA
transfer via software
● This is very useful in
memory-to-memory
transfers, where an
external signal is not
available to begin the
DMA transfer.
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Mask register set/reset
● The mask register set/reset
sets or clears the channel
mask
● If the mask is set, the channel
is disabled.
● Recall that the RESET signal
sets all channel masks to
disable them.
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The mask register
● clears or sets all of the masks
with one command instead of
individual channels, as with
the MRSR.
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The Status Register
● The status register shows the status of
each DMA channel
● The TC bits indicate whether the
channel has reached its terminal count
(transferred all its bytes). Whenever the
terminal count is reached, the DMA
transfer is terminated for most modes of
operation.
● The request bits indicate whether the
DREQ input for a given channel is
active.
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THANK YOU
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