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Digital Logic and Computer Architecture 20ITC05

The document is an examination paper for the B.E. (IT, IT-AI&DS) III Semester at Chaitanya Bharathi Institute of Technology, covering topics in Digital Logic and Computer Architecture. It consists of two parts: Part A with five questions worth 15 marks and Part B with five questions worth 45 marks, including topics like Boolean functions, flip-flops, multiplexers, and memory management. The exam is designed to assess students' understanding of digital logic and computer architecture concepts.

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14 views2 pages

Digital Logic and Computer Architecture 20ITC05

The document is an examination paper for the B.E. (IT, IT-AI&DS) III Semester at Chaitanya Bharathi Institute of Technology, covering topics in Digital Logic and Computer Architecture. It consists of two parts: Part A with five questions worth 15 marks and Part B with five questions worth 45 marks, including topics like Boolean functions, flip-flops, multiplexers, and memory management. The exam is designed to assess students' understanding of digital logic and computer architecture concepts.

Uploaded by

sowmyadell680
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Code No.

: 20ITC05

CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY (Autonomous)


B.E. (IT, IT-AI&DS) III Sem (Main) Examination February/March 2022
Digital Logic and Computer Architecture
Time: 3 Hours Max Marks: 60
Note: Answer ALL questions from Part-A & Part –B (Internal Choice) at one place in the
same order
Part - A
(5Q X 3M = 15 Marks)
M CO BT
1 Minimize the following Boolean function using three-variable map (3) 1 3
F(A,B,C) =Σm (0,1,2,4,5,6)
2 Solve the given arithmetic operations using 2’s complement representation (3) 2 3
i) (+39) + (-12)
ii) (-39) – (-12)
3 Classify program control instructions. (3) 3 3
4 Define vectored and non-vectored interrupt. (3) 4 1
5 A computer uses RAM chips of 1024*1 capacity. How many chips are (3) 5 4
needed, and how should their address lines be connected to provide a
memory capacity of 1024 bytes.

Part – B
(5Q X 9M = 45 Marks)
M CO BT
6 (a) Simplify the following function in product of sums form and realize (5) 1 3
using NOR gates only
F(w,x,y,z) = M (2,3,4,5,6,7,11,14,15)
(b) Write the excitation tables for SR,D, JK and T flip-flops (4) 1 2
(OR)
7 (a) What is the significance of Edge triggered flip-flop? (3) 1 2
(b) Simplify the following function in sum of products form and realize (6) 1 3
using NAND gates only
F(w,x,y,z) = m (0,2,8,9,10,11,14,15)

8 (a) Construct a 16-to-1 line multiplexer with two 8-to-1 line multiplexers (5) 2 2
and one 2-to-1 line multiplexer. Use block diagram representation.
(b) Convert the following numbers with indicated bases to decimal (4) 2 3
i) (12121)3 ii) (198)10
(OR)
9 (a) Construct a 4-to-16 decoder with 2-to-4 line decoders with an enable (5) 2 2
input.
(b) Represent the number (+46.5)10 as a floating point binary number with (4) 2 3
24 bits. The normalized fraction mantissa has 16 bits and the exponent
has 8 bits

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Code No.: 20ITC05
10 (a) Explain data manipulation instructions with examples. (5) 3 3
(b) State the major characteristics of a RISC processor. (4) 3 2
(OR)
11 (a) Draw the bus organization for CPU and write the operations performed (5) 3 2
by MUX, ALU and decoder.
(b) Given the 16-bit value 1010101010101010. What operation must be (4) 3 3
performed in order to
i) clear to 0 the first 8 bits ii) clear to 0 the last 8 bits.
iii) Set to 1 the last 8 bits. iv) complement the middle 8 bits.

12 (a) With a block diagram explain the DMA transfer in a computer system. (5) 4 2
(b) How data transfer can be performed using asynchronous serial (4) 4 2
communication interface.
(OR)
13 (a) Analyze the general computer register organization with a neat block (5) 4 3
diagram.
(b) Draw the block diagram of Memory connection to the CPU and (4) 4 2
explain.

14 (a) How address mapping is done using pages. Illustrate the same with an (5) 5 3
example.
(b) Define a memory management system. Write its basic components. (4) 5 2
(OR)
15 (a) What is associative memory and explain its hardware organization. (5) 5 2
(b) Write the three types of mapping procedures used in cache memory (4) 5 2
and briefly explain one of them.
******

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