Digital Logic & Design
UNIT III
Contents
1. Binary Parallel Adder
2. Look-ahead Carry Generator
3. ROM
4. PLA
Binary Parallel Adder
➢The Parallel binary adder is a combinational circuit consists of various
full adders in parallel structure.
➢ So that when more than 1-bit numbers are to be added, then there can
be full adder for every column for the addition.
➢The number of full adders in a parallel binary adder depends on the
number of bits present in the number for the addition.
➢If 4-bits numbers are to be added, then there will be 4-full adder in the
parallel binary adder.
• The full-adder forms the sum of two bits and a previous carry.
• Two binary numbers of n bits each can be added by means of this
circuit.
• When pair of bits are added through the full adder, the circuit
produces a carry to be used with the pair of bits one higher significant
position.
• The bits are added with full-adders, starting from the lest significant
position, to from the sum bit and carry bit.
• The sum of two n-bit binary numbers A and B, can be generated in
two ways: either in serial fashion or in parallel.
• The serial addition method uses only one fulladder circuit and a
storage device to hold the generated output carry and sum.
• The parallel method uses n full-adder circuit.
• A binary parallel adder is a digital function that produces the
arithmetic sum of two binary numbers in parallel.
• An n-bit parallel adder requires n full-adders.
• It can be constructed from 4-bit, 2-bit and 1- bit full-adders ICs by
cascading several packages.
• The 4-bit binary parallel adder is a typical example of an MSI
function.
• It can be used in many applications involving arithmetic operations.
• The application of this MSI function to the design of a combinational
circuit is demonstrated in the example of BCD to excess1 code
converter.
Structure of Parallel Adder
➢Parallel adder nothing but a cascade of several full adders.
➢The number of full adders used will depend on the number of bits in
the binary digits which require to be added.
Figure 5. Parallel adder example
CARRY PROPAGATION
• The addition of two binary numbers in parallel implies that all the
bits of the augend and the addend are available for computation at
the same time.
• As in any combinational circuit, the signal must propagate through
gates before the correct output sum is available in output terminals.
• The total propagation time is equal to the propagation delay of
typical gate times the number of gate levels in the circuit.
• The longest propagation delay time in a parallel adder is the time it
takes the carry to propagate through the full-adders.
• The number of gate levels for the carry propagation can be found
from the circuit of the full adder.
• The signal from the carry to the output carry (Ci+1) propagates
through 2 gate levels.
• If there are four full-adders in the parallel adder, the output carry C5
would have 2*4=8 gate levels from C1 to C5.
• The total propagation time in the adder would be the propagation
time in one half adder plus eight gate levels.
• For an n-bit parallel adder, there are 2n gate levels for the carry to
propagate through.
• The carry propagation time is a limiting factor on the speed with
which two numbers are added in parallel.
• All other arithmetic operations are implemented by successive
additions, the time consumed during the addition process is very
critical.
• One way to reduce the carry propagation delay time is to employ
faster gates with reduced delays.
• Another solution is to increase the equipment complexity in such a
way that the carry delay time is reduced.
Look Ahead Carry Generation
➢A look ahead carry adder or fast adder is a type of adder used in
digital logic.
➢A look ahead carry adder improves speed by reducing the amount of
time required to determine carry bits.
➢Carry look ahead depends on calculating for each digit position,
whether that position is going to propagate a carry if one comes in
from in from the right.
➢Combining these calculated values to be able to deduce quickly
whether, for each group of digits, that group is going to propagate a
carry that comes in from the right.
Look-ahead carry
• If we define two variables:
• Gi is called a carry generated and it produced an output carry when
both Ai and Bi one.
• Pi is called a carry propagate because it is the term associated with
the propagation of the carry Ci to Ci+1
• The output sum and carry can be expressed as:
• The boolean functions for the carry output of each stage are:
• C1 = G0 + P0C0
• C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0) = G1 + P1G0 + P1P0C0
• C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
• C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
• The general expression is :------
• Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + ……. PiPi-1….P2P1G0 + PiPi-1
….P1P0C0 .
• Circuit diagram of a look–ahead carry generator shown in figure 1 and 2.
Figure 1: Look-ahead carry generator
4-bit Full-adders with look-ahead carry:
Figure 2: Look-ahead carry generator
Programmable Logic Device (PLD)
➢A Programmable Logic Device (PLD) is an IC (Integrated Circuit) with internal logic
gates connected through electronic paths that behave similar to fuses.
➢In the original state, all the fuses are intact, but when we program these devices, we
blow away certain fuses along the paths that must be removed to achieve a particular
configuration.
➢And this is what happens in ROM, ROM consists of nothing but basic logic gates
arranged in such a way that they store the specified bits.
➢Typically, a PLD can have hundreds to millions of gates interconnected through
hundreds to thousands of internal paths.
Programmable Logic Array (PLA)
➢Programmable Logic Array is a type of PLDs (programmable logic
devices), and these are mainly used for designing combination logic
mutually by sequential logic.
➢The main difference among these two is that PAL can be designed with a
collection of AND gates and fixed collection of OR gates whereas PLA can
be designed with a programmable array of AND although a fixed collection
of OR gate.
➢A programmable logic device offers a simple as well as flexible logic
circuit designing.
➢The number of functions implemented in PLA is limited.
➢The speed of PLA is high.
ROM and PLA
➢Read-Only Memory (ROM) is the primary memory unit of any
computer system along with the Random Access Memory (RAM), but
unlike RAM, in ROM, the binary information is stored permanently.
➢Now, this information to be stored is provided by the designer and is
then stored inside the ROM.
➢Once, it is stored, it remains within the unit, even when power is
turned off and on again.
➢The information is embedded in the ROM, in the form of bits, by a
process known as programming the ROM.
Q.1) Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and
generate an output binary number equal to the square of the input number.
Q.2) Give the logic implementation of a 32X4 bit ROM using a decoder of a suitable size.
Q.3) Give the logic implementation of a 8X4 bit ROM using a decoder of a suitable size.
Solution 2: A 32X4 bit ROM is to be implemented. It consist of 32 words of four bits each. There must be
five input lines that form the binary numbers from 0 through 31 for the address. The five inputs are
decoded into 32 distinct outputs by means of a 5X 32 decoder. Each output of the decoder represents a
memory address. The 32 outputs of the decoder are connected to each of the four OR gates.
Figure shows this implementation:
Solution 3: A 8X4 bit ROM is to be implemented. It consist of 8 words of four bits each. There must be 3
input lines that form the binary numbers from 0 through 7 for the address. The five inputs are decoded into 8
distinct outputs by means of a 3X8 decoder. Each output of the decoder represents a memory address. The 8
outputs of the decoder are connected to each of the four OR gates.
Figure shows this implementation:
Q.4) Types of ROMs?
1. Mask Programmable read only memory (MROM)
2. Programmable read-only memory (PROM)
3. Erasable programmable read-only memory (EPROM)
4. Electrically erasable and programmable read-only memory (EEPROM)
Q. 5) Implement the following two Boolean functions with a PLA:
F1 (A, B, C) = ε m(0. 1, 2, 4)
F2(A, B, C) = ε m(0, 5, 6, 7)
Solution: The k-maps for the functions F1 and F2, their minimization, and the minimal expressions for
both the true and complement forms of those in sum of products are shown in figure for finding the
minimal in true form, consider thje 1son the map and for finding the minimal in complement form
consider the 0s on the map.
Considering the 1s of F1
F1(T) = A’C’+B’C’+A’B’
Considering the 0s of F1
F1’ = AB+AC+BC
Therefore,
F1(C ) = (AB+AC+BC)’
Considering the 1s of F2
F2(T) = A’B’C’+AB+AC
Considering the 0s of F2
F2’ = AB’C’+A’B+A’C
Therefore,
F2(C ) = (AB’C’+A’B+A’C)’
Out of all the combinations that gives the minimum number of product terms is:
F1(C ) = (AB+AC+BC)’
F2(T) = A’B’C’+AB+AC
This gives 4 distinct items: AB, AC, BC and A’B’C’
