FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern

Generator
Yuayng Ye Zonghui Wang Zun Xue
Southeast University Southeast University Southeast University
Nanjing, Jiangsu, China Nanjing, Jiangsu, China Nanjing, Jiangsu, China
[email protected] [email protected] [email protected]

Ziqi Wang Yifei Gao Hao Yan

Southeast University Southeast University Southeast University
Nanjing, Jiangsu, China Nanjing, Jiangsu, China Nanjing, Jiangsu, China
[email protected] [email protected] [email protected]

ABSTRACT Fault Preprocess

The advanced multi-core technology enables parallel computing
to speed up Automatic Test Pattern Generation (ATPG). The main Collapsed Fault list 30000

#SAT-based faults
challenge is to solve an increasing number of hard-to-solve faults 25000
FAN-Based Engine Fault Simulation
effectively. In this paper, we develop an efficient parallel computing 20000
system for the ATPG program, i.e., FPGNN-ATPG, which is con- Result 15000
sisted of two parts: graph-neural-networks-based (GNN-based) fault Redundant
Fault
FAN-based Fault

classification and fault-driven deterministic test pattern generator 10000

SAT-Based Engine
(DTPG). The end-to-end GNN-based classifier can predict fault types 5000
Redundant
with superior accuracy compared with classical machine learning Fault
Result
SAT-based Fault
0
methods. And the fault-driven DTPG can solve different types of D1 D2 D3 D4 D5
faults in parallel without runtime overhead. According to the exper-
imental results on an 8-core machine, our FPGNN-ATPG framework
obtains an average of 7.56X speedup while reducing 14.13% pattern Figure 1: left: industrial DTPG flow with FAN-based and SAT-
count ratio with full 100% fault coverage for 10 industrial instances. based engine; right: The number of SAT-faults in five bench-
mark with the scales ranging from 50k to 100k.
CCS CONCEPTS
• Hardware → Test-pattern generation and fault simulation; Testing (DTPG). It aims to detect as many faults as possible based on different
with distributed and parallel systems; Test-pattern generation and fault test pattern generation engines [1].
simulation. The details of deterministic pattern generation in current indus-
trial flow are shown in Figure 1. The first engine is based on a fan-
KEYWORDS
out-oriented test generation algorithm (FAN), i.e. FAN-based engine
ATPG, graph learning, parallel technology
[2], which can solve easy-to-detect faults with a short time interval.
ACM Reference Format: As a common method, it is usually embedded in commercial tools.
Yuyang Ye, Zonghui Wang, Zun Xue, Ziqi Wang, Yifei Gao, Hao Yan. 2023.
For example, NXP Semiconductors integrates a highly optimized
FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator
FAN-based engine in their ATPG framework [1].
. In Proceedings of the Great Lakes Symposium on VLSI 2023 (GLSVLSI ’23),
June 5–7, 2023, Knoxville, TN, USA. ACM, New York, NY, USA, 6 pages. https: However, the detectability of FAN-based engines reaches a limita-
//doi.org/10.1145/3583781.3590250 tion when dealing with hard-to-detect faults in a reasonable runtime.
For hard-to-detect faults, Boolean satisfiability algorithm (SAT) is
1 INTRODUCTION the most efficient solution. It converts the circuit into Conjunctive
The advanced manufactured integrated circuits (ICs) demand a Normal Form (CNF) and deals it with SAT solver [1] [3] [4]. As
more effective test pattern generator. After fault list preprocessing, shown in Figure 1, the SAT-based engine is usually connected in
including fault collapsing and redundant fault identification, the series after the FAN-based engine to figure out the hard-to-detect
most critical task in the ATPG is deterministic test pattern generation faults. Accordingly, those faults are defined as SAT-based faults and
the number of them increases with the circuit size obviously, as
Permission to make digital or hard copies of all or part of this work for personal or
classroom use is granted without fee provided that copies are not made or distributed shown in Figure 1. In conventional ATPGs, identification of SAT-
for profit or commercial advantage and that copies bear this notice and the full citation based faults is challenging, as they remain indeterminate until the
on the first page. Copyrights for components of this work owned by others than the FAN-based test pattern generation is carried out. These faults can
author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or
republish, to post on servers or to redistribute to lists, requires prior specific permission be detected only while reaching the restricted number of backtracks
and/or a fee. Request permissions from [email protected]. in the FAN-based engine. It causes substantial runtime increments.
GLSVLSI ’23, June 5–7, 2023, Knoxville, TN, USA For solving large-scale designs, parallel ATPGs using multi-core
© 2023 Copyright held by the owner/author(s). Publication rights licensed to ACM.
ACM ISBN 979-8-4007-0125-2/23/06. . . $15.00 processors have been posited as a prospective technology that can
https://doi.org/10.1145/3583781.3590250 ensure reasonable runtime. Most of present parallel ATPGs utilize

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GLSVLSI ’23, June 5–7, 2023, Knoxville, TN, USA Yuyang Ye et al.

fault parallelism [5–11]. The main idea is to divide the given fault
list into some subsets through fault partitioning and solve them Computational Circuit
Input output FAN-based Fault list
parallelly. However, the fault partitioning methods always cause
1 SA- -0
test inflation [10]. Traditional methods (static fault partitioning [5] G2
2 SA- -1
and dynamic fault/pattern broadcasting [6]) alleviate this problem G4 3 SA- -1
at the cost of inter-process communication overhead. Recently, the
most popular method is shared-memory ATPG [7] [8] [11], which
involves fault list sharing and fault status exchanging. G7
SAT-based Fault list
In recent years, graph methods have played an increasingly im-
1 SA- -0
portant role in EDA tools [12]. Graph algorithms, such as graph G5
G6 2 SA- -1
convolutional network (GCN) [13] and graph neural network (GNN) 3 SA- -1
[14], are efficient in learning the latent representations of nodes G4
(i.e., gates) through collecting structure information. And there is an
increasing number of manufacturing test research based on graph
Figure 2: The illustration of the relationship between faults
algorithms. In [15], better circuit testability is achieved by using a
and faulty gates.
GCN-based model.
In this paper, we propose an advanced fault parallel ATPG (i.e., elaborate the derivation on the example of an OR gate with the
FPGNN-ATPG) integrated with GNN-based fault classification model inputs 𝑋𝑖 and the Tseitin variable 𝑍 :
(i.e., GNN-F-Class) and fault-driven DTPG to solve different types
of faults effectively. The GNN-based model can achieve fault classi-
Ô Ô Ó
𝑍⇔ 𝑖 𝑋𝑖 ≡ (¬𝑍 ∨ 𝑖 𝑋𝑖 ) ∧ ( 𝑖 𝑍 ∨ ¬𝑋𝑖 ) . (1)
fication for distinguishing FAN-based faults and SAT-based faults
instantly. Then, the faults are solved in parallel with a fault-driven For various simple gates in our benchmark, generalized CNF
test pattern generation flow. Experimental results illustrate that the formulas are shown in Figure 4, and the literals in the CNF formula
proposed GNN model outperforms conventional machine learning are the valid input-output assignments to gates.
models on fault classification with high accuracy. Compared with
other industrial ATPG, FPGNN-ATPG achieves comparable test pat-
2.2 Problem Formulation
tern results with up to 7.56X runtime improvement and 14.13% pat- In this paper, we place emphasis on classifying FAN-based faults
tern count reduction under full 100% fault coverage on an 8-thread and SAT-based faults to improve the ATPG efficiency. This problem
machine. The key contributions are summarized as follows: can be categorized as binary classification with imbalanced data in
machine learning. Each gate in a design is reviewed by a classifier to
• We propose an end-to-end GNN classifier, called GNN-F-
decide on whether the faults on the gate pins belong to FAN-based
Class, to predict fault behavior in a netlist efficiently without
or SAT-based. GNN is an ideal method for this since the graph is a
running a FAN-based engine. The inductive GNN layers are
comprehensive representation of circuit netlists.
used to model the circuit logic information represented with
boolean formulas and circuit structure information. Definition 1 (FAN-based faulty gate). The gate where the faults on
• We design a fault-driven test pattern generation flow integrat- the pins of it are FAN-based faults.
ing a FAN-based engine, SAT-based engine, and FAN+SAT-
based engine to deal with corresponding classes of faults Definition 2 (SAT-based faulty gate). The gate where the faults on
created by GNN-F-Class, respectively. the pins of it are SAT-based faults.
• We achieve the overall FPGNN-ATPG framework using multi-
thread architecture on shared memory and validate the pro- Definition 3 (Circuit Network). An circuit network can be de-
posed framework using real design instances. fined as a graph G = {V, E} and node features: (1) a node set
V = {𝑣 (1) , 𝑣 (2) , . . . , 𝑣 (𝑛) }, where |V| = 𝑛, which represents the in-
2 PRELIMINARIES stances in the netlist; (2) an edge set E, where |E| = 𝑚, which repre-
2.1 Conjunctive Normal Form (CNF) sents the logical connections; (3) the node features 𝑿 ∈ R𝑛×𝑘 , where
The SAT solver is an effective method to deal with hard-to-detect 𝑖 th row vector x𝑖 ∈ R𝑘 (𝑖 = 1, . . . , 𝑘) is the attribute information for
faults. It is necessary to represent the combinational logic circuits the 𝑖 𝑡ℎ node.
using boolean formulas, which should be expressed as conjunctive
normal form (CNF) in an advanced SAT solver. The CNF formula 𝜑 In this paper, the network G is represented by an adjacency matrix
denotes the conjunction of clauses 𝜔, and each of which denotes a 𝑨, an attribute matrix 𝑿 , and a label matrix 𝒚.
disjunction of literals 𝑥𝑖 . Alternately, the literal is either a variable Problem 1 (Fault Classification). As shown in Figure 2, all the
𝑥𝑖 or its complement ¬𝑥𝑖 . Thus, the CNF formula can be regarded as nodes are labeled as either FAN-based faulty gate (the faults on the
a set of clauses, and the clause can be viewed as s set of literals, and pins are FAN-based faults) or SAT-based faulty gate (the faults on the
the CNF formula of a netlist is the conjunction of the CNF formulas pins are SAT-based faults). The objective is to train a classifier and
for all gates in the circuit. And the connectives between literals are adapt it to classify all the faulty gates accurately and fast, which can
¬, →, ↔, ∧, ∨. maximize fault coverage and minimize test pattern number. Based
Converting the boolean logic gate to CNF is straightforward fol- on the results, faults, including FAN-based faults and SAT-based
lowing the procedure proposed via Tseitin in [16]. Namely, we will faults, can be solved with corresponding engines.

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Adjacency Matrix
Graph Neural Network
aggregator
k=2

k=1

SoftMax

present


k=2 Node Embedding probability distributions of
each Faulty-gate type
k=1
absent

Initial Features: encoder Faulty Gate Classification

CNF Clause Vocabulary Matrix

Figure 3: The illustration of our GNN-F-Class training process: An adjacency matrix 𝐴 depicting a netlist and its initial features
ℎ 0𝑣 is given as part of the inputs. Graph learning is performed to calculate the node embeddings 𝒉𝑘𝑣 that express the netlist better
than the initial features. A softmax-based classification algorithm is then executed with the learned nodes to determine the
final faulty gate assignment 𝑃 that used in the overall ATPG framework.

3 GNN-BASED FAULT CLASSFICATION Cora Content Present

As shown in Figure 2, if we want to achieve the target of fault Absent
electronic
classification, we must finish faulty gate classification at first. Node embedding
biomedical
embedding and classification are the two key parts in our GNN- factorization
distribution
based method (i.e., GNN-F-Class) as shown in Figure 3. Given a social
incorporating
circuit netlist represented with adjacency matrix 𝑨 and feature ma-
Paper words vocabulary
trix 𝑯 . The graph neural network first generates its node embedding Gate Content
:Output
results H𝐾 for each gate based on node features and circuit struc- : Input ( )

tural information. These node embedding results are then given to a

classification model for predicting a label 𝑷 to represent faulty gate +
types. Our model deploys three types of modules to achieve such +

functions. These modules are aggregator, encoder that achieve node

embedding and classifier that predicts the type of faulty gates based CNF clauses vocabulary

on embedding results. Figure 4: The illustration of initial node features. There are
3.1 Initial Dataset Generation different encoding vectors for various logic gates with CNF
Original Features. For evaluating the performance of the gate clause vocabulary.
design, there are many features, such as output capacitance, area,
and slack, which can be extracted from related technology files and including aggregation and encoding, is required to obtain global
timing reports easily. However, there is no method to construct a structure information from neighborhoods of different hops.
vector for characterizing the logic of gates. Fortunately, the content Firstly, the feature information is obtained by an aggregator by
of CORA dataset inspires us, which is a famous test case that con- applying different aggregation functions on the node’s neighbors.
sists of 7 kinds of machine learning papers. It utilizes paper words Then an encoder handles the information transfer between various
vocabulary consisting of 1433 unique words to indicate all papers. layers using a weight matrix. At inference time, our trained aggre-
As shown in Figure 4, we have defined an initial feature vector used gators and encoders can generate embeddings for entirely unseen
to describe the logical information of standard gate types, including nodes by applying the learned parameters.
BUFF, NOT, AND, NAND, OR, NOR, XOR, and XNOR, in a similar Assuming that we have learned all the aggregator functions and
method called CNF clauses vocabulary. We have considered 8 types encoder weight matrices. Algorithm 1 describes the embedding gen-
of gates, and the maximum number of inputs is assigned to be 9, eration process in the case. The entire graph, G = {V, E} represented
which matches integrated circuit design rules. The total count of with node feature matrix 𝑿 : {𝒙 (𝑣) : ∀𝑣 ∈ V} and adjacency Ma-
the CNF clause in the constructed vocabulary is 72. For the initial trix 𝑨 are provided as input, and the node embedding results 𝑯 :
feature of gates, binary values indicate whether each clause in the {𝒉 (𝑣) : ∀𝑣 ∈ V} is defined as output after GNN learning. To im-
CNF vocabulary is present or absent (indicated by 1 and 0). prove the performance of node embedding, only the information in
Labels. A binary value is also assigned to each node. ‘0’ (negative) a limited range of the neighborhood region of a node is aggregated.
stands for FAN-based and ‘1’ (positive) stands for SAT-based. Labels This limitation is implemented through a search depth 𝐷. The node
are acquired through commercial ATPG workflow. representation is initialized with features of the node (line 1). Two
3.2 GNN-based Node Embedding Generation loops are involved in the node embedding process. First, each node
(𝑁 )
In this section, we explain how aggregators and encoders achieve 𝒗 aggregates the neighborhood features into a single vector 𝒉𝑑 𝑣
node embedding. Aggregators and encoders perform specific opera- based on the aggregation function (line 4). We use an element-wise
tions on the node. An iterative process of embedding computation, max-pooling operator as the aggregation function, which can be

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Algorithm 1 GNN-based Node Embedding Methodology GNN-F-class

Layer 1 Layer 2 FC Layer FC Layer
Input: circuit netlist graph: G = {V, E}; adjacency matrix: 𝑨;
node features matrix: 𝑿 :{𝒙 (𝑣) : ∀𝑣 ∈ V}; Search depth: 𝐷;
𝑎𝑔𝑔
Weight matrices of GNN-layers: {𝑾𝑑 , ∀𝑑 ∈ {1, ..., 𝐷 }} and
𝑝𝑟𝑜 𝑗
{𝑾𝑑 , ∀𝑑 ∈ {1, ..., 𝐷 }}.
FAN-based DTPG SAT-based DTPG
(𝑣)
Output: node embedding: 𝑯 : {𝒉𝐷 : ∀𝑣 ∈ V}. FAN- SAT-
based FAN- SAT- based
Fault Fault
(𝑣)
ℎ 0 ← 𝒙 (𝑣) , ∀𝑣 ∈ V; Fault based Undetected Fault based Fault
Simulation Simulation
1: List Engine Engine List

2: for 𝑑 ← 1 to 𝐷 do
3: for 𝑣 ∈ V do FAN+SAT-based DTPG
(𝑁 ) FAN+SAT-based
4: Compute 𝒉𝑑 𝑣 based on Equation (2), Engine
 
(𝑣) 𝑝𝑟𝑜 𝑗 (𝑣) (𝑁 )
5: 𝒉𝑑 = 𝜎 𝑾𝑑 · concat[𝒉𝑑−1, 𝒉𝑑 𝑣 ] ; Fault Simulation

6: end for Figure 5: The illustration of FPGNN-ATPG. It can be divided

7: end for into two key parts: GNN-F-Class and fault-driven DTPG. Dif-
fernt colors of DTPG flow with various DTPG engines for
formulated explicitly as: solving related faults.
 
(𝑁 𝑣 ) 𝑎𝑔𝑔 (𝑢)
𝒉𝑑 = maxpool {𝑾𝑑 ℎ𝑑−1, ∀𝑢 ∈ 𝑁 (𝑣) } , (2) in the framework by targeting the minimum loss function. Finally, we
𝑎𝑔𝑔 can divide the faults in collapsed fault list into two types: FAN-based
where 𝑁 (𝑣) is the neighborhood nodes of node 𝒗, 𝑾𝑑 is weight faults and SAT-based faults according to the classification results of
for aggregators, which means how the node is influenced via the faulty gates. They can be solved with responding engines to speed
neighbors in 𝑑-th hop. up the overall ATPG work. The entire classification procedure is
Then, a non-linear transformation is applied to encode the ag- inductive for each node, which only relied on the knowledge of its
∈ R𝐾𝑑 ×𝐾𝑑−1
𝑝𝑟𝑜 𝑗
gregated representation using a weight matrix 𝑾𝑑 neighborhood. Thus, the learned parameters are valid for both seen
and an activation function ReLU (line 5). Where 𝐾0 is 72 which is and unseen graphs.
the initial count of feature dimensions and 𝐾𝑑 is the count of the
embedding dimensions after 𝑑-th loop. 4 FAULT PARALLEL ATPG FRAMEWORK
Obviously, search depth is a critical parameter that affects the Our parallel ATPG framework is based on master-slave architec-
performance of a GNN learning framework. The deeper search depth ture. As shown in Figure 5, there is only one master process that
means covering a larger number of neighbor gates such that more creates various multi-slave processes on shared memory. The master
information can be involved for the target node. However, the num- process divides the fault list into two classes with GNN-F-Class, then
ber of neighbors increases explosively with the growth of hop-count, creates slave processes to solve these faults. For the slave process, it
which may lead to overfitting. For getting the most suitable search is effective to deal with different types of faults with corresponding
depth for our work, we monitor and compare the accuracy of train- test pattern generating engines.
ing and testing under various configurations on the search depth. 4.1 Master Process
According to the results, we set the 𝐷=3 and 𝐾𝐷 =128. Once reaching As shown in Figure 5, there are four main tasks: fault classification
the maximum depth 𝐷, the fully-connected layers for classification based on GNN-F-Class, fault list creation, dynamic fault parallelism,
receives the result of final node embeddings 𝑯 . slave processes creation, and monitoring. The fault creation mod-
ule is totally different from the traditional ATPG, because we can
3.3 Multi-stage Faulty Gate Classification
create two kinds of faults based on the faulty gate classification re-
Our faulty gate classification takes the node embedding results of
sults. For example, if the gate belongs to FAN-based faulty gate, the
GNN model as input, and outputs the faulty gate types. For a typical
corresponding faults (faults on the gate pins) belong to FAN-based
design, there are many more FAN-based faults (negative nodes) than
faults in our definition. Dynamic fault parallelism is used to ensure
SAT-based faults (positive nodes) in common, which is not beneficial
the balance of distributed workloads among slave processes. This
to train machine learning models [1]. Thus, the preference towards
strategy can avoid congestion of hard-to-detect faults.
the majority class can lead to a loss in efficacy and not meet our
requirements when using a single-layer classification model. 4.2 Fault-driven DTPG Slave Processes
For solving this imbalance issue, a multi-stage GNN model is used In Figure 5 (blue part and green part), we apply the fault-driven
instead. The GNN model of each stage is trained to only identify DTPG slave processes in our framework. The FAN-based slave pro-
negative cases with high confidence, and the remaining nodes are cesses pick faults from the FAN-based fault list and solve them within
dealt by latter stages. A large penalty is imposed when a faulty a short time using FAN-based engines. Then, the SAT-based slave
classification of positive nodes happen to guarantee such feature. processes work on the SAT-based fault list and utilize the SAT-based
In this way, the number of negative nodes is reduced substantially engine to generate test patterns. Once a test pattern is generated,
until generating a relatively balanced dataset of positive nodes and the fault simulation is carried out and may identify additional faults.
negative nodes after a few stages. As shown in Figure 3, our Softmax- Furthermore, the slave process should update the fault status to in-
based classifier regards cross-entropy loss as loss function and apply terrupt other slave processes when they try to solve detected faults
a gradient descent optimizer named Adam to adjust the parameters concurrently. Finally, the slave processes repeat the procedure above

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Table 1: Benchmark Circuit Information Table 2: Fault Classification Accuracy Comparison

circuit #PI #Gates #SA Faults Usage Method c544479 c76271 c87167 c98063 c103505 ave.
s35932 35 16065 39094 LR 0.723 0.684 0.739 0.697 0.701 0.709
s38584 38 19253 36303 RF 0.778 0.763 0.792 0.712 0.736 0.756
s38417 28 22179 31180 SVM 0.791 0.802 0.813 0.806 0.801 0.803
b14 277 21680 23716
b15 485 20186 23496 MLP 0.821 0.816 0.828 0.814 0.807 0.817
b17 1449 61044 75498 training GCN[13] 0.842 0.837 0.842 0.825 0.814 0.832
b20 522 31258 34528 GNN 0.994 0.989 0.992 0.991 0.987 0.991
b22 735 39385 48812
ethernet 10640 72609 190924
des3 9041 86309 218524 5.2 FPGNN-ATPG Fault Coverage
vga 17160 115011 300406 Figure 6(a) shows the fault coverage results of TG-Pro, parallel
des 9035 135555 270762 ATPG in [7] and our work on an 8-core machine. The fault coverage
c10863 656 10176 25184 of [7] is lower because it cannot solve some difficult-to-detect SAT-
c11175 1320 9713 20724 based faults. For the largest case (c103505), the fault coverage is
c12603 645 11768 27870 is just 86.23% and much lower than the requirement of practical
c25589 1290 24109 55740
c51561 2580 48791 111480 testing application. For all the cases we used, TG-Pro and our FPGNN-ATPG
c54479 3280 51120 125920 can reach 100% fault coverage without considering the untestable
c76271 4592 71568 176288 faults. When considered, the fault coverage is still larger than 98%.
c87167 5248 81792 201472 The reason for it is that the ability of SAT engine to generate a pattern
c98063 5904 92016 226656 for difficult-to-detect faults is much stronger than the FAN-based
c103505 5160 98155 222960
engine. In addition, it can prove that some faults are untestable.
The results of the fault coverage analysis using varying thread
until accomplishing all the task faults. At last, there may be a tiny counts are illustrated in Figure 6(d). It can be observed that the fault
number of faults assigned to be undetected, which takes around 0.6% coverage of [7] declines as the number of threads increases, owing
of all the faults. To deal with these faults, we utilize FAN+SAT-based to the concurrent interruption technique. In contrast, our approach
engine shown in Figure 5 (red part) to ensure fault coverage. maintains a high level of fault coverage across diverse conditions.
5.3 FPGNN-ATPG Speedup
5 EXPERIMENTAL RESULTS
Figure 6(b) compares the runtime speedup between our work
In this section, the achievements of our GNN-F-Class and FPGNN- and [7] . Both works use 8 threads, and the runtime results are nor-
ATPG are demonstrated, which are implemented in C++, Python, malized with the baseline work TG-Pro (classical serial framework)
PyTorch and Pthreads. The benchmark circuit set includes ISCAS’89 proposed in [3]. An average speedup of 7.56X can be observed on
and IWLS’05 circuits for training and 10 commercial and complex un- our work while the performance of work in [7] averages at 5.37x and
seen designs for testing. Their specifications, including the number is degrading with the increasing circuit size. In traditional ATPGs,
of inputs, gates, and stuck-at-faults, are shown in Table 1. The GNN the SAT-based faults are figured out by performing FAN-based en-
is trained on a Linux machine with 64 cores and 4 NVIDIA Tesla gines iteratively until reaching a limited number of backtracks. Our
V100 GPUs. The total memory used in training is 64GB. The baseline work can save the time through selecting out SAT-based faults and
ATPG is TG-Pro proposed in [3] which is based on FAN+SAT-based FAN-based faults in advance.
ATPG engine, and a fault-parallel ATPG based on FAN engine pro- Figure 6(e) shows the speedup of multi-thread FPGNN-ATPG over
posed in [7] is regarded as a comparison. TG-Pro with respect to different thread numbers. The near-linear
increment confirms that our framework can fully utilize the benefit
5.1 GNN-F-Class Classification Accuracy of multi-thread. This can be attributed to the use of concurrent inter-
ruption exclusively in the slave fault simulation processes, thereby
We compare the faulty gate classification performance of GNN-F- minimizing the communication overhead.
Class with the state-of-the-art classical machine learning methods,
including logistic regression (LR), random forest (RF), support vector 5.4 FPGNN-ATPG Pattern Counts Reduction
machine (SVM), Multi-layer perceptron (MLP), and GCN [13]. Every Figure 6(c) demonstrates the pattern count reduction results of
method was trained and tested using the same benchmarks listed different parallel ATPGs. For most cases, our parallel ATPG algo-
in Table 1. The experimental results in Table 2 show that the pro- rithm requires a negligible number averaging at 0.42% of additional
posed framework, reaching 99.1% in average accuracy, significantly test patterns but identifies a higher number of faults. Among the
outperforms other methods in different designs. Compared with benchmark sets evaluated in [7], c76271 and c87167 exhibit the high-
other machine learning methods, the collected structure information est fault coverages of 94.79% and 94.87%, respectively. Our approach
and cell features provide accuracy improvement. For GCN [13], the outperforms [7] in terms of pattern counts reduction and provides su-
specific aggregating functions based on circuit domain knowledge perior fault coverage. This outcome corroborates that the additional
used in our work make the GNN models more effective in our work. test patterns generated through our approach effectively enhance
In addition, our work can be valid for unseen circuits. fault coverage and are more efficient than those of [7].

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(a) (b) (c)

2-threads 4-threads 8-threads

Bench Fault Coverage Fault Coverage Fault Coverage
[6] ours [6] ours [6] ours
c10863 95.67% 99.49% 95.01% 99.49% 94.27% 99.49%
c11175 94.97% 100% 94.21% 100% 93.54% 100%
c12603 93.98% 98.63% 93.21% 98.63% 92.24% 98.63%
c25589 93.22% 98.61% 92.54% 98.61% 91.26% 98.61%
c51561 95.13% 98.11% 94.06% 98.11% 93.34% 98.11%
c54479 94.98% 99.49% 94.01% 99.49% 92.02% 99.49%
c76271 95.76% 99.27% 95.21% 99.27% 94.79% 99.27%
c87167 96.01% 99.34% 95.66% 99.34% 94.87% 99.34%
c98063 94.21% 99.49% 93.37% 99.49% 93.19% 99.49%
c103505 88.97% 98.92% 87.65% 98.92% 86.23% 98.92%

(d) (e) (f)

Figure 6: The fault coverage, speedup, and pattern reduction results generated through TG-Pro proposed in [3], a fault-parallel
ATPG proposed in [7] and our work (Figures 6(a) to 6(c)); The fault coverage, speedup, and pattern reduction results generated
through our work using 2,4 and 8 threads (Figures 6(d) to 6(f)).

Figure 6(f) shows the FPGNN-ATPG test set inflation (compared to [4] J. Silva and K. Sakallah, “Robust search algorithms for test pattern generation,”
TG-Pro) with respect to different thread counts. The average pattern in Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing,
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reduction by our method is 10.75%, 12.62%, and 14.45% in 2, 4, and [5] S. Patil and P. Banerjee, “Fault partitioning issues in an integrated parallel test
8 cores of parallel ATPG, respectively. The result suggests that the generation/fault simulation environment,” in Proceedings. ’Meeting the Tests of
Time’., International Test Conference, 1989, pp. 718–726.
communication on shared memory is capable of suppressing the [6] R. Butler, B. Keller, S. Paliwal, R. Schoonover, and J. Swenton, “Design and im-
effect from occurring during fault simulation. plementation of a parallel automatic test pattern generation algorithm with low
test vector count,” in Proceedings International Test Conference 2000 (IEEE Cat.
6 CONCLUSION No.00CH37159), 2000, pp. 530–537.
[7] J. C. Y. Ku, R. H.-M. Huang, L. Y.-Z. Lin, and C. H.-P. Wen, “Suppressing test
In this work, we propose an FPGNN-ATPG framework with GNN- inflation in shared-memory parallel automatic test pattern generation,” in 2014
based fault classification model and fault-driven DTPG. The fault 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, pp.
664–669.
classification module (GNN-F-Class) is applied to identification of [8] S. Hadjitheophanous, S. N. Neophytou, and M. K. Michael, “Utilizing shared mem-
FAN-based faults and SAT-based faults, which shows superior perfor- ory multi-cores to speed-up the atpg process,” in 2016 21th IEEE European Test
Symposium (ETS), 2016, pp. 1–6.
mance to classical learning methods. Then we leverage fault-driven [9] P. Krauss and M. Henftling, “Efficient fault ordering for automatic test pattern
DTPG flow in our parallel work. Experimental results demonstrate generation for sequential circuits,” in Proceedings of IEEE 3rd Asian Test Symposium
high speed-up rates of our work (7.56X on average) that keep in- (ATS), 1994, pp. 113–118.
[10] X. Cai, P. Wohl, J. Waicukauski, and P. Notiyath, “Highly efficient parallel atpg
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This work is supported by the National Natural Science Founda- shallow to deep learning,” in Proc. ISPD, 2020.
tion of China (No. 62274034 and 61904030). [13] T. N. Kipf and M. Welling, “Semi-supervised classification with graph convolutional
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