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Heaven’s Light is Our Guide

Department of Computer Science & Engineering

Rajshahi University of Engineering & Technology, Bangladesh

Course Code: CSE 2103

Course Title: Digital Logic Design

Presented by,
Prof. Dr. Boshir Ahmed
Md. Zahirul Islam
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Canonical and Standard Forms

• We need to consider formal techniques for
the simplification of Boolean functions.
– Identical functions will have exactly the same
canonical form.
– Minterms and Maxterms
– Sum-of-Minterms and Product-of- Maxterms
– Product and Sum terms
– Sum-of-Products (SOP) and Product-of-Sums
(POS)
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Definitions
• Literal: A variable or its complement
• Product term: literals connected by •
• Sum term: literals connected by +
• Minterm: a product term in which all the
variables appear exactly once, either
complemented or uncomplemented
• Maxterm: a sum term in which all the variables
appear exactly once, either complemented or
uncomplemented
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Minterm
• Represents exactly one combination in the truth
table.
• Denoted by mj, where j is the decimal equivalent
of the minterm’s corresponding binary
combination (bj).
• A variable in mj is complemented if its value in bj
is 0, otherwise is uncomplemented.
• Example: Assume 3 variables (A,B,C), and j=3.
Then, bj = 011 and its corresponding minterm is
denoted by mj = A’BC
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Maxterm
• Represents exactly one combination in the truth
table.
• Denoted by Mj, where j is the decimal equivalent
of the maxterm’s corresponding binary
combination (bj).
• A variable in Mj is complemented if its value in bj
is 1, otherwise is uncomplemented.
• Example: Assume 3 variables (A,B,C), and j=3.
Then, bj = 011 and its corresponding maxterm is
denoted by Mj = A+B’+C’
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Truth Table notation for Minterms

and Maxterms
• Minterms and x y z Minterm Maxterm
Maxterms are 0 0 0 x’y’z’ = m0 x+y+z = M0
easy to denote
0 0 1 x’y’z = m1 x+y+z’ = M1
using a truth
table. 0 1 0 x’yz’ = m2 x+y’+z = M2

• Example: 0 1 1 x’yz = m3 x+y’+z’= M3

Assume 3 1 0 0 xy’z’ = m4 x’+y+z = M4
variables x,y,z 1 0 1 xy’z = m5 x’+y+z’ = M5
(order is fixed) 1 1 0 xyz’ = m6 x’+y’+z = M6
1 1 1 xyz = m7 x’+y’+z’ = M7
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Canonical Forms (Unique)

• Any Boolean function F( ) can be
expressed as a unique sum of minterms
and a unique product of maxterms (under
a fixed variable ordering).
• In other words, every function F() has two
canonical forms:
– Canonical Sum-Of-Products (sum of
minterms)
– Canonical Product-Of-Sums (product of
maxterms)
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Canonical Forms (cont.)

• Canonical Sum-Of-Products:
The minterms included are those mj such that
F( ) = 1 in row j of the truth table for F( ).
• Canonical Product-Of-Sums:
The maxterms included are those Mj such
that F( ) = 0 in row j of the truth table for F( ).
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Example
• Truth table for f1(a,b,c) at right
a b c f1
• The canonical sum-of-products form
for f1 is 0 0 0 0
f1(a,b,c) = m1 + m2 + m4 + m6 0 0 1 1
= a’b’c + a’bc’ + ab’c’ + abc’
• The canonical product-of-sums form 0 1 0 1
for f1 is 0 1 1 0
f1(a,b,c) = M0 • M3 • M5 • M7
1 0 0 1
= (a+b+c)•(a+b’+c’)•
(a’+b+c’)•(a’+b’+c’). 1 0 1 0
• Observe that: mj = Mj’ 1 1 0 1
1 1 1 0
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Shorthand: ∑ and ∏
• f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that
this is a sum-of-products form, and m(1,2,4,6)
indicates that the minterms to be included are
m1, m2, m4, and m6.
• f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that
this is a product-of-sums form, and M(0,3,5,7)
indicates that the maxterms to be included are
M0, M3, M5, and M7.
• Since mj = Mj’ for any j,
∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)
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Conversion Between Canonical Forms

• Replace ∑ with ∏ (or vice versa) and replace those j’s

that appeared in the original form with those that do not.
• Example:
f1(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m 2 + m 4 + m 6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
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Standard Forms (NOT Unique)

• Standard forms are “like” canonical forms,
except that not all variables need appear
in the individual product (SOP) or sum
(POS) terms.
• Example:
f1(a,b,c) = a’b’c + bc’ + ac’
is a standard sum-of-products form
• f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
is a standard product-of-sums form.
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Conversion of SOP from standard

to canonical form
• Expand non-canonical terms by inserting
equivalent of 1 in each missing variable x:
(x + x’) = 1
• Remove duplicate minterms
• f1(a,b,c) = a’b’c + bc’ + ac’
= a’b’c + (a+a’)bc’ + a(b+b’)c’
= a’b’c + abc’ + a’bc’ + abc’ + ab’c’
= a’b’c + abc’ + a’bc + ab’c’
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Conversion of POS from standard

to canonical form
• Expand noncanonical terms by adding 0 in terms
of missing variables (e.g., xx’ = 0) and using the
distributive law
• Remove duplicate maxterms
• f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
= (a+b+c)•(aa’+b’+c’)•(a’+bb’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•
(a’+b+c’)•(a’+b’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)
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Combinational Logic Circuit

from Logic Function
• Consider function F = A’ + B•C’ + A’•B’
• A combinational logic circuit can be constructed to implement F, by
appropriately connecting input signals and logic gates:
– Circuit input signals 🡪 from function variables (A, B, C)
– Circuit output signal 🡪 function output (F)
– Logic gates 🡪 from logic operations

A F

B
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Combinational Logic Circuit

from Logic Function (cont.)
• In order to design a cost-effective and A B C F G
efficient circuit, we must minimize the
0 0 0 1 1
circuit’s size (area) and propagation
delay (time required for an input signal 0 0 1 1 1
change to be observed at the output 0 1 0 1 1
line) 0 1 1 1 1
• Observe the truth table of F=A’ + B•C’ 1 0 0 0 0
+ A’•B’ and G=A’ + B•C’ 1 0 1 0 0
• Truth tables for F and G are identical 1 1 0 1 1
🡪 same function
1 1 1 0 0
• Use G to implement the logic circuit
(less components)
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Combinational Logic Circuit

from Logic Function (cont.)
C

A F

C
B
A G
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Circuit Simplification Methods

• Boolean algebra: greatly depends on
inspiration and experience.
• Karnaugh map: systematic, step-by-step
approach.
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Algebraic Simplification
• Use the Boolean algebra theorems
introduced in Lecture 4 to help simplify the
expression for a logic circuit.
• Based on experience, often becomes a
trial-and-error process.
• No easy way to tell whether a simplified
expression is in its simplest form.
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Two Essential Steps

• The original expression is put into the
sum-of-products form by repeated
application of DeMorgan’s theorem and
multiplication of terms.
• The product terms are checked for
common factors, and factoring is
performed whenever possible.
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Examples 1- 4
Original Simplified

ABC+AB’(A’C’)’ A(B’+C)

ABC+ABC’+AB’C A(B+C)

A’C(A’BD)’+A’BC’D’+AB’C B’C+A’D’(B+C)

(A’+B)(A+B+D)D’ BD’
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Examples 5 - 6

• (A’+B)(A+B’): equivalent form A’B’+AB

• AB’C+A’BD+C’D’: cannot be simplified further.
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Boolean expressions-NOT unique

• Unlike truth tables, expressions x y z F G

representing a Boolean function are 0 0 0 1 1
NOT unique.
0 0 1 0 0
• Example:
– F(x,y,z) = x’•y’•z’ + x’•y•z’ + x•y•z’ 0 1 0 1 1
– G(x,y,z) = x’•y’•z’ + y•z’ 0 1 1 0 0
• The corresponding truth tables for F()
and G() are to the right. They are
1 0 0 0 0
identical. 1 0 1 0 0
• Thus, F() = G() 1 1 0 1 1
1 1 1 0 0
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Algebraic Manipulation
Example 7
• Boolean algebra is a useful tool for
simplifying digital circuits.
• Why do it? Simpler can mean cheaper,
smaller, faster.
• Example: Simplify F = x’yz + x’yz’ + xz.
F = x’yz + x’yz’ + xz
= x’y(z+z’) + xz
= x’y•1 + xz
= x’y + xz
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Algebraic Manipulation (cont.)

Example 8
• Example: Prove
x’y’z’ + x’yz’ + xyz’ = x’z’ + yz’
• Proof:
x’y’z’+ x’yz’+ xyz’
= x’y’z’ + x’yz’ + x’yz’ + xyz’
= x’z’(y’+y) + yz’(x’+x)
= x’z’•1 + yz’•1
= x’z’ + yz’
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Complement of a Function
• The complement of a function is derived
by interchanging (• and +), and (1 and 0),
and complementing each variable.
• Otherwise, interchange 1s to 0s in the
truth table column showing F.
• The complement of a function IS NOT
THE SAME as the dual of a function.
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Complementation
Example 9
• Find G(x,y,z), the complement of
F(x,y,z) = xy’z’ + x’yz
• G = F’ = (xy’z’ + x’yz)’
= (xy’z’)’ • (x’yz)’ DeMorgan
= (x’+y+z) • (x+y’+z’) DeMorgan again
• Note: The complement of a function can also be
derived by finding the function’s dual, and then
complementing all of the literals
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Simplifying Logic Circuits (Practice)

Watermark

Example 10
• The circuits shown provide the same output
– Circuit (b) is clearly less complex.

Logic circuits can be simplified using

Boolean algebra and Karnaugh mapping.
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Algebraic Simplification
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Example 11
Simplify the logic circuit shown.

The first step is to determine the expression for the output: z = ABC + AB • (A C)

Once the expression

is determined, break
down large inverter
signs by DeMorgan’s
theorems & multiply
out all terms.
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Algebraic Simplification
Simplify the logic circuit shown.

Factoring—the first & third terms above have

AC in common, which can be factored out:

Since B + B = 1, then…

Factor out A, which results in…

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Algebraic Simplification
Simplifed logic circuit.

z = A(C + B)
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Karnaugh Maps
• Karnaugh maps (K-maps) are graphical
representations of Boolean functions.
• One map cell corresponds to a row in the
truth table.
• Also, one map cell corresponds to a minterm
or a maxterm in the Boolean expression
• Multiple-cell areas of the map correspond to
standard terms.
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Karnaugh Map Method

• A graphical device to simplify a logic
expression.
• Generally work on examples with up to 4
input variables.
• From truth table to logic expression to K
map.
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Complete Simplification Process

• Step 1: Construct the K map and places 1s in those
squares corresponding to the 1s in the truth table. Places
0s in the other squares.
• Step 2: Examine the map for adjacent 1s and loop those
1s which are not adjacent to any other 1s. (isolated 1s)
• Step 3: Look for those 1s which are adjacent to only one
other 1. Loop any pair containing such a 1.
• Step 4: Loop any octet even when it contains some 1s
that have already been looped.
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Complete Simplification Process

• Step 5: Loop any quad that contains one or more 1s that
have not already been looped, making sure to use the
minimum number of loops.
• Step 6: Loop any pairs necessary to include any 1s have
not already been looped, making sure to use the
minimum number of loops.
• Step 7: Form the ORed sum of all the terms generated
by each loop.
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Filling K Map from Output

Expression
• What to do when the desired output is presented as a
Boolean expression instead of a truth table?
• Step 1: Convert the expression into SOP form.
• Step 2: For each product term in the SOP expression,
place a 1 in each K-map square whose label contains
the same combination of input values. Place a 0 in
other squares.
• Example 9: y=C’(A’B’D’+D)+AB’C+D’
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Two-Variable Map
x2 x1
x1 0 1 x2 0 1
0 1 0 2
0 m0 m1
OR 0 m0 m2
2 3 1 3
1 m2 m3 1 m1 m3

NOTE: ordering of variables is IMPORTANT for

f(x1,x2), x1 is the row, x2 is the column.
Cell 0 represents x1’x2’; Cell 1 represents x1’x2;
etc. If a minterm is present in the function, then
a 1 is placed in the corresponding cell.
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Two-Variable Map (cont.)

• Any two adjacent cells in the map differ by
ONLY one variable, which appears
complemented in one cell and
uncomplemented in the other.
• Example:
m0 (=x1’x2’) is adjacent to m1 (=x1’x2) and
m2 (=x1x2’) but NOT m3 (=x1x2)
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2-Variable Map -- Example

• f(x1,x2) = x1’x2’+ x1’x2 + x1x2’
= m 0 + m1 + m2
= x 1’ + x 2’
• 1s placed in K-map for x2
specified minterms m0, m1, m2 x1 0 1
• Grouping (ORing) of 1s allows
0 1
simplification
• What (simpler) function is 0
represented by each dashed 1 1
rectangle? 2 3
– x1 ’ = m 0 + m 1
– x2 ’ = m 0 + m 2 1 1 0
• Note m0 covered twice
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Minimization as SOP using K-map

• Enter 1s in the K-map for each product term
in the function
• Group adjacent K-map cells containing 1s to
obtain a product with fewer variables. Group
size must be in power of 2 (2, 4, 8, …)
• Handle “boundary wrap” for K-maps of 3 or
more variables.
• Realize that answer may not be unique
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Three-Variable Map
yz
x 00 01 11 10
0 1 3 2
0 m0 m1 m3 m2
4 5 7 6
1 m4 m5 m7 m6

-Note: variable ordering is (x,y,z); yz specifies column,

x specifies row.
-Each cell is adjacent to three other cells (left or right
or top or bottom or edge wrap)
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Three-Variable Map (cont.)

minterm

The types of structures that

are either minterms or are
generated by repeated
application of the minimization
theorem on a three variable
map are shown at right.
Groups of 1, 2, 4, 8 are
possible.
group of 2 terms

group of 4 terms
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Simplification
• Enter minterms of the Boolean function into
the map, then group terms
• Example: f(a,b,c) = a’c + abc + bc’
• Result: f(a,b,c) = a’c+ b
bc
a
1 1 1
1 1
1 1 1
1 1
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More Examples
yz
X 00 01 11 10

• f1(x, y, z) = ∑ m(2,3,5,7) 0 1 1
1 1 1
■ f1(x, y, z) = x’y + xz

• f2(x, y, z) = ∑ m (0,1,2,3,6)
1 1 1 1
■f2(x, y, z) = x’+yz’
1
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Four-Variable Maps
YZ
00 01 11 10
WX
00 m0 m1 m3 m2

01 m4 m5 m7 m6

11 m12 m13 m15 m14

10 m8 m9 m11 m10

• Top cells are adjacent to bottom cells. Left-edge

cells are adjacent to right-edge cells.
• Note variable ordering (WXYZ).
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Four-variable Map Simplification

• One square represents a minterm of 4 literals.
• A rectangle of 2 adjacent squares represents a
product term of 3 literals.
• A rectangle of 4 squares represents a product
term of 2 literals.
• A rectangle of 8 squares represents a product
term of 1 literal.
• A rectangle of 16 squares produces a function
that is equal to logic 1.
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Example
• Simplify the following Boolean function
(A,B,C,D) = ∑m(0,1,2,4,5,7,8,9,10,12,13).
• First put the function g( ) into the map, and then
group as many 1s as possible.
ab cd
1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1

1 1 1 1 1 1

g(A,B,C,D) = c’+b’d’+a’bd
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Don't Care Conditions

• There may be a combination of input values which
– will never occur
– if they do occur, the output is of no concern.
• The function value for such combinations is called a
don't care.
• They are denoted with x or –. Each x may be
arbitrarily assigned the value 0 or 1 in an
implementation.
• Don’t cares can be used to further simplify a function
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Don’t-Care Conditions
• Some logic circuits can be designed so
that there are certain input conditions for
which there are no specified output levels.
• A circuit designer is free to make the
output for any don’t care condition either a
0 or a 1 in order to produce the simplest
output expression.
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cd
ab 00 01 11 10
Example 00 0 1 0 1
01 1 1 0 1
• Simplify the function f(a,b,c,d) 11 0 0 x x
10 1 1 x x
whose K-map is shown at the
right. 0 1 0 1
• f = a’c’d+ab’+cd’+a’bc’ 1 1 0 1
or 0 0 x x
1 1 x x
• f = a’c’d+ab’+cd’+a’bd’
0 1 0 1
1 1 0 1
0 0 x x
1 1 x x
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cd
Another Example ab
x 1 0 0
1 x 0 x
• Simplify the function 1 x x 1
g(a,b,c,d) whose K-map 0 x x 0

is shown at right. x 1 0 0
• g = a’c’+ ab 1 x 0 x
1 x x 1
or
0 x x 0
• g = a’c’+b’d
x 1 0 0
1 x 0 x
1 x x 1
0 x x 0
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Another Example
For each symbol of the Excess-3 code, we use 1’s to draw
the map for simplifying Boolean function.

52
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Circuit implementation
z = D’; y = CD + C’D’ = CD + (C + D)’
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
w = A + BC + BD = A + B(C + D)

53
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AND-OR (SOP) Emulation

Using NANDs

Two-level implementations

a) Original SOP
b) Implementation with NANDs
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AND-OR (SOP) Emulation

Using NANDs (cont.)

Verify:
(a) G = WXY + YZ
(b) G = ( (WXY)’ • (YZ)’ )’
= (WXY)’’ + (YZ)’’ = WXY + YZ
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SOP with NAND

(a) Original SOP

(b) Double inversion and grouping AND-NOT
(c) Replacement with NANDs NOT-OR
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Two-Level NAND Gate

Implementation - Example
F (X,Y,Z) = Σm(0,6)
1. Express F in SOP form:
F = X’Y’Z’ + XYZ’
2. Obtain the AND-OR implementation for F.
3. Add bubbles and inverters to transform
AND-OR to NAND-NAND gates.
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Example (cont.)

Two-level implementation with NANDs

F = X’Y’Z’ + XYZ’
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Multilevel NAND Circuits

Starting from a multilevel circuit:
1. Convert all AND gates to NAND gates with
AND-NOT graphic symbols.
2. Convert all OR gates to NAND gates with NOT-OR
graphic symbols.
3. Check all the bubbles in the diagram. For every
bubble that is not counteracted by another bubble
along the same line, insert a NOT gate or
complement the input literal from its original
appearance.
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Example
Use NAND gates
and NOT gates to
implement
Z=E’F(AB+C’+D’)+GH
AB
AB+C’+D’
E’F(AB+C’+D’)
E’F(AB+C’+D’)+GH

Boolean Algebra PJF - 60

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Yet Another Example!

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Two-Level NOR Gate

Implementation - Example
F(X,Y,Z) = Σm(0,6)
1. Express F’ in SOP form:
1. F’ = Σm(1,2,3,4,5,7)
= X’Y’Z + X’YZ’ + X’YZ + XY’Z’ + XY’Z + XYZ
2. F’ = XY’ + X’Y + Z
2. Take the complement of F’ to get F in the POS form: F
= (F’)' = (X'+Y)(X+Y')Z'
3. Obtain the OR-AND implementation for F.
4. Add bubbles and inverters to transform OR-AND
implementation to NOR-NOR implementation.
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Example (cont.)

Two-level implementation with NORs

F = (F’)' = (X'+Y)(X+Y')Z'
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Designing Combinational Logic Circuits

(Procedure)

• To solve any logic design problem:

1. Interpret the problem and set up its truth table.

2. Write the AND (product) term for each case where output = 1.
3. Combine the terms in SOP form.
4. Simplify the output expression if possible.
5. Implement the circuit for the final, simplified expression.
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Designing Combinational Logic Circuits

Example - 1

Circuit that
produces a 1
output only for
the A = 0, B = 1
condition.
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Designing Combinational Logic Circuits

An AND gate with appropriate inputs can be used to
produce a HIGH output for a specific set of input levels.
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Designing Combinational Logic Circuits

Example - 2
Each set of input conditions that is to produce a
1 output is implemented by a separate AND gate.

The AND outputs are ORed to produce the final output.

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Designing Combinational Logic Circuits

Example - 3
Truth table for a 3-input circuit.
AND terms for each
case where output is 1.

•Now, add this terms

•Simplify the
expression if possible
•Draw the circuit
Diagram
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Designing Combinational Logic Circuits

Example - 4
Design a logic circuit with three inputs, A, B, and C.
Output to be HIGH only when a majority inputs are HIGH.
AND terms for each
Truth table. case where output is 1.

SOP expression for the output:

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Designing Combinational Logic Circuits

Design a logic circuit with three inputs, A, B, and C.
Output to be HIGH only when a majority inputs are HIGH.
Simplified output expression:

Implementing the
circuit after factoring:

Since the expression is in SOP form, the circuit is a

group of AND gates, working into a single OR gate,
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Example - 5 : Exclusive NOR Circuits

Truth table and circuit

for detecting equality of
two-bit binary numbers.
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Designing Combinational Logic Circuits

Example – 6 (Home Work)
• Design a logic circuit that is to produce a
HIGH output when the voltage
(represented by a four-bit binary number
ABCD) is greater than 6V.
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Designing Combinational Logic Circuits

Example – 7
• Four chairs A, B, C, and D are placed in a row.
Each chair may be occupied (“1“) or empty (“0“).
A Boolean function F is (“1“) if and only if there
are two or more adjacent chairs that are empty.

a) Give the truth table defining the Boolean F.

b) Express F as a minterm expansion (standard
sum of products).
c) Express F as a maxterm expansion (standard
product of sums).
d) Simplify the minterm expansion of F.
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Analysis procedure
To obtain the output Boolean functions from a logic
diagram, proceed as follows:
1.Label all gate outputs that are a function of input variables with arbitrary
symbols. Determine the Boolean functions for each gate output.
2.Label the gates that are a function of input variables and previously labeled
gates with other arbitrary symbols. Find the Boolean functions for these
gates.
3.Repeat the process outlined in step 2 until the outputs of the circuit are
obtained.
4.By repeated substitution of previously defined functions, obtain the output
Boolean functions in terms of input variables.
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Example – 1
F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1;
F1 = T3 + T2
F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC

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Derive truth table from logic

diagram
• We can derive the truth table in Table 4-1 by using the
circuit of Fig.4-2.

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Design procedure
1. Table4-2 is a Code-Conversion example, first, we can
list the relation of the BCD and Excess-3 codes in the
truth table.

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Thank
You

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