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ASIC Design Flow-1

The document outlines the ASIC (Application-Specific Integrated Circuit) design flow, detailing its advantages over FPGAs, such as energy efficiency and suitability for bulk production. It describes the key steps in the ASIC design process, including specification, architectural design, functional verification, synthesis, design for testability, physical design, static timing analysis, GDSII generation, and fabrication/testing. Each step is crucial for ensuring that the ASIC meets its intended functionality and performance requirements.

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Rahul Jaiswal
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12 views6 pages

ASIC Design Flow-1

The document outlines the ASIC (Application-Specific Integrated Circuit) design flow, detailing its advantages over FPGAs, such as energy efficiency and suitability for bulk production. It describes the key steps in the ASIC design process, including specification, architectural design, functional verification, synthesis, design for testability, physical design, static timing analysis, GDSII generation, and fabrication/testing. Each step is crucial for ensuring that the ASIC meets its intended functionality and performance requirements.

Uploaded by

Rahul Jaiswal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Page |1

ASIC Design Flow

- Logesh A
Page |2

Introduction:

ASIC stands for Application-Specific Integrated Circuit.


It’s a chip designed to do one specific task efficiently, like:

❖ Signal processing in a smartphone

❖ AI inference in a data center

❖ Engine control in a car

Unlike general-purpose chips (like CPUs), ASICs are custom-


designed for a particular application.

Why ASIC not FPGA?

1. ASICs can’t be reconfigured with different design. They contain


only one design in them for the whole life time. While FPGAs
can be reconfigured with different designs.
2. ASICs are suited for bulk production but FPGAs are not suited
for bulk production.
3. ASICs are energy efficient and consumes less power than FPGA.
4. Higher Frequencies can be achieved on then same node. While
in other hand FPGAs works on limited frequencies
5. ASICs are built only after validating the design for permanent
use of that design on silicon. While FPGAs are used to
prototype and validate a design.

- Logesh A
Page |3

ASIC FLOW:

- Logesh A
Page |4

1. Specification

What should the chip do?

• Define functionality, performance, area, and power


requirements.

• Set I/O count, power consumption limits, target technology


node (e.g., 3nm,5nm).

2. Architectural Design

Write the digital logic in a hardware language.

• Use Verilog or VHDL to describe what the chip does logically.

• This is where the design is created using registers, logic gates,


and FSMs.

• Example: ALUs, registers, multiplexers.

3. Functional Verification

Make sure the RTL works as intended.

• Use testbenches, simulators (like Model Sim, VCS), and write


test cases.

• Techniques: Simulation, Formal Verification, Code Coverage

• Goal: Catch bugs before synthesis.

- Logesh A
Page |5

4. Synthesis (named as circuit design)


Convert RTL to a gate-level netlist.
• RTL + Constraints → Netlist of logic gates

• Tools: Synopsis → Design Compiler, Cadence → Genus

• Input: RTL, SDC, LIB, LEF, UPF

• Output: Netlist that can be physically implemented

5. DFT (Design for Testability)


Insert test logic to allow chip testing after manufacturing.
• Add scan chains, BIST (Built-in Self-Test)

• Ensure manufacturing defects can be detected

6. Physical Design
Convert the netlist into a physical layout.
Steps inside Physical Design:

• Floor planning: Place blocks, macros, IOs

• Power Planning: Create power rings and straps

• Placement: Place standard cells

• CTS (Clock Tree Synthesis): Balance clock arrival times

• Routing: Connect all cells and blocks

• Physical Verification: Check DRC, LVS

• Tools: Cadence → Innovus, Synopsis → ICC2


- Logesh A
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7. Static Timing Analysis (STA) (Timing closure)

Make sure timing constraints are met.

• Analyse timing without simulation

• Identify setup and hold violations

• Tools: Synopsis → PrimeTime, Cadence → Tempus

8. GDSII Generation

Create the final layout file to send to the foundry.

• GDSII is the file that represents all layers of the chip.

• Handoff to fabrication plant (like TSMC, Intel Foundry, etc.)

9. Fabrication and Testing

Chip is manufactured, packaged, and tested.

• Wafer is manufactured

• Packaged into a usable form (like BGA or QFN)

• Tested for functionality, power, and speed

- Logesh A

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