ASIC Design Flow
Table of Content:
ASIC Design Flow
ASIC IN Everyday life
Types of ASIC
How does the ASIC cycle Work
ASIC
An Application-Specific Integrated Circuit (ASIC) is a chip custom-
designed for one specific function or application.
Unlike general-purpose chips like CPUs or GPUs, ASICs are built to do a
single task efficiently
The primary purpose of ASICs is efficiency. By designing a chip specifically
for one task, engineers can make it faster, smaller, and use less power
compared to a general-purpose chip.
ASICs in Everyday Life
Smartphones:
The Apple A-series chips are custom ASICs designed for iPhones.
They handle everything from app performance to image
processing.
The Google Tensor chip in Pixel phones improves AI-based
photography.
Healthcare:
ASICs in medical devices like pacemakers or MRI machines
ensure precise and reliable operation.
Cryptocurrency Mining:
ASICs like the Antminer S19 are built exclusively for solving
cryptographic puzzles required in Bitcoin mining.
Why it is essential?
This process is essential for achieving:
1. Accurate Specifications and Requirements: Ensuring a clear understanding of
the ASIC's purpose, design specifications, and application-specific needs.
2. Low Power Design and Performance: Emphasizing energy efficiency and optimal
performance in the design.
3. Timely Market Delivery: Meeting strict deadlines to achieve a competitive edge
with faster time-to-market.
Types of ASIC
How does ASIC Design Cycle works ?
STEP 1: Chip Specification
Feature Definition: Defines features, microarchitecture, and
hardware/software interfaces.
Specification Development: Determines time, area, power, and
speed requirements (clock frequency).
Blueprint for entire ASIC design flow
STEP 2: Architectural Design
Purpose: Translate the specification into structured architechtures in the
form of block diagrams.
This includes details about interconnects.
Cost of chip will be predicted here.
STEP 3: RTL design
Purpose: Coding and functional verification
Process:
Interconnection of combinational circuits and registers using
behavioural modelling in HDL.
Functional verification is done
Tool used: Xilinx
STEP 4: Logic Synthesis
Purpose: RTL behavioural model is converted to gate level netlist.
Inputs for this stage are RTL code, libraries, sdc constraints.
Stages of Logic Synthesis:
Translation: High level RTL code ---> Logic gate.
Technology mapping: Maps with required technology
like 28nm,7nm,etc..
Optimisation for power, area and timing.
Tool used: Genus by Cadence / Design compiler by Synopsys.
Design for testablity is done after this stage
STEP 5: Logic Verification and Testing
Purpose:
Test for design correctness and performance.
Identifying and fixing any timking violations.
Output of this step is the gate-level netlist and sdc constraints file which
serve as input for physical design.
Untill no error is found the iterations are made continuously
STEP 6: Placement and Routing
Purpose: Gate level netlist is converted to GDSII format with best Quality of
result.
GDSII format is the transistor level layout.
Tool used: Innovus by Cadence
Steps involved:
Design import Floor planning Power planning
Optimisation Clock tree synthesis
STEP 7: Physical Verification and Signoff
Process:
Design rule check
Perform layout versus schematic checks
Timing analysis, Power analysis are carried out.
GDSII file is sent to foundry for manufacturing and this process is
called tape-out.
Thank You
