VLSI STA Interview Preparation Guide
**VLSI STA Interview Preparation Guide with Q&A and Mock Interview**
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### Basic STA Interview Questions
1. What is Static Timing Analysis (STA)?
> STA is a method of verifying the timing of a digital design by calculating the arrival times of signals at each
gate without simulating the design. It ensures that all timing constraints are met.
2. What are setup and hold times?
> - Setup time: Minimum time before the clock edge by which data must be stable.
> - Hold time: Minimum time after the clock edge during which data must remain stable.
3. What is slack in STA?
> Slack = Required Arrival Time (RAT) - Actual Arrival Time (AAT)
> - Positive slack: No timing violation
> - Negative slack: Timing violation
4. What is the difference between max and min paths?
> - Max path: Setup timing check
> - Min path: Hold timing check
5. What is clock skew?
VLSI STA Interview Preparation Guide
> Clock skew is the difference in clock arrival time at different flip-flops. It impacts setup and hold margins.
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### Intermediate STA Questions
6. Common reasons for setup violations?
> - Long combinational paths
> - High fanout
> - Slow cells
> - Clock skew
7. How to fix setup/hold violations?
> - Setup: Upsize cells, reduce path delay, balance skew
> - Hold: Add delay buffers, adjust skew
8. What is MCMM analysis?
> Multi-Corner Multi-Mode (MCMM) checks timing across process-voltage-temperature (PVT) corners and
functional/test modes.
9. How does OCV affect STA?
> OCV accounts for within-die variations. Derates are applied to setup/hold paths.
10. What are timing exceptions?
> - False path: Never active
VLSI STA Interview Preparation Guide
> - Multicycle path: Allowed more cycles than 1
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### Advanced STA Questions
11. How to close timing for multi-voltage designs?
> - Use level shifters
> - Verify isolation/retention cells
> - Apply voltage-aware constraints
12. What is DMSA?
> Distributed Multi-Scenario Analysis runs STA across many scenarios in parallel, improving runtime.
13. How to correlate timing between hierarchical and flat STA?
> - Use consistent constraints/libraries
> - Check parasitic mismatches
> - Compare report_timing data
14. What if setup violation remains after upsizing?
> - Check fanout, RC delay
> - Analyze placement
> - Evaluate path reconvergence and congestion
15. Impact of clock gating on STA?
VLSI STA Interview Preparation Guide
> Requires verifying gating checks to ensure clock enable logic is correct.
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### Tool-Specific Questions (Primetime/Tempus)
16. What is the role of .sdc file?
> Defines clocks, IO delays, constraints, exceptions.
17. How to read STA reports?
> - Look at worst paths (negative slack)
> - Analyze cell and net delays
> - Focus on startpoint to endpoint timing
18. Useful flags in `report_timing`?
report_timing -delay_type max -max_paths 5 -sort_by group
19. What is `check_timing` used for?
> Identifies unclocked paths, missing constraints, or loops.
20. How are ECOs applied?
> - Generate ECO with DMSA/pteco
> - Verify changes via STA
> - Back-annotate and recheck timing
VLSI STA Interview Preparation Guide
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### Mock Interview
Interviewer: What is setup and hold time and how does it relate to clock skew?
> You: Setup time is the minimum time before the active clock edge that data must be stable. Hold time is the
time after the clock edge. Clock skew can either help or hurt setup/hold margins.
Interviewer: You see a setup violation on a path. What steps do you take?
> You: First, analyze timing report and identify the path. Then, consider upsizing cells, logic restructuring,
buffer insertion, or floorplan changes. Also, examine clock skew and derates.
Interviewer: What is the impact of OCV and how do you model it?
> You: OCV introduces derating factors to account for on-chip process variations. It is modeled via derate
tables for setup and hold paths in tools like Primetime or Tempus.
Interviewer: How would you handle a false path in STA?
> You: Declare the path as false using `set_false_path` in SDC to prevent it from affecting timing closure.
Interviewer: You are asked to analyze a multi-voltage block. What do you do?
> You: Identify all power domains, insert proper level shifters, apply voltage-aware derates, check for domain
crossing violations, and ensure isolation cells are present.
VLSI STA Interview Preparation Guide
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Problem-Based STA Interview Q&A
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1. Q: A path shows negative setup slack of -120ps. What steps will you take to fix it?
A:
- Analyze report to identify delay contributors (cell/net).
- Increase drive strength of critical cells.
- Insert repeaters (buffers) to reduce net delay.
- Adjust placement or floorplan to reduce wirelength.
- Check clock skew and optimize clock tree if needed.
- Consider useful skew or retiming.
2. Q: You fixed setup violations, but now observe hold violations on the same path. Why?
A:
- Setup fixes (e.g., stronger cells) reduce path delay, leading to hold issues.
- Fix by inserting delay buffers or hold fixing cells.
3. Q: Block timing met at block level fails in SoC. Possible reasons?
A:
- Different constraints or corners used.
- Missing mode/environment setup.
- Improper boundary constraints.
- Missing RC or macro correlation.
VLSI STA Interview Preparation Guide
4. Q: High slack violation on a level shifter path?
A:
- Level shifter might be incorrectly placed or sized.
- Voltage derating not applied properly.
- Investigate net length or skew at voltage boundary.
5. Q: Multicycle path with set_multicycle_path 2. What are setup and hold checks?
A:
- Setup is checked 2 cycles later.
- Hold remains same unless explicitly changed.
- Use:
set_multicycle_path 2 -setup -from FF1 -to FF2
set_multicycle_path 1 -hold -from FF1 -to FF2
6. Q: FF-to-FF path has large delay despite fast cells?
A:
- Likely net delay issue: long wires or large load.
- Fix via buffering, repeater insertion, or routing optimization.
7. Q: Why report_timing misses a known path?
A:
- Path could be unconstrained or masked as false.
- Clock not propagated.
- Multicycle or false path exception applied.
VLSI STA Interview Preparation Guide
8. Q: How does OCV affect closure?
A:
- Adds pessimism with derates (e.g., 0.93/1.07).
- Worsens slack in corners like ss_0.72v_-40C.
- Mitigate with AOCV/POCV and better placement.
9. Q: Test mode (20MHz) shows hold violations. Is it an issue?
A:
- Yes, because low frequency widens hold window.
- Fix via delay buffers or relaxed derates if methodology permits.
10. Q: ECO caused hold failure. Why?
A:
- ECO changes drive strength or skew.
- Delay of short paths might be reduced.
- Fix by re-evaluating and inserting hold buffers.
