wa Se 1 SS ee ae wl 2a QUESTION BANK SOLUTION OF MICROPROCESSOR S.ESEMAV BRANCH: COMPS/AIML/DS/IOT |UMMER SESSION 2025 ‘Ans: Minimum Mode The working of min mode can be easily understor 1g diagrams: © All processors bus cycle is of at least 4 T- 1 Tz,T5,Ta) The address in the T1 state. It is available on the bus © In Tp,the bus is tristated for changing the Wireeti read cycle.) ‘© The data transfer takes place be Clock. ALE Add/statuz a Read timing diagram is slower, then the wait state is inserted between T, and Ts tate ALE = 1, ERIE indicate that valid address is latched on the address bus also M/IO jicates the memory is in progress. © Inte, ress is removed from the local bus and is sent to the address devices. Then bus is tristated. | * During T, DEN = 0, which enables transceiver’s and DT/R = 0, which indicates that the data s received. © During Ts, data is put on the data bus and the processor reads it. (ie toe‘= The output devices makes the READT line high. This means the autput deviens has pertormed the data transfer process When the processor makes the read signal to 1, then the output lpi roan le ssi YO XX si/ou YX) {DY om —S \ XX aisoM es of memory or /O word, 1, which indicates that the datas Aasmaan eR ND ead Operation‘These are explained in steps. ‘© So,S1,5> are set at the beginning of bus passive state So= 5: = S jemientation of allocation of global resources and pas: second processor in the system), because two proces: Circuit Explanation i) When MN/MX = , 8086 works in max mode. li) Clock is provided by 8284 clock generator. }8288 bus controller- Address form the address bus is latched into 8282 8-bit /atch. Three latches are required because address bus is 20 bit. The ALE (Address latch enable) is connected to STB(Strobe) of the latch. The ALE for latch is given by 8288 bus controller [poz aneisAs AUrrighes reserved. This material isthe exclusive proverty of MUSA. Unauthorized reproduction, dis‘Moxirn re required, ion of ss operated through 8286 rection iv) The data bus ane ecause data bus is 16-bit. 7 data is controlled by the DT 1. Both DEN and DT/ Rare Biv en INTR line of 8086. ved one T-state in advance as compared to ves slower devices more time to get ready to accept the data, ‘Mode, when MN/MX = 1 the only processor in the system, The Minimum Mode circuit of 8086 iv)Address ffm the address bus is latched into 8282 8-bit latch. Three such latches are needed, as address bus is 20-bit. The ALE of 8086 Is connected to STB of the latch. The ALE for this latch is given by 8086 itself. W) The data bus is driven through 8286 8-bit trans-receivers. Two such trans-receivers are needed, as the data bus is 16-bit. The trans-receivers are enabled through the DEN signal, white the direction of data is controlled by the DI/R signal. DEN Is connected to OE and OT/R 's connected 10 T. Bath DEN and DT/R are given by BORG itselfDEN | DI/R Action n x Transrecelver Is disabled 0 o Receive date 0 1 Transmit date vi) Control signals for all operations are generated by decoding M/"1O , “RD and “WR signals. M/ 10° Action T 0 | 1 | Memory Read rH 1 (0 [Memory Write oO 0 | 1 [Vo Read 0. 1 0 [v0 Write vii) M/-IO, “RD and “WR are decoded by a 3:8 decoder like IC 741 using the HOLD and HLDA signals vill) “INTA is given by 8086, in response to an interrupt on INTR line. _ im fe itis specified in 1CW4, nce order of giving ICW commands is fixed i.e. ICWs is given first and then IW: and vi) Any of the ICW commands can not be repeated, but the entire initialization process can be repeated if required initialization sequence of 8259:(2) (ews command + The contro! word is recognized as iCW, ‘+ Ithas the contro bits for Edge and fee! Interval and whether ICW4 is requited of 1+ Address lines Ay to Aare {2) IeWs command ews comma one 8258 present in the system je. when 1 Bit slave register. of interrupt mode i selected, a special fully nested made is selected tnuffered mode fs used (ie. M/Sis don't care} and when M/S = herwise isa slave 1, then #66 operations are performed, otherwise 8085 operations ace perating command words (OCW) 1) OCWis given during the operation of 8258 J. microprocessor starts using 8259 1) OCW commands are not compulsory for 8259 Aye sequence order of giving OCW commands not fixe. Iw) The OCW commands can be repeated (1) 0cw,: 11s used to set and reset the mask bits in IMA\interrupt mask cegister) My ~ Me describes 8to set and Intertupt mask 1 Mask sot O= Mask reset (2) 0cws: Its used for selecting the mode of eration of 8259, Here Ly to Laat ‘eve! on which action need to be per formed. Vesna See nto ean ‘Avtomatle rotaton{8} Explain the Integer and Floating point Pipeline of Pentam processor. [Ans: The integer pipeline of the Pentium processor consist of fve stages 1) Instruction Fetch IF: Fetches the instruction from memory iy lostruction Decode (ID): codes the instruction and determines the required operations Ti Execution (EX) Executes the operation specified by the instruction. In) Memory Access (MEM) If necessary, acesses memory for data, ¥) Write Back (WE): Writes the rosut back to the register Me Floating point Pipeline of Pentium processor: “Te floating-point pipeline ofthe Pentum processor is responsible for arithmetic operations. I consists of several stages th computation I) Instruction Decode: In this stage, the pr Instruction and prepares it for exccut ii) Operand Feteh: The operands, register file or memory. Ti) Execution: The actual floating focessor completes the current instruction and stats the ie Routine (SR) or Interrupt Handle. els the processor what ta da when the interrupt occurs. After the ISR to the main routine where it was interrupted. ecrupts present in the 8986 microprocessor are given by: Hardwere foe by sending 2 signa Unraugh a specified pin to the microprocessor. There are two hardware interrupts in the 8086 microprocessor. They ae: 1+ (Non: Mazkable Interrupt} Its a single pin nan-maskabie hardware interrupt that ‘04S microprocessor. After cannot be disabled. Its the highest pony interrupt in th its execution, this interrupt generates a TYPE 2 interrupt (Ps load rom wo (00008 Hand C5 is loaded from the word lecation QOOOA H © INTR (oterrupt Request) i provides a single interrupt request and is activated by the /O port. This interrupt can be masked ar deed. It sa evel-trggered interrupt ear fa a yo MESA ‘receive any interrupt type, s0 the value of IP and CS will hange on the interrupt type 2) Software interrupts ~ These are mstauction inserted within the programs to gensiate interrupts. There are 256 seftware interrupts jn the BORG microprocessor. The struction are ot the format INT type, where the Iype at PL 200004 0056 these are 2-byteinstuctions (Ps loaded trom type “04H, ad CS oases yNTR nterropt Request) W orovides 4 sinle Interupt request ands activated bythe 0 jot This tntertupt can be masked or delayed Its 2 ove -ragoed interupt. Wt can | ‘receive any imerupt type, so the value of I and C5 wil change onthe interupt type recened, 2) Sofware interrupts ~ These are instruction inserted within the program to nenerate Interupts. There ae 256 software Interrupts in the 2086 miroprocestr. The instruction are of the format type, where the type of rage from 00 to FF. The starting adress ranges from (0008 OOSFFH these are 2-byte instructions IPs loaded rom type *04 K, and CS is leaded from the folowing aderes given by type * of) +02 Some important software interrupts at “TYPE d coresponds to division by 20). {TYPE 1 is used for single-step execution fr debugzing the pi {YPE 2 represents NMI and is used in power fale conditions “TYPE 3 represents a breakpoint interrupt. TYPE is the overfiw itera rate It lows the device to raster ane data thecPu, “he unetional Sick Diagram of OMA folows onsite ve fy 9) Dat bus butter gre. z Sh =| Ei bean ie Fe coe 5 Bk foc ase he. 1) ata bus ater: stem dats bus. 2 usta, isdectonal, eight bt bull which terfaces the 8257 tothe sued to Waser data between microprocessor and inter ‘egsters of 8257. n maser mod, t's se Lo send higher bye aes (A8-A15] onthe data bus » adie loge: When te CPs programming oF redng one ofthe itera esters of Pn 257 (2, when the 8257 si he save model, the Read/Meitelgi accaps the VO Read (Of or YO Write LOW) sign, decodes the leat significant four adress bts (AO ~A3) ond1) Oats Bus utter: te atr-stat,blrectional eight it butler which interfaces the #257 tothe system data bus. tn the ave mode, is used to ‘registers of £257, In master mode, it used to send higher byte address (AR-A15) onthe data bus nsfer data betveen microprocessor and iter 1 Read/Wrtelole: When the CPUs programming o reading one ofthe interna esters of Pin Diagram of 8257 (1, when the 8257 nthe ave mode), the Read/Wite lose accepts the YO ‘Read (OR) or VO Write (OWT sgn, decotes the last sinfcant four adres bits (AO~ 3) and ‘ether writes the contents ofthe data bus into the addressed register ( 1OW is ow) ar places the contents of the adresse reister onto the data bus(H10R sow) ‘the €257 fin the master mode) the Read/Write logic generates) (OMAwrte cele) oF YO wete and memory ead (OMA read cycle) transer between peripheral and memory deve. 1H) OMA channels: ‘The Pin Disgra of #257 provides four enti seo sateen reper: 1 OWA acres register ane 2. Terminal count register [DMA adress ester: t species necozsay to load vale memory adc Vo signals an the 16-bit eddress that accessed Icons of mode set register ad status este. 3° CPU to configure 8257 wheres the status registers ead hed a termina count condition and status of update fap 3 sgrificat four bts of mode set register, when set enable each ofthe ifieart four bits alow four dterent options fr the Pn Diagram ot by the CPU ate inaizing the DMA acess reqiters and cleared by the RESET input, thus sable al options, nhting al reverting bus conflicts o power up. As sald ear, indcates which chants have reached a termina count ‘andton and eludes the update flay described previously, The TC status bt, fone, nccates ‘terminal count has been reached for that channel Cit remains set un the status register ‘ead or the 8257 reset. The update ag, however, is not afected by a status read operation. The date fag bit fone nates CPU that 4257 is exeestng update cy. n update cyl 8257 loads parameters in chan! 31 channel 2. ii) Priory Resolver: rexlves the peripherals requests can be rogram o workin two aero aes mode or attng pity mode Control Register Format of 257, ‘he contol ester an 8 veqstr used to cnfigute the OMA's oe Deseition 7 Wewsonyanemary wanser enable (= Erabe 0 DaaUie) . thar aeControl Register Format of 825: ‘The control register is an 8-bit register used to configure the DMA's behavior. Here's the format: Bit Description 7 __ Memory to-memory transfer enable (1 = Enable, 0 = Disable). Channel priority (1 = Fixed, 0 = Rotating). Extended write enable (used for cascading). Enable or disable auto-initialization mode (1 = Enable). woalu oa Reserved (always 0) Channel mask bits (1 = Mask channel, 0 = Enable channel). Ans: Interface of 8257 with 8086 Microproce: Note: You can draw the diagram To interface the 8257 DMA controller 8086 microprocessor, the fol followed: i) Connection of Co} {uest from the 8086 microprocessor. After the transfer, the controller waits for the next request. | + Block Transfer Mode: This mode allows the 8257 DMA controller to transfer a block of data from the memory to an 1/0 device or vice versa. The block size and the number of blocks to be transferred are pre-programmed.+ Demand Transfer Mode: Aiso known as the "Auto-initialized DMA mode," this mode is similar to the block transfer mode, but the 8257 DMA controller automatically reinitializes itself after each block transfer. It is useful for continuous data transfer operations. + Cascade Mode: In this mode, multiple 8257 DMA controllers are cascaded to extend the number of DMA channels available. This allows for more complex and simultaneous data transfer operations. | | ‘Ans: MESI Pratocol Stands for (Modified, Exclusive, Shared, Invali I! protocol is @ cache coherence protocol used in multiproces ney between processor caches and main memory. It ensures th onsistent copies of the same memory block. Each cache block can exist in one of four statess 1. Modified (M) 2. Exclusive (E) 3. Shared (S) 4, Invalid (0) 1. Modified (M) n of the data, which, from the data in 1e block is replaced or evicted, it must fe data, which is identical to the main |i) Any Sccess to this block results in a cache miss, requiring the block to be fetched from main memory or another ¢ache. Working of MESI Protocol: 1. Read Request: 1) fa cache block is in the Invalid state, a read request triggers a cache miss, and the biock is fetched from memory of another cache.1. Read Request: i) Ifa cache block s in the Invalid state, aread request triggers a cache miss, and the block is fetched from memory or anather cache. eee ———— li) The block transitions to the Shared or Exclusive state, depending on whether other caches aiso have the block. 2. Write Request: |) Ha processor writes to a block in the Shared or Exclusive state, the state changes to Modified. li) Hfanother cache has the block inthe Shared state, it transitions to Invalid (write- invalidate mechanism) 3. Coherence Maintenance: i) When a processor modifies block in the Modified state, invalidate their copies of the block to maintain consistency. 3 sges of MESI Protocol: ' {Data Consistency: Ensures all proc shared memory. i) Efficient Cache Usage: Reduces u data fetching. Disadvantages of MESI Protocol that can be used to interface with rode 0, mode 1, and mode 2. fort A and Port B are configured as bidirectional gas a control port for setting various operational modes. oniy port A will work, port B can either isin mede Or 1 pal. The outputs as wel as inputs are latched. It has ty. Control Register is as follows: SEE VO function OFF 19 tinction of ACL 00: mo Yo tune ot Pou 0:0, on OL: yotunction otpa 9° 0/P Lor a8 K:m2 Gian Lue PW mad selection LimiThe mos significant bit (07)/s 1 forthe |/O mode and 0 for the BSR mode, D6 & DSitis used to set the port A mode. D6 D5 Mode O10 m0 0 -2022mt Oo X_m2 (D4 i used to tell whether port Ais taking input or displaying the result input otherwise displaying output. ed to tell whether port C higher bits ist 14 _ fritters pt outt. 2. Reduces Port C avaliablity. 3, Limited speed for high-performance systems. ‘Ans: Branch prediction logic: Yo avai this problem, Pentuw Uses a scheme cated Dynamic Branch Prediction. te Us scheme, a prediaion i made the branch isteuction current the pipeline The predicion wil either be taken oF sot taken. ifthe prediction is tue then the pipeline wil not be used and no dock cycles wil be lost he prediction Is fae then the pypeline is ushed and ‘taits over with the cusrent instruction. ils implemented using 4 way sel associated cache with2. Umted speed for high-performance systems. ‘An: Branch prediction lope: To avoid tis problem, Pentium uses a scheme called Oynamic Beach Prediction. this scheme, predtion is made forthe branch instruction current the pipeline The prediction wil ether be taken of not taken. the prediction i tue then the petine wil not, be flushed and no dock cycles willbe lot the predictions fase then the pilings Rushed and 256 erties. This calle Branch Target Ber (8TB). The sirectoryenty foreach line ents of + Vaid bt: ndcates whether the entry is valid or not Working of Branch Prediction: 1) BTB.s lookasde coche that sits tothe side of i) The st time that a branch instruction ret sorter te ta tm rt ec ragcmn a aes aig peonlereapesiiyciaia ‘The agra xpd by the following abe 1 ang Tabar agreed a wa 10 |Waniy Taken ranch Taken Upgraded te stongy | Downgraded owHistory Resulting Prediction if branch taken If branch not taken Bits Description made a Strongly Taken Branch Taken’ “Remainsinsame Downgraded to weakly state taken 10 Weakly Taken Branch Taken Upgraded to strongly | Downgraded to weakiy taken not taken on Weakly Not Branch Not _Upgraded to weakly@sDowngraded to strongly Taken Taken taken 00 Strongly Not Branch Not Upgraded to weakly Taken Taken not taken Advantages of branch prediction in the Pentium: |) Improved performance li) Increased instruction throughput !) Reduced branch misprediction penalty iv) More efficient use of processor resource: intages of branch predictid 16 reased complexity fncreased power consumption It is designed to interface the CPU 1n program the device according to Port-B, and Port-C. These ports are‘There are two diferent modes of 8255. These modes are: 2. Bit Sot Reset (BSR) Mode 2 Inpu/Outpur Mode 1. BR Set Reset (BR) Mod fe: This mode is used to st ‘ode always 07 wil be 0 The contra) OF reset the Fetisters looking tke this Dits of the Port-c only, For ASR Ad the port ¢ "Control register jg(2.12) Explain hyper threading technology adits use in Pentiun 4, Ans: i) Hyper-Threading Technology (HTT) is a technology developed by Intel to improve parallelization of computations performed on x86 microprocessors, li) {t allows a single physical processor core to behave like two logical processors, enabling better performance for multi-threaded applications iil) In the context of Pentium 4, hyper threading technology was introduced to improve the processor's efficiency in handling multiple tasks simultaneously. It works by duplicating certain sections of the processor—those that store the architectural state- glicating the main execution resources, iy) His allows the processor to schedule the execution of multiple threa improved overall performance iclal for Pentiu: ie Net Burst microarchi v) Hyper-Threading Technology (HTT) was parti ithelped to mitigate the performance limitati known for its relatively |ong pipeline and high| vi) By enabling better utilization of the proces: }oosts performance in multithreaded applications like video rendering, yy utilizing idle CPU resources, xiii) Disadvat of Hyper-Threading in Pentium 4: a) Limited Performance Gains: In CPU-intensive tasks, the performance improvement is minimal as both threads share the same physical resources. 4) Software Dependency: Applications myst be optimized for multithreading to fully benefit from HT, otherwise, there may be no noticeable improvementb} Software Dependency: Applications must be optimived for multithreading o fly benef fam It. otherwiee, there maybe no rateable nprowement, a eee G13) raw and expan Pentium 4 Net burst mieroarctecire, ‘Ans The Net Burst Mcroarchtecture was introduced in tls Pentium & processors to achieve ‘igh performance an higher cock speeds. It focuses on deep pipelines and efficent exacution Se eee eee 2) System Bus and Bus Uni: 1) Connects the processor tothe ster (eg, RAM, chipset) other devices 1) Incude Peper and Floating Pin (FP) execution units for mathematical operations 4) Connected to the Level 3 Data Cache, which provides faster data access compared to 2 Cache. 5) Ot-of Order Execation Engine: 1) Allows instructions tebe executed in a diferent order from their program sequence. 8) Opienzes resource uation by edu ide time for execution units a ‘iy once executed, isruction are reordered back nt sequence before reluement, 6) Retirement Unit: 1) Ensues instructions ae eed (comme) nthe eign program order. 1) Updates the processors architectural staee 5) Out-of-Order Execution Engine: I} Allows instructions to be executed in a different order from their program sequence, i) Optimizes vesource utilization by reducing ile time for execution units Ss ii)Once executed, instructions are reordered back into sequence before retirement. 6) Retirement Unit: i) Ens instructions are retired (committed) inthe original program order. Ji) Updates the processor's architectural state based on completed instructions. Key Features 1) The Pentium 4 had a 20-stage pipeline, allowing higher i) Helps in better instruction handling but increases penalty tions 2. Trace Cache: i) Unique to the NetGurst architecture, i) Stores decoded instructions, enabl execution without d repeated, 3, Outof-Order Execution: i) improves performanct wai the same applications. pid Execution Engine, 4) Divided IM two parts: an BKB instruction cache a ‘an 8 KB data cache Ii) Uses 2-way set associativity for efficient data management i))Directly connected to the processor, providing extremely fast access. 3) Level 2 (12) Cache: 1) Untied cache that stores both instructions and data, 1) Stee ranges from 256 KB to 2 MB, with higher associativity (typically 4-way oF more). C4 a am gf Madani at3} Love 2(12} Cache: 1) Sie anges from 256 KR to 2 Mi 4) Write-Back Policy: Data is written '5) MES Protocl: Ensures cache coh 5) Data Acces Hierarchy: 1) The processor fist checks the L 1H datas not foune, it checks the 's)OntyW datas absent in both ca 7) Performance Optimization: 1 sed dat, significant improv )Uoied cache that stores both instructions and data Eee \W)Aets as an intermediate storage layer, faster than my accesses and improving performance. ‘onsistency using Modified, Exclusive, Shared, his malt-level caching system minimizes’ ing overal system, 0°10 allocate me : lem efficiency, St tele Pece memary wastage eg eee anny boning best ft CEO Instead of sing SNE WY to Increase the me slow theweea ADRS, Hhdensity mene ‘he memory capacity of sales memory madlce FY Modules, sr, providing mtremnely fast acc B, with higher associativity (typically 4-way oF more) tain memory but slower than Lt cathe. to main memory only when necessary reducing memory terency In multiprocessor environments by maintaining data and invalid states. cache for data 1 L2 cache iches does the Processor access eontains even esses called Odd bank, /o* tower bankita) and Ode bank is locations from both banks arin doesnt make compulsory to PMOtY a needed, which : Hoch‘Ans: Descriptor Mechanism in Protected Made: 1. In protected mode, the 80386 microprocessor uses descriptors to manage memory segments Each segment is defined using a Segment Descriptor, which provides details about the segment's location, size, and access permissions. 2, A Segment Descriptor is a 64-bit entry stored in the Global De Descriptor Table (LDT). It contains: Table (GOT) or the Local 1) Base Address: Indicates the starting address of the segmer ii) Segment Limit: Defines the size of the segment. il) Access Rights: Specifies the type of sey allowed (read, write, execute). le, data, or syste iv) Flags: Includes additional properti 3. Tables for Descriptors: i) GDT (Global Descriptor ii) LOT (Local Descriptor Table} . 4. Role of Descriptors: ining pointers to Page Tables, ins entries mapping virtual pages to physical frames. irectory Index: Identifies the entry in the Page Directory. 1i) Page Table Index: Identifies the entry in the Page Table. iii) Page Offset: Points to the exact location within the page. 4. Paging is enabled by setting the Paging (PG) bit in the CRO control register, The CR3 register holds the base address of the Page Directory, 5, Benefits of Paging1) Virtual Memory: Allows the use of more memory than physically available by swapping pages between RAM and secondary storage. Ji) Memory Protection: Ensures processes cannot access pages belonging to other processes {iNon-Contiguous Allocation: Reduces fragmentation by allocating pages independently. 6. Role n Protected Mode: Paging works alongside segmentation to provide a robust mernory _management system, enabling multitasking, isolation, and efficantuse of memory. Ans: Addrossing modes are important in assembly language program is located and accessed by instructions, These modes describe how an i operands, whether they are immediate values, mem: ‘Types of Addressing Modes: ) Register Mode fi) Immediate Mode iil Displacement or Direct Mode 1y) Register Indirect Mode |v) Based indexed Mode | vitindexed Mode wi) Based Mode ‘operands are registers. type of addressing mode the source operand is. & bit or 16 bit data. be immediate data ADDAL, 45 ‘AND Ax, 0000 ii) Displacement ar Direct Mode: In this type of addressing mode the effective address ls directly siven in the instruction as displacement. Example: gg ey MOV AX, (DIS) MOV AX, 10500), |) Register indirect Mode: inthis adgiessing mode the elects asiress isin SI, OL or BX Example: Physical Addiess = Segment Agdless + Eftective Adress pl movax.ionaon eae aT ee a.16) Discuss in brie the protection mechanism of 83860X. ion ‘Ans: The 80386DX microprocessor includes a robust protection mechanism to ensure the integrity and security of system operations. 1. Segmentation-Based Protection: The 803860X uses segmentation to divide memory into segments, each with specific attributes like base address, size, and access rights. This ensures that processes cannot access | ‘memory outside their allocated segments. 2. Privilege Levels: ‘The processor supports four privilege levels (0 to 3), where lev {kernel mode) and level 3is the least privileged (user mode). This system resources based on the privilege level of the executing cod 3. Descriptor Tables: {) Global Descriptor Table (GOT): Cony tasks. ‘These tables define sey 4 Paging Protection: agi its own access yemory regions. it selectors and privilege levels. It ‘maintaining protection. _, General Protection Fault, Page Fault) are triggered if a program aintain system stability by preventing illegal operations. .80386Dx ensures process isolation, secure multitasking, and iit reliable for modern multitasking operating ns: Descriptor Mechanism In Protected Mode: 1. In protected mode, the 80386 microprocessor uses descriptors to manage memory segments; Each segment is defined using a Segment Descriptor, which provides detalls about theSte eran naragerent ane sttrnete operstons these ennteene terete General Purpose Registers (GPR), Segment Rogistrs, Control Registers, Debug Registers, Test Registers, and instruction Pointe. 1. General Purpose Registers (GPRs}: These 22-iragisters are used for arthmetie opel and ata transfer operations. They canbe accessed a 32-bit, 16-bt or 8 bit parts 1) AX (Accumulator Register) Used for arithmetic operations 1 EBX (ase Register: Used asa pointer to memory locations. Wi)ECX (Counter Ragister) Used for lop counters and shift operations IN)EOX (Data Register): Used in multiplication, division, and YO operations. Each register canbe divide: + AGB pa AK, BK, OF OX. + Sit part: AM/AL, BH/BL, CH/CL OH/OL. 2. Segment Registers: These 16-bit reisters store segment selectors segmentation. They ae ued to access diferent memory segments 1) C5 (Code Segment: Pont to the segment eo 1) (Stack Segment) Points to the seg IES (Entra Segment), FS and GS: Adon 5): This 42-0 reiterates the status ofthe processor and conti its 1) Stats Fags Indicate resus of erations eg, Zero Flag, Sn Flag, Cre Fo 1 Corto Fags: Control processor opications(e,Inlrrupt Enable Fag, Direction Fag) ipSystem Fags Manage atvanced features (eg, YO Prileg Love ‘os: The 4.6 ropes nt 486 Os 32 veer, which kd oto 16 nds ‘hat repreent specie status lag, These sas fags prone ilrmaton about he result ofthe resous amet o lg! operation performed by the processor tle aga,MOV AX, [DISP] MOV AX, [0500] iv) Regi )) Register Indirect Mader In this addressing mode the effective address is in SI, D) or 8X. Example: Physical Address = Segment Address + Effective Address : MoV AX, [01] ADD AL, [8X] Mov AX, [SI] ¥) Based Indexed Mode: In this the effective address is sum of base dex regist x register. Base register: BX, BP Index register: S!, DI vi) Indexed Mode: In this type of addressing mod and displacement. Example’ MOV Ax, [S#2000] MoV AL, [Dl+3000] vil) Based Mode: in this the effective Exampie! it MoV AL, [BP+ 0100] ‘effective address is vill) Based Indexed the sum of index regist Exampl Mov AL. 1d DF ix) String {tructions. In this the value of Slam in the value of directional fag, are auto incr Example: wus B jth input output operations. into various categories to SUPPOT rset of registers divided I ategorized a5 jor has 2 ricl rations. These registers are C ‘ans: The 80386 microprocess multitasking, memory managerme”t and arithmetic oper General Purpose Registers (GPRS), Segment Registers, control Register® Debug Registers, Test id instruction Pointer. «for arithmetic, !ogical, ane Registers, an Je 32-bit registers are Use 6-bit, or 8-bit parts 1e Registers (GPRS): Thes sed as 32-bit, 1 1. General Purpos be access jer operations. They ca data transfe(Contra Flags: Contrel processor = Fg Song, Carry Fag InteruptEoale Fg, Ovecton Fag) VO Prisege Level. ‘Operations (eg. System Flags: Manage advance features eg ‘The individual bits ofthe fag regster. A. Cary fag (CF): This figs sett ‘ost significant bt. Is used for 2. Parity fag (PF: This agi set the ‘Operation has an even numberof bts 3. Aula cary between bts 3 and: leas operations negative an anthmetic operation generates esi thats too lege or ton operand 89 Used Yo control the level of /0 privilege that fia s wie to control the execution of nested tasks La RF): This lags used for debasing purposes, (VA: This fags used to contol the execution of vital 8086 mode, ching AC): Thi fags use vo datect unaligned memory accesses 27 _ }alinerrupt ag (vif): Tis ag is used to conto te execution of vrtua interrupts. 2 interrupt pending (IPF Ts gs use to indicate the presence ofa pending Waal ntreupt. cy | 0.21) expan the segment descsitor of 90386 processor. ‘Ans: i) the Protected made, Meme management uses the segment selector to acess on wnt whch provides the pracesor ‘escrito, segment descriptors area part ofthe sagmentaton vn whch linear ares, GaN Spee pli banca cout aiimeslia wari 416. Virtual interrupt fag te the preser - etual interrupt pending lag (VIP): This fag Is used to ind © indicate the presence of a pending virtual interrupt. er a TS In the Protected mode, Memory management uses the segment selector to access a descriptor, segment descriptors are a part of the segmentation unit, which provides the processor with the data it needs to translate a logical address into a linear address. Ii) A segment descriptor isa special structure that describes the segment, yr must be defined for each segment of the memory. ii) Exactly one segment descriptor ven region of inear iv) Descriptors are eight types of quantities that contain attributes, address space. jude the 32-bit base linear address ofthe seer and vi) These attributes in read, write, or execute granularity ofthe segment, the protection level, of the operands (16-bit or 32-bit), and the type of segmest- SEGMENT LIMIT 15..0 Pal tees ) fine the attributes sddress, segment ponents SEGMENT BASE 15..0 fescriptor in the 80386 pr vii) The segment d in memory. ttcontai ‘and location of a a ») system, ete), a .gment (code, dat, Be segment operation, such as granularity, ind protection in the ts of memory based 0” Jal role in memory management 3 sss and protect different segment (store string Byte) 1 the AL register into the memary cation struction stares the contents of plis incremented; if DF = 1 O15 decremented. iv) Example.mw} fsa MOV AL'S); Load ASCII Fors ADDAL S| Ad ASCH Fors ee meena cl AAA Aalst AL (Result = O84, valld ScD) 6.PusH: ‘i Syotax: PUSH rea/mem MBampe MOVAX.1234H Load AX wth data PUSH ax Store AX on stack 7.00: 2 Open: The Ss incremented by 3 W)Syotax: FOP reg/mem Mbampie DKAK, oF EDX:cay,2) [oiI=AL 1) tthe Diecton Fag (OF =0, Os ietemented, HOF 1, bli decremented fi)Synax: STOS® example Ree MOVALA —;toad'A'into AL ‘MOV 01, 20001; Set OI to memory address 2000H sTos@ Store’ at [20001] and increment 0 2. DAA Decimal Adjust for Addon): 1) Defintion: Adjusts the result of ang two BCD numbersin Ato form a valid 8CD result. 1 Operation 2) ifthe lower nibble f AL> 9 or Auxiliary Carry is se, 6s 1b) ifthe upper nibble of AL> 9 or Carry is set, 60H iad 1 ip syntax DAA example MOVAL 25H; Lead BCD number 25 into AL ADDAL, 34H; Add 38H (8C0) ona Acjust est to 8CD (AL = 59 3.XLAT (Transat): 1) Deftion: Replaces the value in 1) Operation: AL= [BX + AL} lapsyotax aT: byte from a lookup table in example just the test in AL. ater adding two ASCI- coded decimal numbers, ‘he ower nile of AL > 9 or Alar Cary set 6 added tol, and AH is incremented by 3 i)symtan AAA Esample "5 :load ASC for 2) 3 Add ASG for 3 MAA Aust ALR 6.pusi 8H was 8D) 3) Definition: Pushes a ward (16 bs} fom a restr or memory onto the sack | 2rmation te ssc sits decremented by 2 and he value stored tthe now ]ost “The architecture is divided into 4. Bus interface Unit (BI) fe cycles such as Memory , Fetches instruction from 1) address for the Code Segment. All programs are stored pled by 20H (26), to.gve the 20-bit physical adaress of the Code toe modified by executing any Instruction except branch instrUstions ‘egment.It is multiplied by 10H se (Segment) address forthe Data S 1fDS = 4321H then DS x 10H the 20-bit physical address of the Data Segment. Eg 1g address of Data Segment, olds the base-{Segment) address forthe Stack Segment, [tm ultiplied by 10H SS Registe (16d), to gve the 20-bit physica adaress ofthe Stack Segment. 4) £5 Register: ES hid the base (Segment) address for the Extra Se 5 af the Extra Segment .gment, It is multiplied by 10H (16d), to give the 20-bit physical addres 6-bit register. It holds offset of the next instruction in the after Ii instruction Pointer (register): Iisa 1 Code Segment. Ad every instruction byte {dress ofthe next instruction is calculated as CS x 10H + IP. IP is incremente is fetched. IP gets a new value whenever o branch occurs ill Address Generation Circuit: The BIU has a Physical Address Generation Circuit, It generates the 20h yl wrens sr uot a fet res ng the formula; Physical Address (20 bi) = Sepmient Address (16 bit) X 10H + Offset Address (16 bit) Iv) Pipelining: It is 2 6-byte FIFO RAM used to Implement Pipelining, Fetching the nest instruction singe instruction Is aled Pipelining, BLU fetches the next “si instruction aE Dee: are et ne 4ES RelttBS Mids bse ia weal ori Es SAVE lal (16d), to give the 20-bit physical address of the Extra Segment. a instr (ger: Ha 0: ett a i i an Chae Seger Adress ofthe fet nstueon eles 108 Pine ot eveiy instruction byte is Fetched. IP gets a new value whenever a branch occurs ee it: The BIL has a Physical Address Generation Circuit. ft generates the i) Address Generation Circuit dross (20 20-bit physical address using Segment and Oifset addresses using the formula: Physical A bit) = Segment Address (16 bit) X 10H + Offset Address (16 bit. iv) Pipelining: tis a6 byte FIFO RAM used tolimpiement Pipelining. Fetching the next instruction while executing the current instruction is called Pipelining. BIL fetches the next “six instruction- bytes from the Code Segment and stores it inte the queue, Execution Unit (EU) removes instructions from the queue and executes them. 2) Execution Unit (EU):i) It fetches instructions from the Queue In them. nal data transfer operations. int performs arithmetic, logic and inter rates in synchronization with T Biu to access the external module. t ope “The main components of the EU 21 i) General Purpose Registers: 8086 has four ‘These are available tothe programmer, for s divided into two 8-bit registers such 25 AH, Al these registers also have some function a) AX Register (16-Bits): It holds ‘operations. All 10 data transfers functions as accumulator during 5 b) BK Register (1gBit):t holds the memo modes. ues during Multiplication 206 direc 10 addressing mode. Pass of the top of the Stack. stackisa set of cused with the SS Register to calculate ns ike PUSH, POP, CALL, RET Pits incremented by 2 ne stack segment It UFO manner. $i ment, it used during struction reremented by 22nd during Fe offset address of anyocation nt locations ofthe stack ie normally used to hold the ofiset adres 01 Se sed Peer segments using segment Oven holds offset address of rain Data Segment, during string Operations reson (0) 16-8): ts normaly used to old Ne i or ihr segments ing segment Over ‘string Operations ms and 16-bit arithmetic 3 the Control Unit: The EU fetches tution Decoder decodes it and pata segment but wet address fr Extra segment of address of _ iding. It hoids offset. cate ara oC AL. ret ter and instruction Decoder (resent ie instruction Register. The lst esti nd logic operations iy o) ALY (26-8) Iv) instruction Rett Jeue into the l ‘an apeade from the au ane information tthe contra GTewE Fo SSi) e) ALU (26-01): thas 8 16-bit ALU. t performs & and A6.bit arithmetic and logie operations |v} lnstruction Register and Instruction Decoder (Present inside the Control Unit}: The EU fetches an opcode from the queve Into the instruction Register. The ruetion Deces sends the information to the control dreuit for execution, "0 Compare 80386, Pentium 1, Pentium 2, and Pentium 3 processor. Ans:1) Differentiate between Real mode, Protected mode and Virtual mode. Feature Real Mode 20-bit addressing. Virtual 8086 mode allows suppons upto 1MB [supports upto4G8 —_ | each program to address 1 memory memory. MB in a protected 32-bit acdressing ‘Memory [No memory Provides memory Protection | protection. Programs. | protection using Can overwrite each | segment descriptors other Multitasking | Not supported Nat avalabie Not available Privilege Levels inder protected Slower than Similar to protected mode but slighty slower due to virtual machine emulation ‘Speed protection any [Each virtual machine has its Descriptor Table (101). own IVT, managed by the os. Interrupt Handling Used for modern Used to run rear-mode operating systems, programs (e., DOS multitasking, and large | programs) ina protected programs environment, [30386 and above (in protected mode) — we and Hardware Interrupts 34) Software and Hardware interrupts Ss ‘oftware Interrupts Hardware Interrupts Triggered by a software instruction | Triggered by an external hardware sigral or (e.g., INT instruction). device (e.g., keyboard, timer) Ans: Trigger Comes from the program or nal hardware devices. software. Used for system calls, debugging, 0° requesting OS services. INT 21H (DOS service}, INT 80H (Linux syscall). Slower because it depends on. program execution. Priority ‘Dependency = — Gadress space for both Priority i program Manually generated by programmer. for Tses separate address space inet from memory. ye devices, dist Uses fewer address lines (usually 16-bit) Ties special instructions (IN, OUT) for |/0 operations. Jar memory instruc sed via 7 devices are acces Tare accessed a5 memory specific /0.ports locations: Sanity slower since special VO ed, Faster access 2s the same address us is qui and VO. instructions are r= used for memon Tas memory and 1/0 Simple aadress yemory and 1/0 devices have senarat® Tomplex, a both m to the same address More Hardware are mepped complexity spaces space:reba) ees spec etuchons (WOU) V0 operations. for V0 operations Fadoare Complesity — TO devices are Rens Fe EMO [70 devices are accessed va specie V0 ports. Sigiy tower since spe nsteetions are required 70 Nore complex ssbothmemery and 70 [Simpler ss memory and 70 are mapped into the same address | devices have separate address space spaces More feb, slows easy integration of [less Fenble, designed mami Tor memory and /0. simpler VO operations [a0386, Pentium series Wemony-mapped | B085, 8086 Nand OUT spiny, aucio cares Instructions for /0 operations).