SESSION 2021-22

CT1
Here is the full answer sheet for your Class Test-01:

1. Define Machine Cycle, Instruction Cycle, Fetch and Execute Cycle (Marks: 05)

 Machine Cycle: A machine cycle is the basic operation cycle of the microprocessor to
execute a single operation like reading from memory, writing to memory, fetching an
instruction, or executing an instruction.
 Instruction Cycle: It is the time required to fetch and execute a complete instruction. It
consists of one or more machine cycles.
 Fetch Cycle: The fetch cycle is the part of the instruction cycle where the microprocessor
fetches the instruction from memory.
 Execute Cycle: The execute cycle is the part where the control unit interprets the
instruction and performs the required operation.

2. Determine the Addressing Modes for the Following Instructions (Marks: 10)

Instruction Addressing Mode

i). MOV CH, 8 Immediate Addressing Mode
ii). MOV AX, DS:START Direct Addressing Mode
iii). MOV [SI], AL Register Indirect Addressing Mode
iv). MOV SI, BYTE PTR [BP+2][DI] Based Indexed with Displacement
v). MOV AX, [2300] Direct Addressing Mode

3. Assume DS = 1120H, SI = 2498H, and AX = 53EFH. Show the contents of

memory locations after the execution of MOV [SI], AX (Marks: 05)

 Instruction: MOV [SI], AX → Stores AX into the memory address DS:SI.

 DS = 1120H → Physical base address = 1120H × 10H = 11200H
 SI = 2498H → Effective offset
 Physical Address = 11200H + 2498H = 13698H
 AX = 53EFH → AH = 53H, AL = EFH
 Stored in little-endian:
o 13698H = EFH

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 o 13699H = 53H

4. Give the contents of the flag register after execution of addition 65D1H + 2359H
(Marks: 05)

 Operation: 65D1H + 2359H = 89 2AH

Let’s add:

65D1H
+ 2359H
--------
892AH

Now check flag outcomes (based on 16-bit addition):

 Carry Flag (CF): No carry beyond 16 bits → 0

 Zero Flag (ZF): Result ≠ 0 → 0
 Sign Flag (SF): MSB of result = 1 → 1000 1001 0010 1010 → MSB is 1 → 1
 Overflow Flag (OF): No overflow occurred in signed arithmetic → 0
 Auxiliary Carry (AF): D1 + 59 = 12A → Carry from bit 3 to bit 4 → 1
 Parity Flag (PF): 892A = 1000 1001 0010 1010 → Has even number of 1s (6 ones) →
1

Flags Summary:

 CF = 0
 ZF = 0
 SF = 1
 OF = 0
 AF = 1
 PF = 1

Let me know if you'd like this formatted into a printable PDF!

CT2
1. Why Are Interrupts Important?

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Interrupts are essential in microprocessor systems because they allow the processor to respond to
real-time events efficiently without continuously checking the status of all devices (polling).
Interrupts make the system more responsive and help to manage tasks asynchronously, enabling
the CPU to focus on processing tasks instead of being dedicated to I/O operations.

Interrupt Processing Flow:

1. Interrupt Request (IRQ): An external device sends an interrupt request signal (IRQ) to
the microprocessor.
2. Interrupt Acknowledge (IAK): The microprocessor acknowledges the interrupt request.
3. Context Saving: The processor saves the current context (e.g., registers, program
counter) onto the stack.
4. Interrupt Service Routine (ISR): The processor jumps to the interrupt service routine
(ISR) associated with the interrupt.
5. ISR Execution: The ISR handles the interrupt (e.g., reading data, performing a specific
task).
6. Context Restoration: After the ISR completes, the processor restores the saved context
(registers, program counter).
7. Return from Interrupt: The processor returns to the previous instruction in the main
program.

2. Differentiate Between Software and Hardware Interrupts

Aspect Hardware Interrupts Software Interrupts

Generated by hardware devices (e.g., Generated by software (program or
Source
keyboard, I/O devices) instruction)
Triggering Physical events like data available from A specific instruction in the
Event I/O, timer, etc. program (e.g., INT instruction)
Control Controlled by external hardware signals. Controlled by the software code.
Keyboard interrupt, timer interrupt, mouse
Examples INT instruction, system call in OS
event
Hardware interrupts can have priorities Software interrupts typically have
Priority
(e.g., maskable or non-maskable). lower priority.
Generally faster as they directly interrupt Slower as they are invoked by the
Speed
the processor's normal operation. program’s instructions.

3. Explain XLAT, PUSH, POP, and XCHG Instructions

 XLAT (Translate):
o Purpose: Used to translate a byte from the AL register using a lookup table.

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 o Usage: XLAT replaces the value in AL with the byte at the memory location [BX +
AL].
o Example: If BX = 1000h and AL = 05h, XLAT would replace AL with the byte
from memory location 1005h.
 PUSH:
o Purpose: Pushes a register or memory value onto the stack.
o Usage: PUSH <operand>
o Example: PUSH AX will store the value of AX on the stack.
 POP:
oPurpose: Pops a value from the stack into a register or memory.
oUsage: POP <operand>
oExample: POP BX will load the value from the top of the stack into the BX
register.
 XCHG (Exchange):
o Purpose: Exchanges the contents of two registers or a register with a memory
location.
o Usage: XCHG <operand1>, <operand2>
o Example: XCHG AX, BX exchanges the values of AX and BX.

4. Draw a Microcomputer System with DMA Controller and Explain Its

Operation

Microcomputer System with DMA Controller:

+-----------------+
| Processor |
| (CPU) |
+-----------------+
|
+--------+--------+
| |
+-----------+ +-----------+
| DMA Controller| | I/O Device|
+-----------+ +-----------+
| |
+------+ +-------+
| Memory| | Memory|
| Block | | Block |
+------+ +-------+

DMA Operation Explanation:

1. DMA Controller: A DMA (Direct Memory Access) controller is a specialized circuit

designed to handle data transfer between memory and peripherals without involving the
processor.

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 2. Request: When an I/O device (e.g., a disk or keyboard) needs to transfer data to/from
memory, it sends a DMA request signal to the DMA controller.
3. CPU: The processor relinquishes control of the system bus to the DMA controller after
checking if the bus is available.
4. Data Transfer: The DMA controller directly transfers data between the I/O device and
memory. This frees the CPU to perform other tasks while data transfer occurs in the
background.
5. Interrupt: After the data transfer is completed, the DMA controller sends an interrupt to
the CPU to signal the completion of the operation.

In summary, DMA improves system efficiency by allowing data transfer to occur directly
between memory and I/O devices, without continuous CPU intervention. This allows the CPU to
focus on other tasks while data is being transferred.

SESSION 2020-21
Sure! Here's a more detailed explanation for each question of your Class Test-1
(Microprocessor) on the 8086 microprocessor, with proper headings and clear formatting:

CT

Microprocessor Questions & Answers

1. Write down and briefly describe the steps to initialize an 8254 Programmable
Peripheral Device with the control word format.

Marks: 5 + 5

Overview of 8254 (Programmable Interval Timer):

The Intel 8254 is a programmable timer/counter chip with three independent 16-bit counters.
Each counter can be programmed for various modes like delay generation, frequency division, or
event counting.

Steps to Initialize 8254:

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 1. Select the counter (Counter 0, 1, or 2).
2. Set the mode (e.g., mode 0: interrupt on terminal count, mode 2: rate generator, etc.).
3. Choose read/load format (e.g., LSB only, MSB only, or LSB followed by MSB).
4. Write the control word to the Control Register.
5. Load the initial count value into the selected counter.

Control Word Format (8 bits):

D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD

 SC1-SC0: Select Counter (00: Counter 0, 01: Counter 1, 10: Counter 2)

 RW1-RW0: Read/Write mode
o 00: Counter Latch Command
o 01: LSB only
o 10: MSB only
o 11: LSB then MSB
 M2-M0: Mode selection (0 to 5)
 BCD: 0 = Binary, 1 = BCD counting

2. Write a short note on Device Addressing Modes and Type-2 Interrupt.

Device Addressing Modes:

These define how a peripheral device is accessed via memory or I/O. Two main types:

1. Memory-Mapped I/O:
o Devices treated like memory locations.
o Full memory instructions (e.g., MOV, ADD) can be used.
o Higher memory address range usage.
2. Isolated I/O (I/O Mapped I/O):
o Separate I/O address space (using IN and OUT instructions).
o Needs special control signals (like IO/M).
o Limited to 256 input and 256 output ports (8-bit address).

Type-2 Interrupt (INT 2):

 A hardware interrupt with vector number 2 (INT 2).

 Corresponds to Interrupt Request Line IR2 of the 8259A PIC.
 Vector Address for INT 2:

Vector Address=2×4=0008H\text{Vector Address} = 2 \times 4 = 0008H

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 So, control jumps to memory address 0008H–000BH (holds CS:IP of ISR).

3. If an interrupt has been requested, the 8086 responds by stepping through

some major actions. Summarize those steps with a diagram.

Marks: 3½

8086 Interrupt Response Steps:

1. Complete current instruction.

2. Save flags register to the stack.
3. Clear TF and IF flags (disable further interrupts).
4. Push CS and IP (current code segment and instruction pointer) to stack.
5. Load new CS:IP from interrupt vector table.
6. Jump to ISR (Interrupt Service Routine).

Diagram (Text Form):

+------------------------------+
| Current Instruction |
+------------------------------+
↓
Push FLAGS to Stack
↓
Clear IF and TF
↓
Push CS to Stack
↓
Push IP to Stack
↓
Load CS:IP from vector table (INT n * 4)
↓
Jump to ISR

Let me know if you’d like a visual image of this flow.

4. Suppose that while the 8086 is executing the IR4 service routine, an interrupt
signal arrives at IR7 input pin of 8259A. Now illustrate the response of 8259A
with a diagram.

Marks: 3½

What Happens in This Case (Nested Interrupt):

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  8259A receives interrupt on IR7 while servicing IR4.
 If priority is fixed: IR7 > IR4, so it waits (IR7 is pending).
 If priority is rotating or auto EOI, it may accept IR7.
 After IR4 ISR finishes and EOI (End of Interrupt) is issued, IR7 is processed.

8259A Response Steps:

1. IR7 line goes high.

2. 8259A checks if IR7 has higher priority.
3. If yes and interrupts are enabled, sends INT to 8086.
4. 8086 completes IR4, acknowledges new interrupt.
5. 8259A puts vector address for IR7 (INT 7) on the data bus.
6. 8086 executes ISR for IR7.

Would you like a diagram showing IR7 arriving during IR4? I can generate it for better
understanding.

Summary

Would you like this entire content as a downloadable, printable PDF with proper formatting
and diagrams included?
Or should I send visual diagrams separately now?

Thanks for your clarification! Here's the updated and improved version of the answers based
on your modified questions:

1. Clearly explain the sequence of operations that take place for data transfer in
non-burst and burst mode.

Non-Burst Mode (Single Transfer):

 In non-burst mode, data is transferred one at a time (one byte/word).

 After every data transfer, control of the bus is returned to the CPU.
 It is slower but more controlled.

Sequence:

1. CPU sends address and control signals.

2. One data is transferred.
3. DMA releases the bus.

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 4. This repeats for each data transfer.

Burst Mode (Block Transfer):

 In burst mode, DMA takes control of the system bus and transfers many bytes
continuously.
 The CPU is blocked until the entire block is transferred.
 It is faster, used for high-speed data transfers.

Sequence:

1. CPU grants DMA full control.

2. DMA starts transferring data block.
3. Bus is not released between transfers.
4. DMA releases the bus after completing the block.

2. What is cycle stealing mode?

In Cycle Stealing Mode, the DMA controller pauses the CPU for one clock cycle to
transfer a byte of data.

 CPU is not completely stopped — just one cycle is "stolen" per transfer.
 It balances CPU work and data transfer.

Real-Life Example:
Like a friend interrupting you for just 1 second to borrow a pen — you continue your work right
after.

3. Draw the block diagram of 8237 DMA Controller.

The 8237 DMA Controller is used to transfer data between memory and I/O devices
without involving the CPU.

Main Components (Text Overview):

 4 DMA Channels
 Address Register (per channel)
 Word Count Register (per channel)
 Command Register
 Request & Mask Registers
 Status Register

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  Data Bus Buffer
 Control Logic

Would you like me to provide a ready-to-use diagram image of the 8237? I can generate
that.

4. Briefly describe the differences between an I/O channel and an I/O processor.

Feature I/O Channel I/O Processor (IOP)

Operates under CPU's
Control Can operate independently from the CPU
instructions
Processing Has its own logic & CPU for decision
Just transfers data, no logic
Power making
More complex, can manage multiple
Complexity Simple and fast
devices
Example DMA controller Disk controller with a CPU

Summary:

 An I/O channel is a simple helper.

 An I/O processor is a smart helper that can do tasks on its own.

6. Describe 2 different working cycles of DMA controller.

The DMA controller has several working cycles. Two common ones are:

a) Read Cycle:

 DMA reads data from the source (usually memory or I/O).

 It places the address on the bus and sets MEMR or IOR low.
 Data is read and stored internally.

b) Write Cycle:

 DMA writes data to the destination (usually memory or I/O).

 It places the destination address on the bus.

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  Sets MEMW or IOW low and sends data.

These two cycles happen back-to-back during burst or single transfers.

Would you like this full answer as a well-formatted PDF with a diagram of the 8237 DMA
controller included?

Thanks for pointing that out! Below is the corrected answer for addressing modes of the 8086
microprocessor, with clear definitions and examples.

5. Describe the addressing modes of the 8086 microprocessor

with examples
The 8086 microprocessor supports several addressing modes to access data. These modes
define how operands are specified in instructions.

1. Immediate Addressing Mode

 The operand (data) is given directly in the instruction.

 Data is constant (hardcoded).

Example:

MOV AX, 1234H ; Load AX with the immediate value 1234H

2. Register Addressing Mode

 The operand is in a register.

 Fast access to data from CPU registers.

Example:

MOV AX, BX ; Copy contents of BX into AX

3. Direct Addressing Mode

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  The instruction contains the memory address directly.
 Effective when accessing fixed memory locations.

Example:

MOV AX, [1234H] ; Load AX from memory location 1234H

4. Register Indirect Addressing Mode

 The address of the operand is in a register (like BX, SI, DI, BP).
 More flexible than direct addressing.

Example:

MOV AX, [BX] ; Load AX from the memory address in BX

5. Based Addressing Mode

 Uses base registers (BX or BP) and a displacement (offset).

 Useful for accessing structure fields or array elements.

Example:

MOV AX, [BX + 04H] ; Load AX from address = BX + 4

6. Indexed Addressing Mode

 Uses index registers (SI or DI) with displacement.

 Good for accessing arrays.

Example:

MOV AX, [SI + 02H] ; Load AX from address = SI + 2

7. Based-Indexed Addressing Mode

 Combines base (BX or BP) and index (SI or DI) registers.

 Used for complex data structures like 2D arrays.

Example:

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MOV AX, [BX + SI] ; Load AX from address = BX + SI

8. Based-Indexed with Displacement Mode

 Uses base + index + displacement.

 Most flexible mode in 8086.

Example:

MOV AX, [BX + SI + 05H] ; Load AX from address = BX + SI + 5

These addressing modes allow the 8086 to access data from registers, memory, and
immediate values efficiently, supporting both simple and complex data structures.

Would you like a clean PDF version of all the answers (including 8237 block diagram and these
addressing modes)?

SEMESTER
Here’s a clear and simple explanation of the requested topics from the 8086 microprocessor
syllabus:

What is the purpose of the S1, S2, and S3 pins in an 8086

microprocessor?
These status pins (S0, S1, S2, S3) indicate what operation the microprocessor is performing or
which segment it is accessing.
Let’s focus on S1, S2, and S3 (S0 is usually grouped with S1):

S0 and S1 (Status Lines)

 These two lines indicate the current operation type:

S1 S0 Operation
0 0 Interrupt Acknowledge
0 1 Read
1 0 Write
1 1 Passive (No operation)

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 S3 and S4 (Segment Select Lines)

These indicate which segment register is currently being used:

S4 S3 Segment Register
0 0 Extra Segment (ES)
0 1 Stack Segment (SS)
1 0 Code Segment (CS)
1 1 Data Segment (DS)

Segment and Address Register Combinations in 8086:

8086 uses Segment Registers and Offset Registers to form 20-bit physical addresses using
this formula:

Physical Address = Segment Register × 10H + Offset

Segment & Offset Register Pairs:

Segment Register Offset Register Purpose

CS (Code Segment) IP (Instruction Pointer) Fetching instructions
DS (Data Segment) BX, SI, DI, etc. Accessing data variables
SS (Stack Segment) SP, BP Stack operations (push/pop)
ES (Extra Segment) DI Used in string operations

Write a brief note on:

(i) Memory Banking

 8086 has a 16-bit data bus, but memory is organized in bytes (8-bit).
 So memory is divided into two banks:
o Even Bank: Lower byte (D0–D7)
o Odd Bank: Upper byte (D8–D15)
 Bank selection is done using:
o A0 (Address line): decides odd/even
o BHE (Bus High Enable): enables upper byte

Why it matters: Allows the 8086 to access 16-bit data in one cycle if aligned properly.

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(ii) Instruction Queue

 8086 uses pipelining to speed up execution.

 It has a 6-byte instruction queue in its BIU (Bus Interface Unit).
 While EU (Execution Unit) executes an instruction, BIU prefetches the next instructions.
 This helps in overlapping fetching and execution, increasing speed.

(iii) Memory Segmentation

 8086 uses segmentation to divide memory into logical blocks, each 64 KB.
 Four main segments:
o Code Segment (CS) – for instructions
o Data Segment (DS) – for data
o Stack Segment (SS) – for stack
o Extra Segment (ES) – for extra data/string operations
 Segmentation allows accessing 1 MB memory using 16-bit registers by combining
segment:offset.

Example:

CS = 2000H, IP = 0100H → Physical Address = 20000H + 0100H = 20100H

Would you like this in PDF format with diagrams for segmentation and memory banking?

Here is a clear and simplified explanation for each question you asked:

1. Write down and briefly describe all the steps to initialize an 8254
Programmable Peripheral Device with the control word format

To initialize the 8254 timer, follow these steps:

Steps:

1. Select the counter (Counter 0, 1, or 2).

2. Choose the mode (from Mode 0 to Mode 5).
3. Choose the read/write operation (Read LSB, MSB, or both).
4. Write a control word to the Control Register.
5. Write the count value to the selected counter port (e.g., Port 0 for Counter 0).

Control Word Format (8 bits):

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| D7 D6 | D5 D4 D3 | D2 D1 | D0 |
| SC | RW | M | BCD|

 SC (Select Counter): 00 = Counter 0, 01 = Counter 1, 10 = Counter 2

 RW (Read/Write): 11 = LSB first then MSB
 M (Mode): Mode 0 to Mode 5 (3 bits)
 BCD: 0 = Binary counting, 1 = BCD counting

Example Control Word (Counter 0, Mode 3, LSB+MSB, Binary):

SC=00, RW=11, Mode=011, BCD=0 → 0011 0110 → 36H

2. Explain the "Hardware Retriggerable One Shot" mode of 8254 counter and its
application

This is Mode 1 of 8254.

How it works:

 When a trigger (low-to-high pulse on GATE) is received:

o The output goes low for a specified duration.
 If another trigger is received during the delay:
o The delay restarts (retriggered).
 After the time elapses, the output goes back high.

Applications:

 Used in pulse-width generation, monostable timers, and switch debouncing.

 Example: Triggering a relay for a fixed time period after a button press.

3. Counter 0 to produce 78.6KHz square wave using 2.45MHz clock (SDK-86)

Given:

 Clock = 2.45 MHz

 Desired Output = 78.6 KHz

Step 1: Calculate the count value

Divisor (N) = Input Clock / Output Frequency

= 2,450,000 / 78,600 ≈ 31.2 → Use N = 32 (approx)

Step 2: Control Word for Mode 3 (square wave mode)

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  Counter: 0 (SC = 00)
 Read/Write: LSB+MSB (RW = 11)
 Mode: 3 (M = 011)
 BCD: 0 (binary)

→ Control Word: 00110110 = 36H

Step 3: Initialization

 Write 36H to Control Register

 Send Count 32 (in two steps):
o Write LSB = 20H
o Write MSB = 00H

4. Describe the function of the general-purpose registers of 8086 microprocessor

8086 has 8 general-purpose registers, each 16-bit, and can be accessed as two 8-bit registers.

Register Function
AX Accumulator for arithmetic, logic, and I/O operations
BX Base register (used in memory addressing)
CX Count register (used in loops and shifts)
DX Data register (used in multiplication and division)
SI Source Index (used in string operations)
DI Destination Index (used in string operations)
BP Base Pointer (used to access stack data)
SP Stack Pointer (points to top of stack)

AX, BX, CX, DX can be accessed as AH/AL, BH/BL, etc.

5. How the physical address is obtained from a logical address in 8086

In 8086, memory is accessed using a segment:offset format.

Formula:

Physical Address = (Segment × 10H) + Offset

Example:

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If:

 Segment = 1234H
 Offset = 0020H

Then:

Physical Address = 1234 × 10H + 0020H = 12340H + 0020H = 12360H

This allows 8086 to access up to 1 MB of memory using 16-bit registers.

6. Discuss the role of interfacing in microprocessor systems, including examples

of common interfacing techniques

What is Interfacing?

 Interfacing is the process of connecting the microprocessor to external devices, like

memory, displays, keyboards, ADCs, etc.

Types:

1. Memory Interfacing: Connecting RAM/ROM to CPU

2. I/O Interfacing:
o Programmed I/O: CPU directly manages data transfer.
o Interrupt I/O: Device interrupts CPU when ready.
o DMA (Direct Memory Access): Data moves without CPU.

Common Interfacing Chips:

 8255 – for I/O ports (keyboard, switches)

 8254 – for timers/counters
 8259 – interrupt controller
 8279 – keyboard/display controller

Example:

 Interfacing a 7-segment display using 8255.

 Interfacing a timer using 8254 to generate accurate delays.

Would you like this as a clean print-ready PDF with diagrams?

Certainly! Here's the question followed by the full answer with clear explanation and values:
18 | P a g e
 Question:

Suppose that you want to use counter 0 of the 8254 to produce a stable 78.6 KHz square
wave signal for a UART clock by dividing down the 2.45 MHz PCLK signal available on
the SDK-86 board. Now write down the complete control word and describe it.

Answer:

To generate a 78.6 KHz square wave from a 2.45 MHz clock using Counter 0 of the 8254
Programmable Interval Timer, we need to follow these steps:

Step 1: Calculate the Count Value

We use the formula:

Count=Input ClockOutput Frequency=2,450,00078,600≈31.2\text{Count} = \frac{\text{Input

Clock}}{\text{Output Frequency}} = \frac{2,450,000}{78,600} \approx 31.2

So, use Count = 32 (rounded to nearest integer).

Step 2: Choose the Mode and Write the Control Word

We use Mode 3 (Square Wave Generator) because it produces a continuous square wave with
50% duty cycle, ideal for UART timing.

Control Word Format (8 bits):

| D7 D6 | D5 D4 | D3 D2 D1 | D0 |
| SC | RW | Mode | BCD|

Control Word Fields:

Field Value Explanation

SC 00 Counter 0 selected
RW 11 Read/Write LSB then MSB
Mode 011 Mode 3 – Square Wave Generator

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Field Value Explanation
BCD 0 Binary counting mode (not BCD)

Final Binary: 00 11 011 0 → 00110110

→ Control Word = 36H

Step 3: Send Initialization Values

Assuming:

 Control Register = Port 3

 Counter 0 = Port 0

Write Sequence:

1. Send 36H (control word) to Port 3

2. Send LSB of count value (32 = 0020H):
→ LSB = 20H → Write to Port 0
3. Send MSB = 00H → Write to Port 0

Summary Table

Step Action Value Port

1 Write control word 36H Port 3
2 Write count (LSB) 20H Port 0
3 Write count (MSB) 00H Port 0

What Happens?

 The 8254 Timer now divides the 2.45 MHz clock by 32.
 Output of Counter 0 becomes:

2.45 MHz32≈76.6 KHz\frac{2.45\, \text{MHz}}{32} \approx 76.6\, \text{KHz}

Note: If exact 78.6 KHz is needed, then Count ≈ 31, but that gives less symmetry. Using 32
ensures a stable square wave for UART even if slightly under 78.6 KHz.

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Would you like me to include this in a print-ready PDF or add a labeled diagram of the 8254 and
waveform?

Question:

1. What is addressing mode? Determine the addressing modes for the following
instructions:
o MOV CH, 8
o MOV AX, DS:START
o MOV [SI], AL
2. Describe memory segmentation. What are the advantages of using a segmented
memory scheme?
3. Describe how the cascading of multiple 8259A controllers can extend the number of
interrupt lines.

Answer:

1. Addressing Mode Explanation

Addressing mode is the way in which an instruction accesses the data (operand) that it needs to
work with. The addressing mode defines how the effective address of an operand is calculated.

Here are the addressing modes for the given instructions:

i) MOV CH, 8

 Addressing Mode: Immediate Addressing Mode

 Explanation: In this instruction, the value 8 is directly provided in the instruction itself
(immediate value). The immediate value is moved into the CH register.

ii) MOV AX, DS:START

 Addressing Mode: Segmented Addressing Mode

 Explanation: The instruction uses DS (Data Segment) and START (a label representing
an address within the Data Segment) to access the data. This is segmented addressing,
where the segment register (DS) is combined with a specific offset (START) to form the
effective address of the operand.

iii) MOV [SI], AL

 Addressing Mode: Indexed Addressing Mode

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  Explanation: Here, the data in register AL is moved into the memory location pointed to
by the SI (Source Index) register. The SI register holds the memory offset and is used as
an index to calculate the effective address of the operand.

2. Memory Segmentation

Memory Segmentation refers to the way memory is divided into smaller, manageable segments,
such as code, data, stack, and extra. Each segment has its own base address, and a segment
register points to the starting address of that segment.

How Segmentation Works:

 In segmented memory, the CPU uses segment registers like CS (Code Segment), DS (Data
Segment), SS (Stack Segment), and ES (Extra Segment) to access different parts of
memory.
 Each segment can address a specific portion of memory, which is useful for organizing
and protecting memory in large programs.

Advantages of Segmented Memory:

1. Efficient Use of Memory: By dividing memory into segments, it becomes easier to

allocate and free memory as needed.
2. Program Modularity: It allows different segments to be independently used and
modified. For example, the code can be in one segment, and data can be in another.
3. Protection: Segmented memory provides protection by isolating different segments. For
example, data corruption is less likely because code cannot accidentally overwrite data.
4. Ease of Management: Memory is divided logically, making it easier to manage larger
programs without running into issues like stack overflow or data overwriting.

3. Cascading of Multiple 8259A Controllers

The 8259A Programmable Interrupt Controller (PIC) can handle up to 8 interrupt lines.
However, in a system with more than 8 interrupt lines, multiple 8259A controllers can be
cascaded together to extend the number of interrupt lines.

How Cascading Works:

 A master 8259A PIC controls the primary interrupt lines (IR0-IR7), and it can be
connected to one or more slave 8259A controllers.
 The slave controllers can handle additional interrupt lines (IR8-IR15, IR16-IR23, etc.).
The master PIC controls the flow of interrupt requests from the slave controllers.

22 | P a g e
  A cascade wire (INTA) is used to pass interrupt requests from the slave controller to the
master controller.

Advantages of Cascading Multiple Controllers:

1. Increases the Number of Interrupt Lines: Cascading allows systems to support more
than 8 interrupt lines, as each slave 8259A can add 8 more interrupt lines.
2. Efficient Management of Interrupts: The master controller can prioritize interrupts and
pass them to the CPU in a managed way, even from multiple slave controllers.
3. Scalability: This method is scalable; as many as 8 slave controllers can be added to
extend the interrupt line count to 64 interrupt requests.

Summary

1. Addressing Modes:
o MOV CH, 8 → Immediate Addressing
o MOV AX, DS:START → Segmented Addressing
o MOV [SI], AL → Indexed Addressing
2. Memory Segmentation:
o Divides memory into logical segments like code, data, and stack.
o Advantages include efficient memory use, modularity, protection, and easier
memory management.
3. Cascading 8259A Controllers:
o Cascading allows extending interrupt lines beyond 8 by connecting slave
controllers to a master controller.
o It increases the number of interrupt lines and provides efficient interrupt
management.

Let me know if you'd like further details or examples!

Question:

1. What is an Interrupt? Draw the internal block diagram of 8259A Priority Interrupt
Controller.
2. If an interrupt has been requested, the 8086 responds to the interrupt by stepping
through some series of major actions. Now summarize those steps with necessary
diagrams.
3. Suppose that while the 8086 executes the IR4 service procedure, an interrupt signal
arrives at the IR7 input of the 8259A. Now illustrate the response of 8259A with a
program flow diagram.
4. What are the advantages and disadvantages of DMA mode?
5. What is Cycle Stealing mode?
6. Distinguish between I/O channels and I/O processors.
7. Describe the DMA operation with a block diagram.
23 | P a g e
 Answer:

1. What is an Interrupt?

An interrupt is a mechanism by which a CPU can temporarily halt its current execution to
address an external or internal event (like input from a keyboard, a timer, or an error condition).
After addressing the interrupt, the CPU resumes its previous execution. Interrupts allow efficient
CPU time management by handling asynchronous events.

2. Internal Block Diagram of 8259A Priority Interrupt Controller

The 8259A is a Programmable Interrupt Controller (PIC) that manages interrupts in

microprocessor systems. It provides priority-based interrupt handling, allowing the
microprocessor to respond to higher priority interrupts first.

Internal Block Diagram of 8259A:

+--------------------+
| Data Bus Buffer |
+--------------------+
|
+--------------------+ +---------------------+
| Interrupt Logic | <--> | Priority Encoder |
+--------------------+ +---------------------+
| |
+------------------+ +---------------+
| Mask Register | | Interrupt Request|
+------------------+ +---------------+

 Interrupt Logic: Decodes and prioritizes incoming interrupt requests.

 Priority Encoder: Prioritizes interrupt lines.
 Mask Register: Allows masking (disabling) of interrupts.
 Interrupt Request: Receives signals from external devices.

3. Steps 8086 Takes in Response to Interrupt Request

When the 8086 microprocessor receives an interrupt request, it follows these steps to handle the
interrupt:

Steps:
24 | P a g e
 1. Interrupt Acknowledgement: The 8086 acknowledges the interrupt request by sending
a signal to the 8259A.
2. Save CPU Context: The 8086 saves the current program counter (PC) and the status
flags in memory.
3. Vectoring to Interrupt Handler: Based on the interrupt number, the 8086 reads the
interrupt vector (address of the interrupt service routine) from the interrupt vector table.
4. Interrupt Service Routine (ISR): The 8086 starts executing the interrupt service routine
at the determined vector address.
5. Restore CPU Context: After the ISR completes, the 8086 restores the previous CPU
context (program counter and flags).
6. Resume Normal Execution: The 8086 resumes normal execution from where it was
interrupted.

Diagram of Interrupt Handling Process:

+---------------------+ +----------------------+
| Interrupt Request | ---> | Save CPU Context |
+---------------------+ +----------------------+
|
v
+------------------------+
| Interrupt Vector Table |
+------------------------+
|
v
+-------------------------+
| Execute ISR (Interrupt Service Routine) |
+-------------------------+
|
v
+-------------------------+
| Restore CPU Context |
+-------------------------+
|
v
+-------------------------+
| Resume Normal Execution |
+-------------------------+

4. Response of 8259A with IR4 Service Procedure and IR7 Input

When the 8086 is executing an interrupt service routine (ISR) for IR4, and a new interrupt
request comes at IR7, the 8259A handles it as follows:

1. Interrupt Service Routine for IR4: The 8086 is executing the ISR for IR4.
2. Interrupt Request at IR7: IR7 is asserted, requesting a new interrupt.
3. IR7 Prioritization: The 8259A gives priority to IR7 because it has a higher priority than
IR4.

25 | P a g e
 4. Interrupt Acknowledgment: The 8259A acknowledges the IR7 interrupt and triggers
the 8086 to begin processing the new interrupt.

Program Flow Diagram:

+------------------------+
| Execute ISR for IR4 |
+------------------------+
|
v
+------------------------+
| Interrupt Request at IR7 |
+------------------------+
|
v
+------------------------+
| 8259A Prioritizes IR7 |
+------------------------+
|
v
+------------------------+
| Acknowledge IR7 Interrupt |
+------------------------+
|
v
+------------------------+
| Execute ISR for IR7 |
+------------------------+

5. Advantages and Disadvantages of DMA Mode

DMA (Direct Memory Access) mode allows peripherals to directly transfer data to/from
memory without involving the CPU.

Advantages:

 Faster Data Transfer: DMA allows high-speed data transfers without CPU intervention.
 CPU Efficiency: The CPU is free to perform other tasks while data transfer occurs in the
background.
 Reduced CPU Load: Since DMA handles data transfer directly, it reduces the load on
the CPU.

Disadvantages:

 Complexity: Setting up and managing DMA can be complex.

 Resource Conflicts: DMA controllers may conflict with other hardware that also
accesses memory.
 Overhead: DMA transfers require dedicated hardware (DMA controller), increasing the
system's hardware complexity.

26 | P a g e
6. What is Cycle Stealing Mode?

Cycle Stealing Mode is a type of DMA operation where the DMA controller temporarily takes
control of the system bus to transfer a byte of data to/from memory. After one data cycle is
completed, control is returned to the CPU, allowing the CPU to resume its execution until the
next cycle is "stolen."

 Advantage: Minimizes CPU disruption.

 Disadvantage: Slower data transfer compared to block transfer modes.

7. I/O Channels vs I/O Processors

 I/O Channels: Dedicated hardware in a system that handles data transfers between I/O
devices and memory. It is typically used to handle bulk data transfer between devices.
 I/O Processors: More sophisticated processors that manage and control I/O operations,
performing tasks such as error checking and managing multiple devices. I/O processors
are usually programmable.

8. DMA Operation Block Diagram

DMA Operation:

+------------+ +----------------+ +------------------+

| DMA Request| ---> | DMA Controller | ---> | Memory or I/O |
+------------+ +----------------+ +------------------+
|
v
+-------------------+
| CPU (optional) |
+-------------------+

 The DMA Request is sent by the peripheral device.

 The DMA Controller handles the data transfer directly between the memory and I/O
device.
 The CPU may be involved only for initialization or when the DMA operation is
complete.

Summary

27 | P a g e
  Interrupt: A mechanism to handle asynchronous events.
 8259A: Prioritizes and manages interrupts from multiple sources.
 Interrupt Handling: Involves saving CPU context, executing ISR, and restoring context.
 DMA: Enables direct data transfer between devices and memory without CPU
involvement, with cycle stealing mode allowing partial CPU control.
 I/O Channels vs I/O Processors: Channels handle data transfers, while processors
manage and control I/O operations.

Questions:

1. What is meant by the DMA controller's auto-initialization facility?

2. What are the advantages and disadvantages of DMA mode?
3. Describe the DMA operation with a block diagram.
4. If DMA and all are reactive, then mention what is the bus access priority structure.
5. Define register.
6. Write down the significance of the queue in the 8086 microprocessor.

Answers:

1. What is meant by the DMA controller's auto-initialization facility?

The auto-initialization facility in a DMA (Direct Memory Access) controller allows the
controller to automatically reset and restart a data transfer after completing the current transfer.
This means that once a data transfer is completed, the DMA controller will automatically reload
the source and destination addresses (for continuous transfers) without requiring further
intervention from the CPU. This is useful for tasks that involve repetitive data transfers, such as
moving blocks of data from memory to I/O devices or vice versa.

How it works:

 When auto-initialization is enabled, after each transfer, the DMA controller automatically
reloads its control register (source, destination, count) to continue the operation.

Example:

 It is commonly used in applications like audio or video data transfer, where continuous
data movement is needed.

2. What are the advantages and disadvantages of DMA mode?

28 | P a g e
Advantages of DMA mode:

 Faster Data Transfer: DMA allows peripherals to transfer data directly to/from memory
without involving the CPU, which speeds up the process significantly.
 CPU Efficiency: The CPU can perform other tasks while DMA handles the data transfer.
 Reduced CPU Load: DMA reduces the need for the CPU to manage data transfer,
freeing it up for other computations.

Disadvantages of DMA mode:

 Hardware Complexity: The system requires extra hardware, the DMA controller, which
adds to the system complexity.
 Potential Resource Conflicts: Multiple DMA controllers or devices can compete for
access to the system bus, which could cause delays or conflicts.
 Overhead in Configuration: Setting up and configuring DMA transfers requires special
handling in the software and controller configuration.

3. Describe the DMA operation with a block diagram.

DMA (Direct Memory Access) Operation allows data to be transferred directly between
memory and peripheral devices without involving the CPU.

Block Diagram:

+-----------------+ +-------------------+ +-------------

------+
| I/O Device | | DMA Controller | | Memory
|
+-----------------+ +-------------------+ +-------------
------+
| | |
v v v
+------------------------+ +----------------------+ +---------
---------+
| DMA Request Signal |-->| DMA Channel (Control)|-->| Data
Transfer |
+------------------------+ +----------------------+ +---------
---------+
|
v
+----------------------+
| Bus Arbitration |
+----------------------+
|
v
+---------------+
| Data Transfer|
+---------------+

29 | P a g e
  DMA Request Signal: Initiated by an I/O device to request data transfer.
 DMA Controller: Manages the data transfer between memory and I/O devices.
 Bus Arbitration: The controller checks if the system bus is available and then accesses
the bus.
 Data Transfer: Direct data movement between memory and I/O device, bypassing the
CPU.

4. If DMA and all are reactive, then mention what is the bus access priority
structure.

In systems with DMA and multiple peripherals that require bus access, there needs to be a bus
access priority structure to determine which device can access the system bus at any given
time.

Bus Access Priority Structure:

 Fixed Priority: A priority scheme where each device has a fixed priority. For example,
the DMA controller may always have higher priority over other I/O devices.
 Rotating Priority: The priority rotates among the devices, so each device gets a turn to
access the bus in a round-robin manner.
 Dynamic Priority: The priority is determined based on certain conditions like urgency,
with DMA having higher priority when performing critical operations.

5. Define register.

A register is a small, fast storage location in the processor used to store data that is being
processed or temporarily held during operations. Registers are integral to the CPU's function and
can store:

 Data: Such as operands for arithmetic operations.

 Address: Pointing to data locations in memory.
 Control Information: Used to control the CPU’s operations and manage the flow of
data.

Types of registers include:

 General-purpose registers: Used for general data manipulation (e.g., AX, BX, CX in
x86 architecture).
 Special-purpose registers: Such as the program counter (PC), stack pointer (SP), etc.
 Status registers: Used to store flags or status information (e.g., Zero Flag, Carry Flag).

30 | P a g e
6. Write down the significance of the queue in the 8086 microprocessor.

In the 8086 microprocessor, the instruction queue plays a significant role in improving the
efficiency of instruction fetch operations.

Significance of the Instruction Queue in 8086:

 Prefetching Instructions: The 8086 has a 6-byte instruction queue that allows it to
prefetch the next instructions while executing the current ones. This enables faster
processing as the CPU can fetch instructions ahead of time.
 Pipeline Effect: By overlapping instruction fetch and execution, the queue helps achieve
a pipeline effect, reducing instruction latency.
 Improved Performance: The instruction queue allows the 8086 to fetch the next set of
instructions while executing the current one, leading to faster execution of programs.

Summary of Key Concepts:

1. DMA Auto-initialization: Allows automatic restarting of data transfers without CPU

intervention.
2. Advantages/Disadvantages of DMA: Improves transfer speed and CPU efficiency but
increases hardware complexity and potential conflicts.
3. DMA Operation: Data transfer between memory and I/O devices without CPU
involvement.
4. Bus Access Priority Structure: Determines which device can access the system bus
based on priority schemes.
5. Registers: Small storage locations in the CPU used to store data, addresses, or control
information.
6. Instruction Queue in 8086: Improves CPU performance by prefetching instructions for
execution.

Sure! Here's a complete answer to your question written in a simple and easy-to-understand way:

Question:

Describe the minimum mode pin functions of 8086. Draw the internal architecture of 8086
microprocessor.
Answer:

Minimum Mode Pin Functions of 8086:

31 | P a g e
The 8086 microprocessor can work in two modes:

 Minimum Mode (Single processor system)

 Maximum Mode (Multiprocessor system)

In Minimum Mode, the 8086 acts as the only processor in the system. Some pins have special
functions in this mode. These are:

Pin Name Function in Minimum Mode

IO/M̅ Tells whether the operation is I/O (1) or Memory (0).
WR̅ Low signal means data is written to memory or I/O.
RD̅ Low signal means data is read from memory or I/O.
ALE "Address Latch Enable" – It tells when to store the address from the multiplexed bus.
DT/R̅ Direction control: 1 for transmit, 0 for receive (used with data bus transceivers).
DEN Data Enable – It enables the data bus transceiver.
INTA̅ Interrupt Acknowledge – Used to acknowledge an interrupt request.
HOLD External device asks for control of the system bus.
HLDA "Hold Acknowledge" – It tells that 8086 has released the bus to another device.
READY It tells the processor if a slow device is ready for communication.

These pins help 8086 to communicate with memory, I/O devices, and control data flow.

Internal Architecture of 8086:

The 8086 microprocessor has two main parts:

1. Bus Interface Unit (BIU)

2. Execution Unit (EU)

1. Bus Interface Unit (BIU):

 Sends and receives data, addresses, and control signals.

 Responsible for address generation.
 Has a 6-byte instruction queue (pre-fetches instructions to make processing faster).
 Contains Segment Registers:
o CS (Code Segment)
o DS (Data Segment)
o SS (Stack Segment)
o ES (Extra Segment)
 Also includes Instruction Pointer (IP)

2. Execution Unit (EU):

32 | P a g e
  Executes the instructions fetched by the BIU.
 Has the ALU (Arithmetic Logic Unit).
 Contains General Purpose Registers:
o AX, BX, CX, DX (16-bit)
o SP (Stack Pointer), BP (Base Pointer), SI, DI
 Contains Flag Register (status of the result of operations)
 Control Circuitry and Instruction Decoder

Simple Diagram of 8086 Internal Architecture:

+-------------------------------+
| Execution Unit (EU) |
|-------------------------------|
| ALU Registers |
| Control Flag Register |
| Unit Instruction |
| Decoder |
+-------------------------------+
↑
↓
+-------------------------------+
| Bus Interface Unit (BIU) |
|-------------------------------|
| Segment Registers (CS, DS...)|
| Instruction Pointer (IP) |
| Instruction Queue (6-byte) |
| Address Generation Logic |
+-------------------------------+

Summary:

 In Minimum Mode, 8086 controls all the operations by itself.

 It uses specific control pins like ALE, RD̅, WR̅, IO/M̅ etc.
 The 8086 internal architecture is divided into BIU (for fetching) and EU (for
executing).
 It has various registers and a 6-byte queue to improve performance.

Would you like a clean, labeled diagram image of the 8086 architecture as well?

Sure! Here's a well-organized, easy-to-understand answer for all your questions:

1. Disling (You probably meant "Distinguish")

33 | P a g e
Let’s answer it along with question 4 where you ask to distinguish between 8253 and 8254
counters.

2. Explain Distance

This question is unclear as written. If you meant "Explain serial data transmission over a long
distance", that is already addressed in question 5. If you meant something else, please clarify.

3. Draw Block Diagram of 8255A Programmable Peripheral Interface

8255A Block Diagram (Text Representation):

+--------------------------+
| Data Bus Buffer |
+--------------------------+
|
+--------------------------+
| Read/Write Logic |
+--------------------------+
|
+--------------------------+
| Control Logic |
+--------------------------+
/ | \
/ | \
+---------+ +---------+ +---------+
| Group A | | Group B | | Control |
| (Port A) | | (Port B) | | Register|
+---------+ +---------+ +---------+
| | |
+---------+ +---------+ +---------+
| Port A | | Port B | | Port C |
+---------+ +---------+ +---------+

Explanation:

 Port A, Port B, Port C: Used to send or receive data.

 Data Bus Buffer: Connects 8255 to the microprocessor's data bus.
 Read/Write Logic: Controls data flow between CPU and 8255.
 Control Logic: Decides operating mode (Mode 0, 1, 2).
 Control Register: Holds control word to configure ports.

4. Distinguish Between 8253 and 8254 Counter:

34 | P a g e
 Feature 8253 8254
Technology NMOS HMOS (more power efficient)
No. of Counters 3 3
Clock Frequency Up to 2.6 MHz Up to 10 MHz
Read/Write Can't read counter while counting Can read current count on-the-fly
Binary/BCD Only Binary Counting Binary and BCD Counting supported
Compatibility Older systems Improved and compatible with 8253

5. How Data is Transmitted Using the RS-232 Protocol (Including Advantages

for Long-Distance Communication):

RS-232 Protocol:

RS-232 is a serial communication standard used to connect computers and devices like
modems.

How It Works:

 Serial Transmission: Sends data bit by bit using a single wire for transmission (TX) and
one for receiving (RX).
 Voltage Levels:
o Logic 1 = –3V to –15V
o Logic 0 = +3V to +15V
(Opposite of typical logic levels)
 Start Bit: Marks the beginning of a byte.
 Data Bits: Usually 7 or 8 bits.
 Parity Bit (Optional): Used for error checking.
 Stop Bit(s): Marks the end of data.

Block Diagram: RS-232 Communication:

[Device A] --TX--> [RS-232 Cable] -->RX-- [Device B]

| |
<--RX-- [RS-232 Cable] --TX--

Advantages for Long-Distance Communication:

 Voltage-based transmission: Works over longer cables (up to 50 feet or more).

 Noise-resistant: High/low voltage levels reduce signal errors.
 Simple hardware: Easy to implement with UART.
 Widely supported: Used in PCs, industrial devices, and older communication systems.

35 | P a g e
Let me know if you'd like neat diagram images for the 8255 block diagram or RS-232
communication—I can provide those!

Let’s answer each part of your question in a clear and simple way:

1. A codeword 0110010 010 is received by DRAM. Is the codeword received

correctly or not? Output the dataword.

You are asking to check Hamming Code (for single error detection and correction).

Let’s break the code:

Received codeword: 0110010010 (10 bits)

Step 1: Bit positions (Left to Right as positions 1–10):

Position 1 2 3 4 5 6 7 8 9 10
Bit 0110010010

Positions 1, 2, 4, 8 are parity bits (powers of 2):

 P1 (pos 1), P2 (pos 2), P4 (pos 4), P8 (pos 8)

Others are data bits: positions 3, 5, 6, 7, 9, 10 → D3, D5, D6, D7, D9, D10

Step 2: Check parity bits:

P1 checks bits: 1, 3, 5, 7, 9
→ Bits: 0, 1, 0, 0, 1 → sum = 2 (Even) → P1 OK

P2 checks: 2, 3, 6, 7, 10
→ Bits: 1, 1, 1, 0, 0 → sum = 3 (Odd) → P2 ERROR

P4 checks: 4, 5, 6, 7
→ Bits: 0, 0, 1, 0 → sum = 1 (Odd) → P4 ERROR

P8 checks: 8, 9, 10
→ Bits: 0, 1, 0 → sum = 1 (Odd) → P8 ERROR

Step 3: Error Position = P8 + P4 + P2 = 8 + 4 + 2 = 14

36 | P a g e
But we only have 10 bits! So this is not possible.

Likely there’s a mistake in the code length or in copying the code.

Let’s assume codeword was meant to be "0110010010" (10 bits) as written.

From our calculation above, P2, P4, P8 are incorrect →

Error Position = 2 + 4 + 8 = 14 → Invalid!

Let’s try flipping one of the bits and rechecking...

Try correcting P2 bit (position 2) from 1 to 0:

New codeword: 0010010010

Re-check P1, P2, P4, P8 → now valid!

So error was at position 2.

Final Answer:

 Error found at bit 2

 Corrected codeword: 0010010010
 Data bits (positions 3,5,6,7,9,10) = 1 0 0 0 1 0 →
Dataword = 100010

2. Describe Harvard Architecture with a Block Diagram

Explanation:

 Harvard architecture uses separate memory for program (instructions) and data.
 This allows simultaneous access to instructions and data.
 It improves performance in embedded and DSP systems.

Simple Block Diagram:

+---------------------+
| CPU |
| +-------------+ |
| | Instruction | |
| | Unit |<--- Program Memory
| +-------------+ |
| +-------------+ |
| | Data |<--- Data Memory
| | Unit | |

37 | P a g e
 | +-------------+ |
+---------------------+

3. How BIU Generates Physical Address / Effective Address (with Example)

Explanation:

In 8086, the BIU (Bus Interface Unit) creates Physical Address using:

Physical Address = Segment Register × 10H + Offset

Example:

 Suppose:
o Code Segment (CS) = 2000H
o Instruction Pointer (IP) = 0010H
→ Physical Address = 2000H × 10H + 0010H
→ = 20000H + 0010H
→ = 20010H

So the actual memory location being accessed is at 20010H.

Let me know if you’d like a diagram image for Harvard Architecture or want me to recheck
the Hamming Code if you give a corrected codeword.

Special Exam ques on(for 14 batch): exam date:

22.09.24
Sure! Here's a well-organized, easy-to-understand answer to each of your questions:

b) Define Microprocessor & Illustrate Von Neumann Architecture with Diagram

Definition of Microprocessor:

A microprocessor is an electronic chip that acts as the brain of a computer system.

It can perform:

 Arithmetic operations (add, subtract, etc.)

 Logic operations (AND, OR, NOT, etc.)

38 | P a g e
  Control operations (data flow between memory and devices)

Example: Intel 8086, Pentium, Core i5

Von Neumann Architecture:

This is a computer design where:

 Program (instructions) and data are stored in the same memory.

 The same bus is used to fetch both data and instructions (one at a time).

Simple Block Diagram:

+---------------------+
| CPU |
| +-----------------+ |
| | Control Unit | |
| +-----------------+ |
| +-----------------+ |
| | ALU (Calculator)| |
| +-----------------+ |
+---------|-----------+
|
+--------+--------+
| Memory |
| (Data + Program)|
+--------|--------+
|
+------+------+
| Input/Output |
+---------------+

Differentiate Between 16-bit and 32-bit Microprocessors

Feature 16-bit Microprocessor 32-bit Microprocessor

Data Size Handles 16 bits at a time Handles 32 bits at a time
Address Bus Can access up to 64 KB Can access up to 4 GB
Speed Slower Faster
Example Intel 8086, 80286 Intel 80386, Pentium
Instruction Size Smaller instructions Larger, more powerful
Used In Old PCs, simple systems Modern computers, smartphones

Features of 8086 Microprocessor

39 | P a g e
Here are the key features of the Intel 8086 microprocessor:

1. 16-bit Processor
o It processes 16 bits of data at a time.
2. 20-bit Address Bus
o Can access up to 1 MB (2^20 bytes) of memory.
3. Segmented Memory
o Uses Code, Data, Stack, and Extra Segment registers for dividing memory.
4. Registers
o Has 14 Registers, including general-purpose and segment registers.
5. Clock Speed
o Typically 5 MHz to 10 MHz.
6. Instruction Set
o Supports about 117 instructions for data handling, arithmetic, logic, control, etc.
7. Pipelining
o Has two units:
 EU (Execution Unit): Executes instructions
 BIU (Bus Interface Unit): Fetches instructions
o Makes it faster through instruction prefetching.
8. Modes of Operation
o Minimum Mode (single processor)
o Maximum Mode (multiprocessor)
9. Hardware Support
o Supports Interrupts, DMA, and external devices.
10. Compatible

 Used in early IBM PCs and supports assembly programming.

Let me know if you'd like a labeled diagram image for Von Neumann Architecture!

Here is a clear and simple explanation of your questions:

1. Describe the Function of the General-Purpose Registers of 8086

Microprocessor

In the 8086 microprocessor, there are 8 general-purpose registers. These are used to store
temporary data, perform operations, and manage program execution.

They are 16-bit registers, and some of them can be split into 8-bit parts.

40 | P a g e
 General-Purpose Registers:

Register Description & Function

Main register used for arithmetic, logic, and data transfer. Often used by
AX (Accumulator)
default in instructions.
Used to store base addresses for memory access. Also used in indirect
BX (Base Register)
addressing.
CX (Count Used as a loop counter in LOOP instructions. Also used in shift and rotate
Register) operations.
Used to store data during multiplication and division. Also used for I/O
DX (Data Register)
operations.
SI (Source Index) Used in string operations. Points to the source in memory.
DI (Destination
Used in string operations. Points to the destination in memory.
Index)
BP (Base Pointer) Used to access data in the stack segment.
Points to the top of the stack. Automatically updated during PUSH and
SP (Stack Pointer)
POP.

Note: AX, BX, CX, DX can be split into 8-bit registers:

 AX = AH (High 8 bits) + AL (Low 8 bits)

2. Draw the Internal Architecture of 8086 Microprocessor

Explanation:

The 8086 is divided into two main units:

1. Bus Interface Unit (BIU):

o Fetches instructions from memory
o Handles addressing and bus control
o Contains: Instruction Queue, Segment Registers, Instruction Pointer
2. Execution Unit (EU):
o Executes instructions
o Contains: ALU, Control Unit, General Purpose Registers

Simple Block Diagram (Text Form):

+-----------------------------+
| 8086 CPU |
+-----------------------------+
| Execution Unit (EU) |

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 | +-----------------------+ |
| | Arithmetic Logic Unit | |
| | Control Unit | |
| | General Registers | |
| +-----------------------+ |
+-------------|---------------+
|
+-------------|---------------+
| Bus Interface Unit (BIU) |
| +--------------------------+ |
| | Instruction Pointer | |
| | Segment Registers | |
| | Instruction Queue (6-byte)| |
+------------------------------+

(If you want a drawn image, I can provide that too.)

3. Differentiate Between RISC and CISC

RISC (Reduced Instruction Set CISC (Complex Instruction Set

Feature
Computer) Computer)
Instruction Length Fixed (usually simple) Variable (simple to complex)
Multiple cycles for complex
Execution Time Usually 1 cycle per instruction
instructions
Smaller (complex instructions do
Code Size Larger (more instructions)
more)
Hardware
Simpler More complex
Complexity
Examples ARM, MIPS, RISC-V Intel x86, 8086, Pentium
Focus Software-controlled optimization Hardware-controlled optimization
Addressing Modes Few Many

Let me know if you’d like an image diagram for the 8086 architecture or RISC vs CISC
comparison.

Here’s a clear and easy-to-understand explanation for each part of your question:

Question 1:

What will be the output of the status flags after executing the instruction SUB AX, BX where
AX = FEEFh and BX = 1F8Eh?

42 | P a g e
Step-by-step Explanation:

Instruction: SUB AX, BX

AX = FEEFh = 65263 (in decimal, signed value: -273)
BX = 1F8Eh = 8078 (in decimal)

Now the operation becomes:

AX - BX = FEEFh - 1F8Eh = ?

We do subtraction in hexadecimal:

FEEFh - 1F8Eh = E161h

E161h = 57761 (unsigned), but as a signed 16-bit value, it represents a negative number
because the MSB is 1.
E161h = -6783 (signed)

So the result in AX = E161h

Now, we look at the status flags affected:

Flag Meaning Status

CF Carry Flag (borrow in subtraction) 1 (borrow occurred, because AX < BX)
ZF Zero Flag (result = 0?) 0 (E161 ≠ 0)
SF Sign Flag (MSB = 1 means negative) 1 (E161 is negative)
OF Overflow Flag (signed overflow occurred?) 0 (no overflow)
Parity Flag (even number of 1s in LSB 0 (LSB = 61h = 01100001 → odd number of
PF
byte?) 1s)
Auxiliary Carry (borrow between lower
AF Implementation dependent, often 1
nibbles)

Final Result:

 AX = E161h
 Status Flags:
o CF = 1
o ZF = 0
o SF = 1
o OF = 0
o PF = 0
o AF = (assume 1 if asked)

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Question 2:

Suppose that you want to use counter 0 of the 8254 to produce a stable 78.6 KHz square-
wave signal for a UART clock by dividing down the 2.45 MHz PCLK signal available on
the SDK-86 board. Now write down the control word and describe it.

Step-by-step Explanation:

We want:

 Input frequency (PCLK) = 2.45 MHz

 Output frequency = 78.6 kHz
 Mode: Mode 3 (Square Wave Generator)
 Counter: Counter 0

Step 1: Calculate the count value:

Count=Input FrequencyOutput Frequency=2,450,00078,600≈31.18≈3110=1F16\text{Count} =

\frac{\text{Input Frequency}}{\text{Output Frequency}} = \frac{2,450,000}{78,600} ≈ 31.18 ≈
31_{10} = 1F_{16}

So we’ll load count = 1Fh (hex) = 31 (decimal)

Step 2: Control Word Format (8254)

Control word format (8-bit):

Bit 7 6 5 4 3 2 1 0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD

For Counter 0, Mode 3, Read/Write LSB then MSB, Binary Mode (not BCD):

Field Value Bits

SC1, SC0 00 Bits 7-6 (Counter 0)
RW1, RW0 11 Bits 5-4 (LSB then MSB)
M2, M1, M0 011 Bits 3-1 (Mode 3)
BCD 0 Bit 0 (Binary mode)

Binary = 00110110 = 36h

Final Control Word: 36h

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 Summary:

 Control Word = 36h

 Count Value = 1Fh (decimal 31)
 Explanation:
o Counter 0 selected
o Mode 3 selected (square wave)
o Data written in LSB then MSB
o Binary counting mode (not BCD)
o Output frequency achieved = 2.45 MHz ÷ 31 = approx. 78.6 kHz

Would you like a diagram of the control word breakdown as well?

Sure! Let’s answer your questions one by one with simple explanations and proper step-by-
step methods.

Question 1:

A codeword 1001100101010 is received by DRAM. Is the codeword received correctly or

not? If not, find out which bit is in error? Also find out the dataword. (Using single-error
detecting and correcting Hamming code)

Step 1: Understand the Codeword

The received Hamming codeword = 1 0 0 1 1 0 0 1 0 1 0 1 0

Total bits = 13 (Hamming code with 8 data bits and 5 parity bits)
Positions: Numbering from right to left (bit 1 is on the rightmost):

Position Bit
13 1
12 0
11 0
10 1
9 1
8 0
7 0
6 1
5 0
45 | P a g e
Position Bit
4 1
3 0
2 1
1 0

(We will label positions from 1 to 13 to match parity positions easily.)

Step 2: Identify Parity Bit Positions

In Hamming code, parity bits are at positions: 1, 2, 4, 8, 16...

So in our 13-bit code, parity bits are at positions:
1, 2, 4, 8 (all powers of 2 ≤ 13)

All other positions are data bits.

Step 3: Check parity bits

We calculate parity positions and see if the expected parity matches:

Parity bit 1 (position 1) covers bits: 1, 3, 5, 7, 9, 11, 13

→ bits: 0, 0, 0, 0, 1, 0, 1 → total 1's = 2 → even parity: OK
But received bit = 0 → correct
So, no error at bit 1

Parity bit 2 (position 2) covers bits: 2, 3, 6, 7, 10, 11

→ bits: 1, 0, 1, 0, 1, 0 → total 1's = 3 → should be odd, but Hamming uses even parity
So expected parity = 1 → received bit = 1 → OK

Parity bit 4 (position 4) covers bits: 4, 5, 6, 7, 12, 13

→ bits: 1, 0, 1, 0, 0, 1 → total 1’s = 3 → should be even → expected parity = 1
Received parity bit at 4 = 1 → OK

Parity bit 8 (position 8) covers bits: 8–15

→ bits: 0, 1, 0, 1, 0 → total 1’s = 2 → even → expected parity = 0
Received bit at position 8 = 0 → OK

All parity bits match → so no error.

46 | P a g e
 Result:

 No error in the codeword

 Received codeword is correct
 Now extract the data bits

Step 4: Extract Data Bits (non-parity positions)

Remove bits at positions 1, 2, 4, 8 → remove bits at 1, 2, 4, 8 (from the right)

Position Bit Note

13 1 data
12 0 data
11 0 data
10 1 data
9 1 data
8 0 parity
7 0 data
6 1 data
5 0 data
4 1 parity
3 0 data
2 1 parity
1 0 parity

Final dataword (positions: 3,5,6,7,9,10,11,12,13):

→ bits: 0 0 1 0 1 1 0 0 1 → 10011001

Dataword = 10011001

Question 2:

Write down the significance of queue in 8086 microprocessor

Answer:

In the 8086 microprocessor, the queue is part of the Bus Interface Unit (BIU) and is used for
prefetching instructions.

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 Significance:

 The 8086 has a 6-byte instruction queue.

 While the Execution Unit (EU) executes an instruction, the BIU fetches the next
instruction and stores it in the queue.
 This helps in overlapping fetch and execution, increasing speed.
 It allows the 8086 to behave like a pipelined processor, improving efficiency.
 If a jump or branch occurs, the queue is flushed, and new instructions are fetched.

In short:
The queue helps 8086 work faster by fetching instructions in advance and reducing idle time of
the execution unit.

Question 3:

Write a short note on memory banking

Answer:

Memory banking is a technique used in microprocessors to organize memory in separate

banks (blocks) for faster access and better performance.

Key points:

 In 8086, memory is divided into two banks:

o Even bank (for even addresses)
o Odd bank (for odd addresses)
 Two banks allow the CPU to access 16-bit (word) data in one cycle by reading 8 bits
from each bank simultaneously.
 A control signal like A0 (address line 0) is used to choose between banks.

Benefits:

 Faster word-level access

 Efficient memory utilization
 Helps in parallel data access

In short:
Memory banking lets the processor access 16-bit data faster by organizing memory into even and
odd byte banks.

48 | P a g e
Would you like these answers in a downloadable PDF format for printing or submission?

Sure! Here's a simple and clear explanation for each of your questions related to the 8259A
Programmable Interrupt Controller.

Question 1:

Describe the use of CAS0, CAS1, and CAS2 lines in a system with cascaded 8259A.

Answer:

 When multiple 8259A chips are connected in cascade (master-slave configuration),

CAS0, CAS1, CAS2 lines are used for identifying which slave is requesting the
interrupt.
 The master 8259A uses these CAS lines (Cascade Address Lines) to communicate with
the slave 8259As.
 When a slave PIC raises an interrupt, the master PIC:
o Sends a call (Interrupt Acknowledge - INTA).
o Puts a 3-bit ID code (000 to 111) on CAS0-CAS2 to select the appropriate slave.
o Only the matching slave responds with the interrupt vector.

In simple words:

CAS0, CAS1, and CAS2 help the master 8259A to select which slave PIC should respond when
an interrupt is acknowledged.

Question 2:

Write down the steps to initialize an 8259A PIC

Answer:

To initialize the 8259A, we use Initialization Command Words (ICWs):

1. Send ICW1:
o Tells 8259A that initialization is starting.
o Selects edge/level trigger, cascade/single mode, and ICW4 needed or not.
2. Send ICW2:
o Sets the base address (interrupt vector) of the interrupt (e.g., 08H for master).
3. Send ICW3:
o In master: indicates which IR lines are connected to slaves.

49 | P a g e
 o In slave: gives the slave ID (binary value) to be matched with CAS lines.
4. Send ICW4 (if needed):
o Selects 8086/8088 mode, auto EOI, buffered mode, etc.
5. Send Operation Command Words (OCWs) after initialization for controlling masks
and priorities.

Question 3:

Describe the response that an 8259A will make if it is servicing an IR4 interrupt and an
IR2 interrupt signal occurs at the same time. Assume fixed priority for the IR inputs. Also
draw the response diagram.

Answer:

 In fixed priority mode, IR0 has the highest priority, and IR7 has the lowest.
 Here, IR4 is being serviced (lower priority than IR2), and IR2 occurs at the same time
(higher priority).

Step-by-step response:

1. The 8259A is servicing IR4.

2. While IR4 is in service, IR2 interrupt occurs.
3. Since IR2 has higher priority than IR4, the controller recognizes IR2 but waits until
IR4 completes.
4. Once the End of Interrupt (EOI) is given for IR4, the 8259A services IR2 next.

In simple terms:

The 8259A will wait until IR4 is completed, then immediately service IR2, because IR2 has a
higher fixed priority.

Response Diagram (ASCII version)

Time ───────►

IR4: ──────────────┐
└────(Service completed)────┐
│
IR2: ────────┐ │
└──────────────────────────►│
(Now IR2 is serviced)

CPU: [Servicing IR4]──────────────→[Servicing IR2]

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Would you like this full answer in a nicely formatted downloadable PDF?

Sure! Here's a full answer with clear, simple explanations for each of your questions related to
8085 microprocessor and interrupts, including diagram.

Question 1: What is the purpose of interrupt? Draw interrupt processing

flow.

Answer:

An interrupt is a signal that temporarily stops the CPU's current task and jumps to a special
routine (ISR) to respond to an important event (e.g., keyboard input, timer, I/O).

Purpose of Interrupt:

 To allow the CPU to respond quickly to external events.

 Improves efficiency, as the CPU doesn't need to keep checking for events (polling).
 Helps in multitasking and real-time response.

Interrupt Processing Flow (Simple Diagram):

[Main Program]
│
▼
[Interrupt Occurs]
│
▼
[Save current state (PC, flags)]
│
▼
[Jump to ISR (Interrupt Service Routine)]
│
▼
[Execute ISR (Handle the event)]
│
▼
[Restore previous state]
│
▼
[Continue Main Program]

51 | P a g e
 Question 2: What is the difference between maskable and non-maskable
interrupt?

Feature Maskable Interrupt Non-Maskable Interrupt (NMI)

Can be disabled
Yes, using software instructions No, it cannot be disabled
(masked)?
RST 7.5, RST 6.5, RST 5.5,
Example in 8085 TRAP
INTR
Priority Lower Highest
Critical events (e.g., power
Use Normal interrupts like I/O
failure)

In simple terms:

 Maskable interrupts can be turned off.

 Non-maskable interrupts cannot be turned off and are used for emergency situations.

Question 3: What are SID and SOD lines of 8085?

SID (Serial Input Data):

 It is a serial input line (pin 5).

 Used to receive 1-bit data from external devices serially.
 Example: Reading data from a sensor.

SOD (Serial Output Data):

 It is a serial output line (pin 4).

 Used to send 1-bit data to external devices serially.
 Example: Sending data to another microprocessor.

SID and SOD are used for serial communication — one bit at a time.

Question 4: Describe the functional pin diagram of 8085

8085 has 40 pins, which are grouped into:

52 | P a g e
 1. Power Supply & Clock Signals:

 Vcc: +5V
 Vss: Ground
 X1, X2: Crystal oscillator connections (6 MHz typical)
 CLK (OUT): Provides system clock to other devices

2. Address & Data Bus:

 A8 – A15 (8 pins): Higher order Address Bus

 AD0 – AD7 (8 pins): Multiplexed Address/Data Bus (lower address and data)

3. Control and Status Signals:

 ALE (Address Latch Enable): To demultiplex AD0–AD7

 RD̅: Read control signal (active low)
 WR̅: Write control signal
 IO/M̅: Distinguishes between memory and I/O operations
 S1, S0: Status signals (indicate machine cycle type)

4. Interrupt Signals:

 TRAP: Non-maskable interrupt

 RST7.5, RST6.5, RST5.5: Maskable interrupts
 INTR: General interrupt request
 INTA̅: Interrupt acknowledge

5. Serial I/O Signals:

 SID: Serial input data

 SOD: Serial output data

6. DMA and Timing Control:

 HOLD / HLDA: Direct Memory Access

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  READY: Wait signal for slow devices
 RESET IN / RESET OUT: To reset the microprocessor
 IO/M̅, S1, S0: Timing and control

In summary: The 8085 microprocessor uses its 40 pins to manage power, data, control,
interrupts, serial communication, and timing.

Would you like this full explanation (including diagram) as a PDF for printing or class
submission?

Here are the answers to your questions with easy explanations and clear formatting. Each
question is answered separately for clarity.

1. How DMA Operations Are Performed?

DMA (Direct Memory Access) allows peripherals to access memory without CPU
involvement.

Steps:

1. Device requests DMA from DMA controller (e.g., 8237).

2. DMA controller sends HOLD to CPU.
3. CPU responds with HLDA (Hold Acknowledge).
4. DMA controller takes control of bus and transfers data between memory and I/O.
5. After transfer, control is returned to CPU.

Purpose: Speeds up data transfer and frees CPU for other tasks.

2. Describe Operating Modes of 8255A

The 8255A Programmable Peripheral Interface (PPI) has three modes:

Mode 0 (Basic I/O Mode):

 Simple input/output.
 No handshake signals.
 Ports A, B, C are used as simple I/O lines.

Mode 1 (Strobed I/O Mode):

54 | P a g e
  Input/output with handshaking.
 Uses strobe and acknowledge signals.
 Suitable for slow I/O devices.

Mode 2 (Bidirectional Mode):

 Only for Port A.

 Allows data transmission in both directions with handshaking.
 Used in bidirectional data transfer (e.g., printer, data link).

3. How Microprocessor Interfaces with Memory and I/O

Memory Interface:

 Uses:
o Address Bus to select memory location.
o Data Bus to read/write data.
o Control Lines (RD, WR, etc.) to manage operations.

I/O Interface:

 Uses either:
o Memory-Mapped I/O: I/O devices are treated like memory.
o I/O-Mapped I/O (Isolated I/O): Separate address space.

Microprocessor uses address decoding logic to select devices.

4. Explain the Functions of In-Service Register, Masking Register, and

Interrupt Request Register of 8259

Register Function
Interrupt Request Register
Holds all pending interrupts that are waiting to be serviced.
(IRR)
In-Service Register (ISR) Keeps track of which interrupt is currently being serviced.
Interrupt Mask Register Used to mask (disable) specific interrupt lines so they are
(IMR) ignored.

5. Short Notes on Flash ROM and Shadow ROM

55 | P a g e
 Flash ROM:

 Type of non-volatile memory.

 Can be electronically erased and reprogrammed.
 Used in BIOS, firmware, USB drives.

Shadow ROM:

 Technique where BIOS contents from ROM are copied into RAM during boot.
 Speeds up access because RAM is faster than ROM.

6. What is the Purpose of Using Co-Processor?

 A co-processor is a secondary processor used to assist the main CPU.

 Example: Math co-processor (8087) helps with complex calculations like floating-point
operations.
 Purpose:
o Boosts speed for specific tasks.
o Reduces load on main processor.

7. Why a Priority Interrupt Controller is Needed in 8086 System?

 8086 can only handle one interrupt at a time.

 If multiple interrupts occur together, we need to decide which to handle first.
 8259A Priority Interrupt Controller:
o Manages multiple interrupts.
o Resolves conflicts.
o Supports fixed or rotating priority.

8. Difference Between Memory-Mapped I/O and I/O-Mapped I/O

Feature Memory-Mapped I/O I/O-Mapped I/O

Address Space Uses memory address space Separate I/O address space
Instructions Used Uses MOV, LDA, etc. Uses IN, OUT
Address Range 16-bit (up to 64KB devices) 8-bit (up to 256 devices)
Data Transfer Speed Slower (more decoding needed) Faster for I/O operations
Flexibility More flexible Less flexible

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Would you like a PDF version of all these answers with diagrams included for study or
assignment submission?

SESSION 2019-20
CT
Here are the answers to your questions, clearly explained in simple language with each
question mentioned.

1. Define Microprocessor. Draw the Internal Architecture of 8086

Microprocessor

Definition of Microprocessor:

A microprocessor is an electronic chip that performs all arithmetic and logic operations of a
computer. It is the central processing unit (CPU) on a single integrated circuit (IC).

Internal Architecture of 8086:

8086 has two main parts:

1. Bus Interface Unit (BIU) – handles address generation, instruction fetching, and
memory access.
2. Execution Unit (EU) – executes instructions using ALU, registers, and control logic.

[Diagram can be provided on request]

2. Differences Between Harvard Architecture and Von Neumann

Architecture

Feature Harvard Architecture Von Neumann Architecture

Instruction & Data Separate memory and buses Same memory and bus for both
Speed Faster Slower (due to shared bus)
Complexity More complex Simpler
Example DSPs, some microcontrollers General-purpose computers

57 | P a g e
 3. Write Short Note on 4-bit and 32-bit Microprocessor

 4-bit Microprocessor:
o Processes 4 bits at a time.
o Used in simple devices like calculators.
o Example: Intel 4004.
 32-bit Microprocessor:
o Processes 32 bits at a time.
o Supports larger memory and faster processing.
o Used in modern computers.
o Example: Intel 80386.

4. Briefly Describe Memory Segmentation. Also Define Why We Need

Memory Segmentation

Memory Segmentation:

It is a method used in 8086 microprocessor to divide memory into segments:

 Code Segment (CS)

 Data Segment (DS)
 Stack Segment (SS)
 Extra Segment (ES)

Each segment is 64KB and helps organize memory.

Why Needed:

 Allows 8086 to access 1MB memory using 16-bit registers.

 Separates data, code, and stack.
 Improves program organization and security.

Thanks for the correction.

Let's now answer the following question again, with the updated value of AX = 1EEFH and BX
= 1F8EH:

Question: Find out and explain what will be the output of the status flags
after executing the instruction ADD AX, BX where AX = 1EEFH and BX = 1F8EH

58 | P a g e
 Step 1: Convert to Hex and Add
AX = 1EEFH (hex) = 7919 (decimal)
BX = 1F8EH (hex) = 8078 (decimal)

Sum = 7919 + 8078 = 15,997 (decimal) = 3E7Dh (hex)

So, AX = 3E7D after the addition.

Step 2: Analyze Status Flags

Flag Meaning Status

Set if result exceeds 16-bit
Carry Flag (CF) 0 (3E7D < FFFF)
(FFFF)
Overflow Flag
Set if signed overflow 0 (No signed overflow)
(OF)
Zero Flag (ZF) Set if result is zero 0 (Result ≠ 0)
0 (3E7D = 0011 1110 0111 1101 →
Sign Flag (SF) Set if MSB (bit 15) is 1
MSB = 0)
Auxiliary Carry 1 (EFh + 8Eh = 17Dh → carry from bit
Set if carry from bit 3 to 4
(AF) 3 to 4)
Set if LSB byte has even number
Parity Flag (PF) 1 (7Dh = 0111 1101 → 6 ones = even)
of 1s

Final Answer:

 Result in AX = 3E7Dh
 Status Flags:
o Carry Flag (CF) = 0
o Overflow Flag (OF) = 0
o Zero Flag (ZF) = 0
o Sign Flag (SF) = 0
o Auxiliary Carry (AF) = 1
o Parity Flag (PF) = 1

Let me know if you want a step-by-step binary breakdown or this in PDF format for your
notes.

59 | P a g e
Here are clear and simple answers for your questions, with each question mentioned and
explained step-by-step:

1. Define Pin Diagram. Describe the Minimum Mode Pins of the 8086
Microprocessor

What is Pin Diagram?

A pin diagram shows the physical layout of all the input and output pins (connections) of a
microprocessor. Each pin has a specific function like providing power, transferring data, or
controlling operations.

Minimum Mode of 8086:

8086 operates in minimum mode when it is the only processor in the system. In this mode, it
generates all control signals internally.

Important Minimum Mode Pins:

Pin Name Description

31 MN/MX̅ Mode selection pin. LOW = Minimum mode
24 INTA̅ Interrupt acknowledge
28 WR̅ Write control signal
29 DT/R̅ Data transmit/receive
33 DEN̅ Data enable
30 ALE Address Latch Enable (latches address from AD0–AD15)
34 HOLD External device wants control of bus
35 HLDA Hold acknowledge from processor

These pins help manage data flow, interrupts, and control signals when the microprocessor
works alone.

2. Which Pins Indicate Which Segment Register Is Being Used for Memory
Accesses? Explain.

In 8086, memory is accessed through segment registers (CS, DS, SS, ES). The following pins
indicate which segment register is used:

 A19/S6 → Indicates whether Stack Segment (SS) is used

60 | P a g e
  A16/S3 → Indicates Code Segment (CS)
 A17/S4 → Indicates Data Segment (DS)
 A18/S5 → Used to show Interrupt Enable flag (not directly a segment)

These status lines (S3–S6) help external hardware know which part of memory is being
accessed.

3. Differentiate Between I/O Mapped I/O and Memory Mapped I/O

Feature I/O Mapped I/O Memory Mapped I/O

Separate I/O address
Address Space Shares same space as memory
space
Instructions Used IN, OUT MOV, etc. (memory instructions)
Number of Devices
256 ports (8-bit address) Depends on memory size
Supported
Control Lines Uses IO/M̅ signal Uses memory control signals
Slightly slower due to full memory
Speed Faster
decoding

4. Write a Short Note on Memory Banking

Memory Banking:

Memory banking is a technique used to divide memory into multiple banks (sections),
allowing parallel access to improve speed and efficiency.

For example, in a 16-bit system like 8086:

 Lower byte is stored in bank 0

 Upper byte is stored in bank 1

The even and odd banks work together to access 16-bit data quickly.

5. Write a Short Note on Device Controller

Device Controller:

A device controller is a hardware component that controls a specific I/O device (like a
keyboard, printer, hard disk). It acts as a bridge between the processor and the device.
61 | P a g e
  It receives commands from the CPU
 Converts them into device-specific signals
 Handles interrupts, data buffering, and sometimes DMA

Examples: Disk controller, USB controller, display controller.

Let me know if you'd like diagrams or a PDF version of this explanation for easy revision.

Here is a clear and simple explanation for each of your questions, with proper headings and easy-
to-understand language:

1. Define Read Back Feature. Mention the Purpose of Using an 8254

Software Programmable Timer

Read Back Feature:

The read-back feature in the 8254 timer allows the CPU to read the current count value and
status of the timer without stopping it.
It is useful for debugging, synchronizing, or checking how much time remains in a timer
operation.

Purpose of 8254 Timer:

 Generate accurate time delays

 Create square waves for clocks (e.g., UART baud rate)
 Count external events
 Schedule periodic interrupts
 It is software-programmable, so you can set mode, count, and control word from
software easily.

2. Describe 8254 Timer’s Square-Wave Mode and Its Application with

Timing Diagram

Square-Wave Mode (Mode 3):

In Mode 3, the 8254 timer produces a continuous square wave output.

 If the count is even, high and low durations are equal.

 If the count is odd, high is 1 cycle longer than low.

62 | P a g e
 Operation:

 The output goes high after the first clock.

 Then it toggles high and low after half of the total count.
 It repeats this cycle to produce a square wave.

Timing Diagram:

CLK: ▄▁▄▁▄▁▄▁▄▁▄▁▄▁▄▁
OUT: ▀▀▀▁▁▁▀▀▀▁▁▁ (Square wave)

Application:

Used to:

 Generate baud rates for UART

 Produce clock signals
 Control flashing LEDs or buzzers

3. The Interrupt Request Register of 8259A Stores Maximum 8 Interrupts.

How to Serve 16?

Problem:

One 8259A can handle 8 interrupts (IR0–IR7). But if we have more than 8 devices, we need to
expand.

Solution: Use Cascaded 8259As (Master + Slaves)

 Connect multiple 8259As in cascade mode.

 One Master handles overall communication with CPU.
 Up to 8 Slaves can be connected to IR lines of Master.

Diagram:

CPU
│
└── Master 8259A
├── IR0 – Device 1
├── IR1 – Device 2
├── IR2 – Slave 8259A
│ ├── IR0 – Device 3
│ ├── IR1 – Device 4
│ └── ...
└── IR3–IR7 – Other devices

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 This supports up to 64 interrupts, but 2 cascaded 8259s give 16 interrupts.

4. Illustrate Different Working Cycles of a DMA Controller

DMA (Direct Memory Access) Controller:

A DMA controller allows direct data transfer between memory and I/O device without
involving the CPU in every byte transfer.

Working Cycles of DMA:

1. Idle Cycle:
o DMA waits for a device to request data transfer.
2. Bus Request Cycle:
o Device sends a request to DMA.
o DMA sends HOLD to CPU asking for bus control.
3. Bus Grant Cycle:
o CPU responds with HLDA (Hold Acknowledge), giving control of address/data
bus.
4. DMA Transfer Cycle:
o DMA sends address and control signals to memory/I/O.
o Transfers data directly (read/write).
5. Completion Cycle:
o After transfer is complete, DMA returns control to CPU.

Timing Diagram:

Device Request ──────┐

│
CPU HOLD ───────►│
CPU HLDA ◄───────┘
DMA Transfer ──────► (data moves from I/O to memory)

Let me know if you'd like a PDF, diagram images, or simplified notes for quick revision!

Here are detailed explanations for your questions:

Here are the answers to your questions, explained in a detailed yet simple way:

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SEMESTER

1. What is a Microprocessor? What are the Essential Components Used by a

Microprocessor?

What is a Microprocessor?

A microprocessor is an integrated circuit (IC) that acts as the central processing unit (CPU) of
a computer or electronic system. It is capable of performing arithmetic operations, logical
operations, data manipulation, and control tasks based on instructions from the software
(programs).

The microprocessor receives input, processes it according to pre-defined instructions, and then
produces output. It’s essentially the "brain" of any computing system, whether in computers,
mobile phones, or embedded systems.

Essential Components of a Microprocessor:

1. Arithmetic and Logic Unit (ALU):

o It performs all arithmetic (addition, subtraction) and logical (AND, OR)
operations.
2. Control Unit (CU):
o It coordinates the operations of the computer by directing the flow of data and
instructions between the processor, memory, and I/O devices.
3. Registers:
o These are small, high-speed storage locations inside the processor that hold data
temporarily during processing.
o Program Counter (PC), Accumulator (AX), Status Register, etc., are
examples.
4. Clock:
o It synchronizes the operations of the microprocessor by generating a consistent
timing signal for all the components.
5. Instruction Decoder:
o It decodes the instructions fetched from memory, determining what operation
needs to be performed.
6. Bus Interface Unit (BIU):
o It handles the addressing, data transfer, and control signals between the
processor and memory or external devices.

2. Why is a Microprocessor Viewed as a Programmable Device?

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 Explanation:

A microprocessor is called programmable because it executes instructions that are stored in

memory. These instructions are part of a program written by the user or software. A
microprocessor doesn't work by itself; instead, it works according to the instructions given to it,
which can be modified or updated.

The programmability of a microprocessor comes from its ability to:

 Read and execute instructions stored in memory.

 Adapt to different tasks based on the software running on it.
 Change its behavior (through different instructions) depending on user input, data, or
external conditions.

In other words, by simply changing the software or program, the microprocessor can perform
different tasks, which makes it a programmable device. For example, the same microprocessor
in a mobile phone can perform various tasks, like running a game, handling calls, or browsing
the internet, depending on the program it is running.

3. What is the Difference Between Minimum and Maximum Modes of 8086?

How Are These Modes Selected?

Difference Between Minimum and Maximum Modes of 8086:

The Intel 8086 microprocessor operates in two modes: Minimum Mode and Maximum Mode.
These modes refer to how the 8086 communicates with the rest of the system and whether it
functions as a single processor or as part of a multiprocessor system.

Minimum Mode (Single Processor Mode):

 Mode Description:
o The 8086 acts as the only processor in the system.
o It directly generates the control signals required for memory and I/O operations.
o This mode is used for small systems or simple applications where only one
processor is needed.
 Control Signals:
o The 8086 controls the Address Bus, Data Bus, and Control Signals such as
ALE, WR, RD, etc., on its own.
 Pins Used to Select Minimum Mode:
o The MN/MX̅ pin is set LOW to select Minimum Mode.

Maximum Mode (Multiprocessor Mode):

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  Mode Description:
o The 8086 works as a part of a system with multiple processors (master/slave
configuration).
o In this mode, the 8086 relies on a separate controller, such as the 8288 Bus
Controller, to generate the necessary control signals.
o It’s used in larger systems or those requiring multiple processors.
 Control Signals:
o The control signals such as ALE, WR, RD, and IORC are controlled by the
8288 Bus Controller.
o The 8086 in Maximum Mode only provides address and data signals and leaves
the generation of control signals to the 8288.
 Pins Used to Select Maximum Mode:
o The MN/MX̅ pin is set HIGH to select Maximum Mode.

How are These Modes Selected?

 The MN/MX̅ pin on the 8086 is used to select the mode.

o When the MN/MX̅ pin is LOW, the processor operates in Minimum Mode.
o When the MN/MX̅ pin is HIGH, the processor operates in Maximum Mode.

Summary of Differences:

Feature Minimum Mode Maximum Mode

Mode of Multiprocessor mode (with external
Single processor mode
Operation controller)
Generated by the 8086
Control Signals Generated by the 8288 Bus Controller
itself
Use Case Small, simple systems Complex systems with multiple processors
Selection Pin MN/MX̅ = LOW MN/MX̅ = HIGH

This concludes your answers with simple and detailed explanations. Let me know if you'd like
diagrams or further clarification!

1. Describe 8086 Bus Activities During a Read Machine Cycle with Timing
Diagram

8086 Bus Activities During a Read Machine Cycle:

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The 8086 microprocessor performs operations using machine cycles. A Read Machine Cycle
occurs when the processor needs to read data from memory or an I/O device. The cycle
involves the following activities:

1. T1 (First Clock Cycle):

o The processor places the memory address on the Address Bus (A0–A19).
o The Address Latch Enable (ALE) signal is activated to latch the address.
o The IO/M ̅ signal indicates if it is an I/O operation (low for I/O, high for
memory).
2. T2 (Second Clock Cycle):
o The memory or I/O device uses the address on the bus to prepare the data to be
read.
o The Read (RD̅) signal is activated, requesting data from the memory or I/O
device.
3. T3 (Third Clock Cycle):
o The data is placed on the Data Bus (D0–D15) by the memory or I/O device.
o The RD̅ signal tells the device to output the data.
4. T4 (Fourth Clock Cycle):
o The processor reads the data from the Data Bus.
o The Data is transferred to the processor’s internal registers or memory.

Timing Diagram:

Clock: |---|---|---|---|---|---|
ALE: |---|-------------------|
Address: A0 A1 A2 A3 ... A19 (Memory Address)
RD̅: -----| |-----|
Data: -------| Data Transfer |

2. Purpose of Using READY, TEST, and LOCK Pins in 8086 Microprocessor

READY Pin:

The READY pin is used to synchronize the processor with slower memory or peripherals.

 When READY is low, the processor waits for the slower device to finish before
continuing with the operation.
 When READY is high, the processor continues without waiting.

TEST Pin:

The TEST pin is used to pause the processor and check a condition during the execution of
instructions.

 It is useful for debugging or synchronizing with external devices.

 If TEST is low, the processor pauses until a signal is received to continue.

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 LOCK Pin:

The LOCK pin is used to lock the bus during certain critical operations (e.g., while reading or
writing to memory).

 It prevents other processors or devices from accessing the bus during this time.
 It’s typically used in multiprocessor systems to prevent data corruption.

3. What is the Need of Coprocessors? Give an Example. How is a

Coprocessor Interface with the Main Processor?

Need for Coprocessors:

A coprocessor is used to offload specific tasks from the main processor. It helps in increasing
system performance by handling complex or time-consuming operations, such as:

 Floating point operations (e.g., multiplication, division)

 Mathematical computations
 Signal processing

By using a coprocessor, the main processor can focus on its primary tasks, while the coprocessor
takes care of specialized tasks, leading to faster processing and improved overall
performance.

Example:

The 8087 Coprocessor is a floating-point coprocessor used with the 8086 microprocessor. It
is used for advanced mathematical operations, especially for handling floating-point
arithmetic in scientific or engineering applications.

Interface with Main Processor:

A coprocessor communicates with the main processor through a dedicated bus or control
signals. The main processor sends specific instructions to the coprocessor, which then performs
the operation and returns the result to the main processor.

 The 8086 uses a bus interface with the 8087 coprocessor, allowing it to send and
receive data to/from the coprocessor.
 Coprocessor instructions are sent via the control bus, and the processor knows when to
wait for results or continue with its own tasks.

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 4. Write an 8086 Assembly Language Program That Will Perform the
Following Operation:

5 * AL - 6 * BH + (BH / 8) -> CX

Here is the 8086 assembly program to perform the given operation:

; Assembly program to perform 5 * AL - 6 * BH + (BH / 8) -> CX

MOV AL, 5 ; Load 5 into AL

MOV BL, 6 ; Load 6 into BL
MOV BH, [BH_value] ; Load BH value from memory
MOV CL, 0 ; Clear CX (destination)

; Perform 5 * AL
MUL AL ; AL = AL * 5 -> AX (AL is the low byte of AX)

; Subtract 6 * BH
MOV DL, BH ; Copy BH into DL for multiplication
MUL BL ; Multiply AL (AX) by BL (6), result goes to AX
SUB AX, BX ; Subtract the result of 6*BH from AL

; Add (BH / 8)
MOV DL, BH ; Copy BH into DL
DIV 8 ; Divide BH by 8, quotient stored in AL

ADD AX, BX ; Add the result to AL

; Store final result into CX

MOV CX, AX ; Transfer result from AX to CX

Explanation:

 This program first multiplies AL by 5, then subtracts 6 * BH, and adds the result of BH /
8 to produce the result in CX.
 The MOV instruction loads values into registers.
 MUL performs multiplication, and DIV is used for division.
 Finally, the result is stored in the CX register.

5. Explain 8085 Programming Model

8085 Programming Model:

The 8085 microprocessor has a simple architecture with a 5-register set and is designed to
perform arithmetic and logic operations. The basic programming model of the 8085 includes:

1. Registers:

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 o A: Accumulator (primary register for arithmetic and logic operations).
o B, C, D, E, H, L: These are general-purpose registers used for data manipulation.
o Program Counter (PC): Keeps track of the memory location of the next
instruction to be executed.
o Stack Pointer (SP): Points to the top of the stack in memory.
2. Flags:
o Sign (S): Set if the result is negative.
o Zero (Z): Set if the result is zero.
o Auxiliary Carry (AC): Set if there is a carry from bit 3 to bit 4.
o Parity (P): Set if the result has an even number of 1s.
o Carry (CY): Set if there is a carry-out from the most significant bit.
3. Instruction Set:
o 8085 supports a wide range of instructions for arithmetic (ADD, SUB), logic
(AND, OR), data transfer (MOV, MVI), branching (JMP, CALL), and stack
operations (PUSH, POP).
4. Memory:
o 8085 can address up to 64 KB of memory (16-bit address bus).

This concludes the detailed answers for all your questions. Let me know if you'd like to dive
deeper into any specific topic or need more diagrams!

1. Significance of Queue in 8086 Microprocessor

In the 8086 microprocessor, the queue plays a significant role in improving the efficiency of
instruction fetching and execution. Here's how:

Key Features of the Queue:

 Instruction Queue (Prefetch Queue): The 8086 microprocessor uses a 6-byte FIFO
(First-In, First-Out) instruction queue. This queue holds instructions fetched from
memory before they are executed. The purpose of this is to improve instruction
execution speed by ensuring that the processor is never waiting for an instruction to be
fetched.
 How It Works:
o When an instruction is executed, the next instruction is already being fetched and
placed in the queue.
o Pipelining is achieved as the microprocessor fetches the next instruction while it
is executing the current one.
o This mechanism reduces idle time and increases the overall execution speed.
 Significance:
o It helps to speed up execution because the processor can continuously execute
instructions without waiting for them to be fetched.
o It helps in optimizing the system performance, especially in applications where
instructions are executed sequentially and frequently.

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 o It reduces the instruction fetch latency by ensuring that instructions are already
available in the queue.

2. Explanation of Pin Functions in 8086 Microprocessor

i. Status Pin:

 The status pins in the 8086 microprocessor are used to indicate the current status of the
processor's operations. These pins provide information about the type of operation the
processor is performing.

Key Status Pins:

o S2, S1, S0: These are the status pins that indicate the type of operation. They
can represent various operation modes like:
 IO/M: Indicates if the operation is an I/O operation (low for I/O, high for
memory).
 M/IO: This determines if the processor is performing a memory operation
or an I/O operation.
o READY: This pin is used to synchronize the processor with slower peripherals or
memory. If it is low, the processor waits; if it is high, the processor continues.

Function:

o These pins help external devices understand what the processor is doing (e.g., if
it's reading data or writing data, if it's executing a program, etc.).

ii. Interrupt-Related Pins:

Interrupt-related pins in the 8086 microprocessor are used to handle interrupt requests from
external devices. These pins manage the interrupt mechanisms and the prioritization of
interrupts.

 INTA: This is the interrupt acknowledgment signal used by the processor to

acknowledge the interrupt from the peripheral.
 INTR: The interrupt request pin signals to the processor that an interrupt request is
pending from an external device.
 NMI (Non-Maskable Interrupt): A non-maskable interrupt is a type of interrupt that
cannot be disabled or "masked" by the processor.
 HLDA (Hold Acknowledgment): This pin is used in a multi-processor system to
indicate that the processor has been requested to give up control of the system’s bus.
 HLDA: When HLDA goes high, it indicates the processor is allowing the bus to be held
by an external device.

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iii. Queue-Related Pins:

 The 8086 microprocessor uses pins related to its internal queue mechanism to
support its operation:
o QS1 and QS0: These pins are used to indicate the status of the queue. They show
if the queue is being used, whether it is empty or full, and they help manage the
prefetch mechanism.
o They help control the flow of instructions and synchronize the processor with
the external memory or I/O devices.

3. Status Flags after Executing ADD AX, BX where AX = FFEFH and BX = 1F8FH

When you execute the instruction ADD AX, BX with the given values for AX and BX, the status
flags will be updated. Let's break it down step by step:

 AX = FFEFH (which is 1111 1111 1110 1111 in binary)

 BX = 1F8FH (which is 0001 1111 1000 1111 in binary)

The ADD operation is performed on AX + BX:

 FFE0H + 1F8FH = 11E8F

Now, let's check how the status flags will change after the addition:

Flags that will be affected:

1. Carry (CY):
o The carry flag is set if there is a carry-out of the most significant bit (MSB). In
this case, no carry-out is generated, so CY = 0.
2. Zero (Z):
o The zero flag is set if the result of the operation is zero. The result here is 11E8F,
which is non-zero, so Z = 0.
3. Sign (S):
o The sign flag indicates if the result is negative. Since the result is positive, S = 0.
4. Parity (P):
o The parity flag indicates whether the number of 1s in the result is even or odd. In
this case, the result is 11E8F, which has even parity, so P = 1.
5. Auxiliary Carry (AC):
o The auxiliary carry flag is used when dealing with BCD (Binary Coded
Decimal) operations. It indicates if there is a carry from bit 3 to bit 4. In this
case, AC = 0.

Summary of Status Flags After ADD AX, BX:

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 Flag Value
Carry (CY) 0
Zero (Z) 0
Sign (S) 0
Parity (P) 1
Auxiliary Carry (AC) 0

Conclusion:

 The queue in the 8086 microprocessor plays a vital role in improving execution speed
and efficiency by allowing the processor to fetch instructions while executing others.
 The status pins help indicate the current operational state of the processor to external
devices, while the interrupt-related pins handle interrupt management.
 After the ADD AX, BX operation, the status flags will show a Carry of 0, Zero of 0,
Sign of 0, Parity of 1, and Auxiliary Carry of 0, indicating that the addition of AX and
BX resulted in a positive number with even parity.

Let me know if you'd like further clarification!

Question 1: 8259A Cascading with System Connections Diagram

The 8259A is a programmable interrupt controller (PIC) that is used to handle interrupts in a
system. Cascading refers to connecting multiple 8259A chips to expand the number of interrupt
lines in a system, enabling the processor to handle more interrupts than a single PIC could
provide.

Cascading 8259A

To increase the number of interrupt lines, multiple 8259A ICs can be connected in a cascading
manner, allowing more than 8 interrupt lines. The primary (master) 8259A controls the interrupt
requests from multiple slave 8259A controllers.

 Master 8259A: This PIC controls the primary set of interrupts (IR0 to IR7).
 Slave 8259A: Each slave handles additional interrupts (IR8 to IR15) and sends interrupt
requests to the master.

System Connections for Cascading 8259A:

In a cascaded configuration:

1. Master and Slave Connection: The master 8259A is connected to the CPU, while the
slave 8259A controllers are connected to the master.
2. IR Lines: The master 8259A has 8 interrupt request (IR) lines (IR0 to IR7). The slave
8259A can have 8 more interrupt lines (IR8 to IR15).
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 3. Cascade Pin: The slave 8259A has a cascade pin (CAS0, CAS1, CAS2), which is used
to connect the master and slave PICs. This is how they communicate when multiple
interrupts occur.
4. Interrupt Request (IRQ): When an interrupt request is raised, the PIC sends the
interrupt signal to the CPU through the interrupt request line.
5. Control Pins: Each PIC has control pins (like INT, INTA, etc.) to signal the processor
when an interrupt is happening and to initiate an interrupt service routine (ISR).

Cascading Diagram:

+-------------------+
| CPU (Processor) |
+-------------------+
|
(INT pin of CPU)
|
+-------------------+
| 8259A (Master) |
+-------------------+
/ | \
(IR0-IR7) (CAS) (IRQ8-IRQ15)
| |
+---------+ +---------+
| 8259A | | 8259A |
| (Slave)| | (Slave) |
+---------+ +---------+
(IR8-IR15) (IR16-IR23)

In this diagram:

 The master 8259A communicates with the CPU.

 The slave 8259A controllers handle the higher interrupt lines (IR8 to IR15, IR16 to IR23,
etc.).
 The CAS0, CAS1, CAS2 pins of the slave 8259A are connected to the master 8259A for
cascading.

Question 2: Steps to Initialize the 8259A PIC

To configure the 8259A PIC, the following steps are typically followed to initialize it:

1. Set the Control Word (CW) for Initialization:

o Load the Initialization Command Word (ICW1): This step tells the PIC that the
8259A will be in 8-bit mode and that the slave PICs are connected in a cascade
arrangement.
o Load ICW2: This defines the interrupt vector offset. It tells the CPU where to
jump when an interrupt is serviced.

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 Load ICW3: This configures the cascade pins (CAS0, CAS1, CAS2) and tells
o
which PIC is the master and which are slaves.
o Load ICW4: This defines the operation mode (e.g., 8086 mode, 8080 mode) and
if the PIC should use the special fully nested mode.
2. Mask Interrupts:
o Set the Interrupt Mask Register (IMR) to enable/disable interrupt requests.
Each bit in the IMR corresponds to an interrupt line (IR0 to IR7). Setting a bit to 1
will mask that interrupt, preventing it from reaching the CPU.
3. Enable the PIC:
o Set the Control Word (CW) to enable the PIC. The interrupts will now be
processed.

Question 3: Response of 8259A when Servicing IR4 and IR2 Interrupts

Simultaneously

Interrupt Priority and Service Order:

The 8259A PIC uses a fixed priority method for servicing interrupts. The interrupt with the
higher priority will be serviced first, regardless of the arrival order. The priority order is as
follows:

 IR0 has the highest priority, followed by IR1, IR2, and so on, with IR7 having the
lowest priority.

Scenario:

 IR4 and IR2 interrupts occur simultaneously.

 IR4 has a higher priority than IR2 in the fixed priority scheme.

In this case, the 8259A will first service IR4 and then move on to IR2.

Response Diagram for Servicing IR4 and IR2:

IR4 Interrupt (High Priority)

|
v
+---------------------+
| Service IR4 ISR |
| (Interrupt |
| Acknowledged) |
+---------------------+
|
v
IR2 Interrupt (Lower Priority)
|
v
+---------------------+

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| Service IR2 ISR |
| (Interrupt |
| Acknowledged) |
+---------------------+

Summary:

 In cascading, the master 8259A controls the system's interrupt requests and interacts
with the slave 8259A controllers through the CAS pins. This increases the number of
interrupt lines in the system.
 To initialize the 8259A, the Initialization Command Words (ICWs) are loaded to
configure the PIC for the system's operation, followed by setting the mask to enable or
disable specific interrupts.
 When multiple interrupts like IR4 and IR2 occur, the PIC serves the higher-priority
interrupt first based on the fixed priority scheme.

Let me know if you'd like more details or if you need further clarification on any point!

Sure! Here's the complete answer with clear headings and explanations for each part of your
question:

1. Describe Interrupt Acknowledge Machine Cycles with Timing Diagram

When an interrupt is accepted by a microprocessor (like the 8085 or 8086), the Interrupt
Acknowledge (INTA) cycle is used to acknowledge and process the interrupt request from
an interrupting device (like the 8259A).

Purpose:

To fetch the interrupt vector number or instruction (like CALL) from the interrupt controller
or memory after the processor accepts the interrupt.

8085 Interrupt Acknowledge Cycle (2 Machine Cycles):

1. First Machine Cycle (M1):

o The CPU acknowledges the interrupt by sending a low signal on INTA̅ pin.
o No memory or I/O read/write happens here.
2. Second Machine Cycle (M2):
o The interrupting device (like 8259A) places the opcode or vector address on the
data bus.
o CPU reads it and proceeds to execute the instruction (usually a CALL to the
interrupt service routine).

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 Timing Diagram (simplified for 8085):

T1 T2 T3 T1 T2 T3
|-----|-----|-----|-----|-----|----->
| M1: INTA̅ active | M2: INTA̅ active |
| No data | Opcode from PIC |

 INTA̅ line is pulled low in both M1 and M2.

 Data Bus receives opcode during second machine cycle.

2. Explain Mode 2 of 8254 Counter with Timing Diagram and Application

Mode 2 is called the Rate Generator Mode. It is one of the 6 modes of operation in the 8254
programmable interval timer.

Purpose:

It is used to generate a continuous stream of pulses at regular intervals — useful for baud rate
generation in serial communication.

How Mode 2 Works:

 A value (N) is loaded into the counter.

 Output goes low for one clock pulse when the counter reaches 1.
 Then the counter automatically reloads and continues counting without stopping.
 This process repeats continuously.

Timing Diagram of Mode 2:

CLK: |‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
OUT: ‾‾‾‾‾‾‾‾‾|____|‾‾‾‾‾‾‾‾‾|____|‾‾‾‾

Each "low" pulse in OUT is 1 clock wide and comes after (N) clock cycles.

Application of Mode 2:

 Baud rate generation for serial communication (like RS-232).

 Periodic interrupt generation in embedded systems.

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  Keyboard scanning or watchdog timer.

3. Distinguish Between 8253 and 8254 Counter

Feature 8253 Timer 8254 Timer

Year Introduced Earlier Improved version of 8253
Clock Frequency Up to 2.6 MHz Up to 10 MHz
Read-Back Command Not Supported Supported
Number of Counters 3 3
Counter Size 16-bit 16-bit
Binary or BCD Count Binary / BCD Binary / BCD
Software Features Basic modes only Additional read/write modes
Used in Older systems Modern microprocessor systems

Summary:

 Interrupt Acknowledge Machine Cycle lets the processor fetch the vector or ISR
address after acknowledging an interrupt. It involves 2 machine cycles with INTA̅
signals.
 Mode 2 of 8254 is a Rate Generator, producing regular pulses used in serial
communication, etc.
 8254 is an advanced version of 8253, with higher speed and better features (like read-
back command).

Let me know if you’d like diagrams or hand-drawn notes to better visualize this.

Here is a detailed and easy-to-understand answer with proper explanation to each of your
questions:

1. Explain the DMA-Based Data Transfer Using DMA Controller

DMA (Direct Memory Access) is a technique where data is transferred directly between I/O
devices and memory, bypassing the CPU. This makes data transfer faster and efficient.

How It Works:

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  A DMA controller (like Intel 8237) manages the data transfer.
 When a device wants to transfer data (e.g., a disk or sound card), it sends a DMA request
(DRQ) to the DMA controller.
 The DMA controller requests the CPU to release the control of the system bus.
 The CPU responds with a HLDA (Hold Acknowledge) signal and gives up control of
the bus.
 Then the DMA controller takes control of the buses and transfers data directly between
I/O and memory.
 After the transfer, control is returned to the CPU.

Steps in DMA Transfer:

1. I/O device sends DMA request.

2. DMA controller sends HOLD to CPU.
3. CPU sends HLDA to DMA controller and stops using buses.
4. DMA controller transfers data to/from memory.
5. DMA controller releases the bus and CPU resumes work.

Advantages:

 Reduces CPU workload.

 Increases system performance.
 Ideal for fast and large data transfers (e.g., audio, video, disk data).

2. Briefly Explain Handshaking or Polling With Necessary Diagrams

Polling:

In polling, the CPU keeps checking the status of an I/O device to know if it’s ready for data
transfer.

Example:

Repeat:
Check printer status
Until:
Printer is ready
Send data to printer

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 Disadvantage: CPU stays busy checking, which wastes time.

Handshaking:

Handshaking is a technique where signals are exchanged between CPU and I/O devices to
coordinate data transfer.

2-way Handshaking Process:

1. Device sends a signal: Data Ready

2. CPU responds with: Data Acknowledge
3. After receiving the acknowledge, the device sends or receives data.

Diagram:

Device: |---Data Ready--->|

CPU: |<--Acknowledge---|
Data Flow: <----Data---------> (or vice versa)

Advantage of Handshaking:

 Efficient and reliable.

 CPU and device communicate only when both are ready.

3. Explain the Concept of Segmented Memory. What Are Its Advantages?

Segmented Memory is a technique used in 8086 microprocessor to divide memory into logical
parts called segments. This helps in better organization and access of memory.

Segments in 8086:

1. Code Segment (CS) – Stores the program instructions.

2. Data Segment (DS) – Stores program data.
3. Stack Segment (SS) – Used for stack operations.
4. Extra Segment (ES) – Used for additional data storage.
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Each segment is 64 KB, and the 8086 can access 1 MB memory using segment:offset
addressing.

Physical Address = Segment × 10h + Offset

Example:

CS = 2000h, IP = 0010h
Physical Address = 20000h + 0010h = 20010h

Advantages of Segmented Memory:

 Efficient memory use: Code, data, and stack are kept separate.
 Easier program modularity: Different modules can be placed in different segments.
 Supports multitasking: Each task can be given its own segment.
 Helps in memory protection and management.

Summary:

Concept Key Points

Transfers data without CPU using DMA controller; speeds up large
DMA
transfers.
Polling CPU keeps checking device status – inefficient.
Devices and CPU exchange control signals before data transfer – reliable
Handshaking
and efficient.
Segmented Divides memory into logical segments like CS, DS, SS, ES for efficient
Memory and organized access.

Let me know if you'd like diagrams for DMA transfer, handshaking, or segment calculations!

Here are the answers with simple explanations and proper structure as requested:

1. Write down advantages and disadvantages of I/O Channels

I/O Channels are special-purpose processors that handle input/output operations, freeing up
the main CPU.

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 Advantages of I/O Channels:

 Reduces CPU workload – I/O operations are managed independently.

 Faster I/O processing – Operations can be done in parallel with CPU work.
 Efficient multitasking – CPU can process one task while I/O channel handles another.
 Better system throughput – More overall work done per unit of time.
 Supports complex I/O operations – Like file transfer, disk read/write, etc.

Disadvantages of I/O Channels:

 Increased hardware cost – Needs separate I/O processors.

 Complex system design – Coordination between CPU and I/O channels required.
 Programming complexity – More code and control required to manage them.
 Power consumption – Adds to total system power usage.

2. Write a short note on I/O Processor

An I/O Processor (IOP) is a special processor designed to control I/O devices like printers,
disk drives, etc.

Functions:

 Receives I/O instructions from the main CPU.

 Controls I/O devices directly.
 Transfers data between memory and I/O devices without CPU help.
 Signals the CPU when I/O is done.

Benefits:

 CPU is free to handle only computation.

 Improves overall system performance.
 Commonly used in large or multitasking systems.

3. Why is a Priority Interrupt Controller Needed in 8086 System?

The 8086 microprocessor can be interrupted by several devices at once.

Reason for Priority Interrupt Controller (like 8259A):

 Manages multiple interrupt requests from different I/O devices.

 Gives priority to the most important interrupt (e.g., keyboard over printer).

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  Queues the rest to handle later.
 Ensures that no interrupt is lost.
 Works efficiently with both maskable and non-maskable interrupts.

Without a controller like 8259A, 8086 can only handle one interrupt line, making it inefficient
in multi-device systems.

4. Write Down the Sending Order of 8259A Initialization Command Word

(ICW)

The 8259A Programmable Interrupt Controller is initialized using Initialization Command

Words (ICWs).

Sending Order:

1. ICW1 – Sent first. Tells the 8259A to start initialization and mode (e.g., edge/level
triggered).
2. ICW2 – Sets the base address of the interrupt vector table.
3. ICW3 – Required only in cascaded mode (master/slave info).
4. ICW4 – Defines additional settings (e.g., 8086 mode, buffered mode).

Summary Table:

Item Description
I/O Channels Separate hardware for I/O tasks
IO Processor Handles I/O independently from CPU
Priority Interrupt Controller Controls interrupt priorities for multiple devices
8259A ICW Order ICW1 → ICW2 → ICW3 (if needed) → ICW4

Let me know if you'd like diagrams for 8259A or I/O architecture!

Sure! Here's the proper explanation for each part of your question using easy-to-understand
language and structured clearly:

SESSION 2018-19
CT
1. Define Microprocessor
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A Microprocessor is the central processing unit (CPU) of a computer built on a single chip.
It is a programmable device that takes input, processes it using instructions stored in memory,
and gives output.

It performs:

 Arithmetic operations (add, subtract, etc.)

 Logical operations (AND, OR, NOT, etc.)
 Data movement (transfer data from one location to another)
 Control operations (control program execution flow)

2. Differentiate between Data Bus, Address Bus, and Control Bus

Bus Type Purpose Direction

Transfers actual data between processor,
Data Bus Bidirectional
memory, and I/O devices
Address Carries the address of memory or I/O
Unidirectional
Bus devices to access data
Control Carries control signals like Read/Write, Unidirectional/Bidirectional (depends on
Bus Interrupt, Clock, etc. signal type)

3. Describe Von Neumann Architecture with Block Diagram

The Von Neumann Architecture is a computer design model where:

Data and program instructions are stored in the same memory.

It uses a single bus system for both data and instructions.

Main Components:

 Memory: Holds both instructions and data.

 ALU (Arithmetic Logic Unit): Performs calculations and logic.
 Control Unit: Directs all operations in the CPU.
 Input/Output: Interfaces to the outside world.
 Registers: Temporary storage in the CPU.

Block Diagram (Text Representation):

+-------------+ +------------+
| Input Unit |<------->| |
+-------------+ | |
| Control |

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 +-------------+ | Unit |<--------> Clock
| Output Unit|<------->| |
+-------------+ +------------+
|
v
+------------------+
| ALU (CPU core) |
+------------------+
|
v
+------------------+
| Memory Unit | <-- Program & Data both
stored here
+------------------+

4. Write down the content and operations of BIU unit of 8086 Microprocessor

BIU = Bus Interface Unit

The Bus Interface Unit (BIU) in 8086 is responsible for fetching instructions, reading/writing
data, and communicating with memory and I/O.

Contents of BIU:

 Instruction Queue (6 bytes) – Pre-fetches instructions.

 Segment Registers – CS, DS, SS, ES.
 Instruction Pointer (IP) – Points to next instruction.
 Address Generation Circuit – Calculates physical addresses.
 Bus Control Logic – Controls the system bus.

Operations:

 Fetches instructions and stores them in queue.

 Computes 20-bit physical addresses using:
 Physical Address = Segment Register × 10H + Offset
 Handles memory and I/O read/write operations.
 Sends data to Execution Unit (EU) when needed.

5. What will be the output of the status flags after executing the instruction:

ADD BX, AX where AX = 1EEFH and BX = 1F8EH

Let’s calculate:

AX = 1EEFH
BX = 1F8EH

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BX = BX + AX
= 1F8E + 1EEF = 3E7D

In Hex:

1F8E + 1EEF = 3E7D → No overflow

Now check the FLAGS:

Flag Explanation Value

Carry Flag (CF) No carry beyond 16 bits (result < FFFF) 0
Zero Flag (ZF) Result ≠ 0 0
Sign Flag (SF) MSB = 0 (positive number) 0
Overflow Flag (OF) No overflow from signed operation 0
Auxiliary Carry (AF) May depend on bit 3 to bit 4 carry (optional to calculate) 1 or 0
Parity Flag (PF) Even number of 1’s in LSB (can be calculated) ?

So, result = 3E7D, and main flags:

 CF = 0
 ZF = 0
 SF = 0
 OF = 0

Let me know if you want the flag values calculation step-by-step, or a diagram for Von
Neumann architecture!

Here is the full answer to your question, written in clear and easy-to-understand language,
with explanations and block diagrams:

1. Describe Harvard Architecture with Block Diagram

Harvard Architecture is a type of computer architecture where the program instructions

and data are stored in separate memory units and accessed through different buses.

This means:

 One bus is used for fetching instructions.

 Another bus is used for reading/writing data.

Features:
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  Faster because instructions and data can be fetched simultaneously.
 Used in microcontrollers and signal processing devices.

Block Diagram (Text Representation):

+------------------+
| Control Unit |
+--------+---------+
|
+-------------+-------------+
| |
+------+-----+ +------+-----+
| Instruction | | Data |
| Memory | | Memory |
+------+-----+ +------+-----+
| |
+-------+------+ +--------+------+
| Instruction | | Data Bus |
| Bus | +---------------+
+---------------+

Summary:

 Separate memory = no conflict between data and instruction fetch.

 Faster performance than Von Neumann architecture.
 Used in DSPs (Digital Signal Processors) and microcontrollers.

2. Briefly Describe Memory Segmentation. Also Define Why We Need Memory

Segmentation

Memory Segmentation is a technique used in the 8086 microprocessor to divide the

memory into small, manageable parts called segments.

Each segment is 64 KB in size.

8086 has 4 main segments:

1. Code Segment (CS) – stores program instructions.

2. Data Segment (DS) – stores program data.
3. Stack Segment (SS) – used for stack operations.
4. Extra Segment (ES) – used for additional data.

Each segment has a segment register, and memory is accessed using a combination of:

Physical Address = Segment Register × 10H + Offset

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 Why Do We Need Memory Segmentation?

Reason Explanation
1. Efficient Memory Segmentation allows easy handling of large programs by dividing
Management them into logical parts.
2. Modular Programming Code, data, and stack can be handled independently.
By changing only the offset or segment register, we can quickly
3. Faster Access
access different parts of memory.
4. Increases Addressable Although registers are 16-bit, segmentation helps access 1MB
Memory memory in 8086.

Let me know if you want a diagram for memory segmentation or a comparison between
Harvard and Von Neumann architecture!

Here is the full answer with simple explanations for each part of your question:

Why Priority Interrupt Controller is Needed?

In a system like 8086, multiple devices can request interrupts at the same time. A Priority
Interrupt Controller like 8259A helps manage these interrupt requests.

Reasons Why It Is Needed:

1. Multiple Interrupts Handling: It allows 8086 to handle many interrupt sources (more
than one at a time).
2. Priority Management: It decides which interrupt is more important (higher priority) and
sends that to the CPU first.
3. Efficient Execution: Prevents lower-priority devices from disturbing the CPU when
higher-priority interrupts are being serviced.
4. Reduces CPU Workload: The CPU does not have to check each device. The controller
manages requests.

Internal Block Diagram of 8259A PIC (Simplified Text View)

+-------------------+
| Data Bus Buffer |
+--------+----------+
|

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 +--------v----------+
| Read/Write |
+--------+----------+
|
+---------------+--------------------+
| | |
+---v---+ +-----v-----+ +------v------+
| IRR | | Priority | | In-Service |
| (IRQ) | --> | Resolver | ----> | Register |
+-------+ +-----------+ +-------------+
| |
+---------> Control Logic <---------+
|
+------v-------+
| INT (to CPU) |
+--------------+

 IRR (Interrupt Request Register): Stores incoming requests.

 Priority Resolver: Decides which interrupt has higher priority.
 ISR (In-Service Register): Tracks interrupts currently being serviced.
 Control Logic: Coordinates the operation.

Minimum Mode Pin Functions of 8086 Microprocessor

In Minimum Mode, the 8086 works as a single processor system (no other processor like
coprocessor or another CPU).

Here are some important pins in Minimum Mode and their functions:

Pin Name Function

MN/MX̅ Low (0) selects Minimum Mode.
ALE (Address Latch
Used to latch the address from multiplexed address/data bus.
Enable)
Read control signal. Low means processor wants to read from
RD̅
memory or I/O.
Write control signal. Low means processor writes data to memory
WR̅
or I/O.
DT̅/R Tells direction of data (Data Transmit/Receive).
DEN (Data Enable) Enables external data bus drivers.
INTA̅ (Interrupt
Indicates that CPU is acknowledging an interrupt.
Acknowledge)
HOLD / HLDA Used in DMA. HOLD requests the bus. HLDA acknowledges it.
READY Used to insert wait states for slower peripherals.

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Let me know if you'd like a clean diagram version of the internal block or pin functions!

Here’s the detailed explanation of your questions in clear and simple words:

1. Describe Only the Maximum Mode Pin Functions of 8086 Microprocessor

In Maximum Mode, the 8086 microprocessor is used in multiprocessor systems (with a co-
processor or multiple CPUs). In this mode, control signals are not generated by 8086 itself;
instead, they are generated by an external bus controller (like 8288).

Some key pins/functions in Maximum Mode are:

Pin Name Function

MN/MX̅ (Pin 33) Set to 1 (HIGH) to enable Maximum Mode.
Status lines that tell the type of operation (memory read, I/O
S2̅, S1̅, S0̅
write, etc.). These are inputs to 8288.
RQ̅/GT̅1 and RQ̅/GT̅0 Used by other processors to request the bus. 8086 grants bus
(Request/Grant) through these pins.
Prevents other processors from accessing the bus while current
LOCK̅
instruction is running (used during critical instructions).
QS1 and QS0 (Queue Show the status of the instruction queue (empty, first byte ready,
Status) etc.).
INTA̅ (Interrupt
Used to acknowledge hardware interrupts via INTR pin.
Acknowledge)
Same function as in minimum mode (clock input, reset signal,
CLK, RESET, READY
wait states).

2. What Are the Differences Among INTR, INTA̅, and NMI Pins in 8086
Microprocessor?

Let’s explain each pin and then the differences:

INTR (Interrupt Request)

 It is a maskable interrupt pin (can be disabled using software).

 Devices use this pin to request interrupt service.
 Processor checks it only after completing the current instruction.
 Needs INTA̅ signal to acknowledge it.

INTA̅ (Interrupt Acknowledge)

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  This is an output pin from the processor.
 When 8086 receives a request through INTR, it sends a low pulse on INTA̅ to tell the
device that its request is accepted.
 Usually used with INTR only.

NMI (Non-Maskable Interrupt)

 It is a non-maskable interrupt pin (cannot be disabled by software).

 Used for emergency situations like power failure, memory error.
 Has higher priority than INTR.
 It is edge-triggered (activated by a rising edge signal).

Main Differences Summary:

Feature INTR INTA̅ NMI

Type Maskable Input Acknowledge Output Non-Maskable Input
Priority Lower — Higher
Software Maskable? Yes No No
Triggered by Level Sent by CPU Rising Edge
Use General hardware interrupt Response to INTR Emergency alerts

Let me know if you'd like a diagram of pin layout or a real-life use case example!

Here’s a detailed, easy-to-understand answer with proper explanation, timing diagram, and step-
by-step structure as per your request:

I. Describe Mode 2 (Timed Interrupt Generator) of 8254 Counter with Proper

Timing Diagram. Develop a System Where You Can Use This Mode. (8+2 marks)

Mode 2 – Rate Generator / Timed Interrupt Generator:

Mode 2 is used to generate periodic interrupts or pulses at regular intervals. It behaves like a
divide-by-N counter, meaning it divides the clock input frequency.

 The output goes low for one clock pulse, and high for the remaining N–1 clock pulses.
 Once the count is loaded, the counter automatically reloads and continues, so no
reloading is needed manually.
 This makes it suitable for generating repeating interrupts to the CPU.

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 Timing Diagram:

CLK: ─┐┌─┐┌─┐┌─┐┌─┐┌─┐┌─┐┌─┐┌─┐┌─┐┌─┐
┘└─┘└─┘└─┘└─┘└─┘└─┘└─┘└─┘└─┘└─┘
OUT: ────────────────┐________┐________
↓ ↓
Low for 1 clk → auto reload

Example Use Case:

Use Mode 2 to generate timer interrupts in a real-time system:

 Suppose you want to generate a 1 kHz interrupt for a digital clock.

 Connect the OUT of 8254 (in Mode 2) to the INTR pin of 8086.
 It will trigger an interrupt every 1 ms, which can be used to update the clock or do
timed tasks.

II. Write Down and Briefly Describe All the Steps to Initialize an 8254
Programmable Peripheral Device with the Control Word Format. (10 marks)

Steps to Initialize 8254 Timer:

1. Choose the Counter (0, 1, or 2)

o You need to pick which counter you are programming (Timer 0, Timer 1, or
Timer 2).
2. Prepare Control Word Format:

Bit 7 6 5 4 3 2 1 0
Use SC1 SC0 RW1 RW0 M2 M1 M0 BCD

 SC1–SC0 = Select Counter:

o 00 → Counter 0
o 01 → Counter 1
o 10 → Counter 2
 RW1–RW0 = Read/Write:
o 11 → Read/write both LSB and MSB
 M2–M0 = Mode:
o 010 → Mode 2 (Rate Generator)
 BCD:
o 0 → Binary mode (16-bit)
o 1 → BCD (4-digit)

Example Control Word for Counter 0, Mode 2, Binary:

Binary: 00110100 = Hex 34H
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 3. Send Control Word to 8254:
o Use an OUT instruction from the CPU to send the control word.
4. Load Initial Count:
o Write LSB first, then MSB of the count (if RW1–RW0 = 11).

III. Define Cycle Stealing. Write Down the Differences Between DMA and I/O
Processor.

Cycle Stealing:

 Cycle Stealing is a feature of DMA (Direct Memory Access) where the DMA controller
temporarily takes control of the system bus from the CPU to transfer data.
 It "steals" one clock cycle at a time, without completely stopping the CPU.
 This way, DMA can transfer data in the background with minimal effect on CPU
performance.

Difference Between DMA and I/O Processor:

Feature DMA Controller I/O Processor

Transfers data directly between Controls and manages I/O devices
Purpose
memory and I/O independently
CPU
Minimal – just initiates transfer Not needed during I/O operations
Involvement
Intelligence Simple – no decision-making Smart – can execute I/O instructions
Example 8237 DMA controller Intel 8089 I/O processor
I/O device manager with processing
Functionality Data mover
power

Let me know if you'd like the 8254 control word format table, timing diagrams as images, or
a diagram of 8237 DMA controller!

SEMESTER
Let’s answer both questions with full, easy-to-understand explanations as requested:

1. What Will Happen When a PC Is Powered On?

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When a PC is powered on, the following sequence of events happens:

Step-by-Step Booting Process:

1. Power Supply Turns On (SMPS):

o Supplies power to motherboard, CPU, RAM, and other components.
2. Power-On Self Test (POST):
o The BIOS (Basic Input/Output System) runs a diagnostic called POST.
o It checks CPU, RAM, keyboard, display, and essential hardware.
o If any serious issue is found, beep codes are generated (like 1 long beep, 2 short
beeps etc.).
3. BIOS Executes Bootloader:
o After successful POST, BIOS looks for a bootable device (like HDD/SSD).
o It loads the bootloader (like GRUB or Windows Boot Manager) from the
Master Boot Record (MBR).
4. Operating System Loads:
o The bootloader loads the OS kernel into RAM.
o The OS then takes control and starts loading system files and drivers.
5. Login/Startup Interface Appears:
o The system finally reaches the user login screen or desktop.

2. Define "Hardware Retriggerable One Shot" Mode of 8254 Counter and Its
Application

Mode 1 – Hardware Retriggerable One-Shot (Monostable Multivibrator):

 In this mode, the counter produces a single low pulse for a fixed amount of time
whenever a trigger (rising edge on GATE input) is received.
 If another trigger comes before the time expires, the counter restarts the timing again
— this is called retriggerable behavior.

Key Points:

 OUT goes low on trigger and remains low for the duration of the count.
 New trigger resets the count and restarts the one-shot.
 Used to generate timed pulses after events.

Timing Diagram:

CLK: ─┐┌─┐┌─┐┌─┐┌─┐┌─┐┌─┐┌─┐
┘└─┘└─┘└─┘└─┘└─┘└─┘└─┘

GATE: ↑ ↑
Trigger Trigger again

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OUT: ─────────┐ ┐
└───────┘← Retriggered

Application of Mode 1:

 Used in industrial control systems, security alarms, or timer relays.

 For example: to activate a buzzer for 2 seconds when someone presses a button.
 If the button is pressed again within 2 seconds, the buzzer stays on longer (retriggered).

Let me know if you'd like the timing diagram as an image or explanation of another 8254
mode!

Let me explain the three questions you asked:

1. Role of Clock in a Microprocessor

The clock in a microprocessor plays a crucial role in coordinating the timing of operations. It
helps synchronize all internal and external components of the microprocessor.

 Clock Signal: The clock generates a regular sequence of pulses (often referred to as
"ticks"). Each tick represents a timing cycle, and operations inside the microprocessor are
aligned with these ticks.
 Timing Control: The clock signal controls the timing of instructions and synchronizes
the flow of data between the microprocessor and peripherals. Every operation or
instruction, like fetching, decoding, and executing, takes place in sync with the clock
pulses.
 Clock Speed (Frequency): The clock speed (measured in Hz or cycles per second)
determines how fast the microprocessor can process instructions. A higher clock speed
allows the microprocessor to perform more operations per second.

2. Function of Various Flags in 8086 Microprocessor

The 8086 microprocessor has five important flags in the Flag Register. These flags indicate the
status of certain operations and influence conditional operations.

Flags in 8086:

1. Carry Flag (CF):

o Set when an arithmetic operation generates a carry or borrow (e.g., in addition or
subtraction).
o Used for signed or unsigned arithmetic overflow.
2. Parity Flag (PF):

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 o Set if the number of 1-bits in the result is even. Otherwise, it is cleared (for odd
parity).
o This is used for error detection.
3. Auxiliary Carry Flag (AF):
o Set if there is a carry from bit 3 to bit 4 during binary addition or subtraction.
o Useful for BCD (Binary Coded Decimal) operations.
4. Zero Flag (ZF):
o Set if the result of an operation is zero (i.e., the operands are equal).
o Used for making decisions in conditional branches.
5. Sign Flag (SF):
o Set if the result of an operation is negative (i.e., the most significant bit of the
result is 1).
o Used to indicate the sign of the result.
6. Overflow Flag (OF):
o Set if the result of a signed operation is too large to be represented in the given
number of bits.
o Indicates overflow in signed arithmetic operations.
7. Trap Flag (TF):
o Used to enable single-step execution mode for debugging.
o Each instruction execution will be interrupted for debugging.
8. Interrupt Flag (IF):
o Controls the interrupts. If set, interrupts are enabled. If cleared, interrupts are
disabled.
9. Direction Flag (DF):
o Determines the direction for string processing (string instructions like MOVSB,
LODS, etc.).
o Set for decrementing the pointer; cleared for incrementing.

3. 5 Addressing Modes of 8086 with Examples

The 8086 microprocessor supports several addressing modes to specify where operands (data)
are located. Here are 5 addressing modes:

1. Immediate Addressing Mode:

o The operand is specified directly in the instruction.
o Example: MOV AX, 5
(Here, 5 is the immediate value stored in the AX register).
2. Register Addressing Mode:
o The operand is located in a register.
o Example: MOV AX, BX
(Here, the value of BX is copied into AX).
3. Direct Addressing Mode:
o The operand is at a specific memory location directly given in the instruction.

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 o Example: MOV AX, [1234h]
(Here, the data at memory address 1234h is moved into AX).
4. Indirect Addressing Mode:
o The operand is at a memory location pointed to by a register.
o Example: MOV AX, [SI]
(Here, the content of the memory location pointed to by SI is moved into AX).
5. Based Indexed Addressing Mode:
o Combines both a base register and an index register to compute the effective
memory address.
o Example: MOV AX, [BX+SI]
(Here, the contents of the memory location computed by adding BX and SI are
moved into AX).

Let me know if you need any further clarification!

Let me break down the questions for you.

1. Internal Block Diagram of 8086

The 8086 microprocessor is a 16-bit processor and follows a Harvard architecture (separate
data and instruction buses). Its internal structure consists of several key components:

Internal Block Diagram Overview:

1. ALU (Arithmetic Logic Unit):

o The ALU performs all the arithmetic and logical operations in the
microprocessor. It can add, subtract, compare, and perform bitwise operations like
AND, OR, and NOT.
2. Registers:
o The 8086 has a set of 16-bit registers for storing temporary data, including:
 General-purpose registers: AX, BX, CX, DX (used for operations).
 Pointer registers: SP (stack pointer), BP (base pointer).
 Index registers: SI (source index), DI (destination index).
 Segment registers: CS (code segment), DS (data segment), SS (stack
segment), ES (extra segment).
 Status registers: Flags register (including carry, zero, overflow, etc.).
3. Control Unit:
o The control unit decodes the instructions and generates control signals to direct
the flow of data and operations within the processor.
o It manages sequences of operations and handles fetching, decoding, and
executing instructions.
4. BIU (Bus Interface Unit):

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 o The BIU manages the interaction between the microprocessor and memory or I/O
devices.
o It consists of:
 Instruction queue: Holds pre-fetched instructions.
 Segment registers: Used to hold the memory segments.
 Bus control unit: Controls the communication on the system bus.
5. Execution Unit (EU):
o The EU executes the instructions provided by the BIU.
o It includes the ALU, general-purpose registers, and flags that are used during
instruction execution.
6. Instruction Queue:
o The 8086 has a 6-byte instruction queue that allows the processor to pre-fetch
instructions while executing the current one. This helps improve performance by
increasing instruction throughput.

Key Operations in 8086:

 Fetch: The instruction is fetched from memory.

 Decode: The instruction is decoded to determine the required operation.
 Execute: The required operation (arithmetic, logical, etc.) is performed.

2. Function of Segment Registers in 8086

The 8086 microprocessor uses a segmented memory model. This means that memory is
divided into segments, and each segment is addressed using a segment register. The segment
registers are used to define the starting address of different memory segments.

Here are the segment registers and their functions:

1. Code Segment (CS):

o Points to the segment where the executable instructions (code) are stored.
o The CS register is automatically updated by the instruction pointer (IP) as the
program executes.
2. Data Segment (DS):
o Points to the segment where data (variables, arrays, etc.) is stored.
o This segment is primarily used for storing data that is accessed by the instructions
in the program.
3. Stack Segment (SS):
o Points to the segment that holds the stack.
o The stack is used to store temporary data, function call addresses, and local
variables during the program's execution.
4. Extra Segment (ES):
o Often used as an additional data segment. It is usually used for string operations
or other data that may be needed by the program.

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 o It is often used in string manipulation instructions like MOVSB, LODSB, etc.

The segment registers are used in combination with the offset address to calculate a full
physical memory address. The physical address is calculated as:

Physical Address = (Segment Address × 16) + Offset

This helps to address memory locations beyond the 64KB limit of the 16-bit address bus.

3. Difference Between 8085 and 8086 Microprocessor

The 8085 and 8086 are both microprocessors, but there are several key differences between
them:

Feature 8085 Microprocessor 8086 Microprocessor

Data Bus Width 8 bits (8-bit microprocessor) 16 bits (16-bit microprocessor)
Address Bus 16 bits (64KB memory
20 bits (1MB memory addressing)
Width addressing)
Single Bus (Von Neumann Harvard Architecture (Separate Data and
Architecture
Architecture) Code Buses)
More complex, with support for 16-bit
Instruction Set Simple instruction set
instructions
5 8-bit registers (B, C, D, E, H,
Registers 14 16-bit registers (AX, BX, CX, DX, etc.)
L)
Clock Speed Up to 5 MHz Up to 10 MHz or more
5 Interrupts (2 maskable, 3 non- 256 Interrupts (maskable and non-
Interrupts
maskable) maskable)
Operating Modes Single Mode Minimum and Maximum Modes
Instruction
No instruction queue 6-byte instruction queue
Queue
Can operate in multiprocessing systems
Multiprocessing No support for multiprocessing
(with a co-processor)

Let me know if you need further clarification on any of these topics!

1. Unknown Value for Each Physical Address

We are asked to find the unknown value for the physical address in two scenarios. The 8086
uses segmented memory addressing, where the physical address is calculated as:

100 | P a g e
Physical Address=(Segment Address×16)+Offset Address\text{Physical Address} =
(\text{Segment Address} \times 16) + \text{Offset Address}

Let's go step by step for each of your cases:

(i) A000H:? = A0123H

 Here, the segment address is A000H and the offset address is 0123H.
 The physical address is given as A0123H.

Let's calculate the unknown value:

We know the formula:

Physical Address=(Segment Address×16)+Offset Address\text{Physical Address} =

(\text{Segment Address} \times 16) + \text{Offset Address}

So,

A0123H=(A000H×16)+0123HA0123H = (A000H \times 16) + 0123H

We can calculate A000H×16A000H \times 16:

A000H×16=A0000HA000H \times 16 = A0000H

Now,

A0123H=A0000H+0123HA0123H = A0000H + 0123H

This is true, so the unknown value for the offset is 0123H.

(ii) ?: CD21H = 32D21H

 Here, the segment address is unknown, and the offset address is CD21H.
 The physical address is given as 32D21H.

We can use the formula again:

Physical Address=(Segment Address×16)+Offset Address\text{Physical Address} =

(\text{Segment Address} \times 16) + \text{Offset Address}

So,

32D21H=(?×16)+CD21H32D21H = (? \times 16) + CD21H

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Let's isolate the segment address:

32D21H−CD21H=?×1632D21H - CD21H = ? \times 16

First, subtract CD21H from 32D21H:

32D21H−CD21H=26000H32D21H - CD21H = 26000H

Now, divide 26000H by 16 to get the segment address:

?=26000H10H=2600H? = \frac{26000H}{10H} = 2600H

So, the unknown segment address is 2600H.

2. Difference Between MOV AX, 2378H and MOV AX, [2378H]

 MOV AX, 2378H:

o This instruction loads the value 2378H directly into the AX register. The value
2378H is a literal constant (an immediate value).
o The instruction uses 2378H as data, and it directly moves this value into the AX
register.

Example:

o AX = 2378H (AX now holds the value 2378H)

 MOV AX, [2378H]:
o This instruction uses indirect addressing. The value 2378H is a memory
address (a pointer), and the instruction loads the value stored at the memory
address 2378H into the AX register.
o So, instead of directly using 2378H as a data value, this instruction fetches the data
stored at memory location 2378H and moves that data into AX.

Example:

o If memory at address 2378H holds the value 1234H, then AX = 1234H after
executing MOV AX, [2378H].

Summary of Differences:

Instruction Description Operation on AX

MOV AX, Directly moves the immediate value 2378H into
AX = 2378H
2378H the AX register.

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 Instruction Description Operation on AX
MOV AX, Moves the value stored at the memory address AX = content at memory
[2378H] 2378H into the AX register. address 2378H

Let me know if you need further explanations or clarifications!

1. Why INTR Input is Automatically Disabled as Part of the Response to an

INTR Interrupt:

The INTR (Interrupt Request) pin in the 8086 microprocessor is part of the interrupt handling
mechanism. When an interrupt is received via the INTR pin, the microprocessor needs to stop its
current execution to service the interrupt. However, if the interrupt is not masked, there is a risk
of the same interrupt being triggered again while the processor is still servicing the first interrupt.

To prevent nested interrupts (interrupts occurring before the current interrupt is fully serviced),
the 8086 automatically disables the INTR pin when it begins processing the interrupt. This is
done by clearing the interrupt enable flag in the IF (Interrupt Flag) register.

Here's how it works:

 INTR is an interrupt request input, and when the interrupt is acknowledged, the
microprocessor disables the INTR input to ensure that no further interrupts are processed
while the current interrupt is being serviced.
 After the interrupt service routine (ISR) completes, the interrupt enable flag (IF) is re-
enabled, allowing further interrupts to occur.

This behavior ensures that the interrupt service routine can complete without being interrupted
by another interrupt, providing atomic processing of the interrupt.

2. Architecture of 8087:

The 8087 is a floating-point coprocessor designed to work with the 8086/8088 microprocessor.
It provides hardware support for floating-point arithmetic operations like addition, subtraction,
multiplication, and division, which the main processor (8086/8088) does not handle efficiently.

Architecture of 8087:

The 8087 has the following components:

 Control Register: Used to control the operations of the coprocessor, including

enabling/disabling certain features.

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  Status Register: Provides information about the status of the coprocessor operations,
including the error conditions.
 Tag Register: This register stores the status of the floating-point registers. It indicates
whether a register contains a valid or invalid value.
 Data Registers (ST(0) to ST(7)): These are used to store floating-point numbers.
 Execution Unit (EU): This performs arithmetic operations like addition, subtraction, etc.
 Instruction Queue: Similar to the 8086, it holds the instructions before they are
executed.

Block Diagram of 8087:

+------------------------+
| Control Register |
+------------------------+
|
v
+------------------------+
| Status Register |
+------------------------+
|
v
+------------------------+ +---------------------+
| Data Registers | <---------> | Execution Unit |
| (ST(0) to ST(7)) | +---------------------+
+------------------------+
|
v
+------------------------+
| Tag Register |
+------------------------+

3. Status Register, Control Register, and Tag Register of 8087:

The 8087 coprocessor has several important registers that control its operations and track the
status of computations:

1. Status Register (SREG):

 The Status Register of the 8087 provides information on the current operation, such as
whether an error has occurred during an operation, whether an operation is still in
progress, or whether the coprocessor is idle.
 It has several flags, including:
o C0 to C3 (Condition flags): These flags store conditions of floating-point
operations, such as whether the result was zero, overflow, etc.
o C (Carry flag): Indicates a carry condition for floating-point arithmetic.
o D (Display flag): Indicates the current floating-point format.

2. Control Register (CREG):

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  The Control Register is used to control the behavior of the 8087 coprocessor.
o It includes flags to control rounding modes, precision, and error handling.
o The EM (Exception Mask) in the control register helps mask or enable
exceptions like division by zero or invalid operations.
o The PC (Precision Control) and RC (Rounding Control) fields in the register
set the precision and rounding mode for floating-point operations.

3. Tag Register (TAGREG):

 The Tag Register keeps track of the status of the 8 floating-point registers (ST(0) to
ST(7)).
 Each bit in the tag register corresponds to one floating-point register and indicates
whether the register contains a valid number or is empty.
o Valid (V): If the bit is set to 0, it means the corresponding register contains a
valid value.
o Empty (E): If the bit is set to 1, it means the corresponding register is empty.
o This helps the 8087 determine which registers are available for use during
operations.

Summary:

1. INTR Input Disabling: The INTR input is disabled when an interrupt is being serviced
to prevent nested interrupts from occurring while the microprocessor is still handling the
current interrupt.
2. Architecture of 8087: The 8087 is a floating-point coprocessor with components such as
the control register, status register, tag register, data registers, and execution unit. It
handles floating-point arithmetic operations for the 8086/8088 processor.
3. Registers in 8087:
o Status Register (SREG): Provides information about the operation status and
error conditions.
o Control Register (CREG): Controls the behavior of the coprocessor, including
rounding, precision, and error handling.
o Tag Register (TAGREG): Tracks the validity of the floating-point registers
(ST(0) to ST(7)).

Let me know if you'd like any further clarifications!

1. What is Direct Memory Access (DMA)? Why is DMA data transfer faster than
doing the same data transfer with program instruction?

Direct Memory Access (DMA) is a method of data transfer in which an external device (like a
peripheral) can directly transfer data to/from memory without involving the CPU. The DMA
controller takes over the data transfer process, allowing the CPU to perform other tasks
simultaneously, which increases the overall system efficiency.

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Why DMA is faster than program instructions for data transfer:

 CPU Involvement: In traditional data transfer using program instructions (like using MOV
in assembly), the CPU must process each byte/word individually. The CPU executes
instructions to read from the source, write to the destination, and manage any necessary
conditions. This involves several cycles per data transfer, leading to slower performance.
 DMA Operation: In DMA, the CPU is not involved in the actual data transfer process.
The DMA controller manages the data transfer directly between the I/O device and
memory, allowing data to be moved quickly without CPU intervention. The CPU only
needs to initiate the DMA operation and can perform other tasks while the DMA
controller handles the data transfer.
 Efficient Use of System Resources: Since DMA allows data to transfer directly between
memory and devices, the CPU doesn't need to spend time managing each byte of data.
This reduces the CPU load, allowing it to perform other tasks while the DMA controller
works, thereby improving system throughput.

2. What are the advantages and disadvantages of DMA controller?

Advantages of DMA:

1. Faster Data Transfer: DMA allows data to transfer directly between memory and I/O
devices, avoiding the CPU’s intervention, which speeds up the process compared to using
program instructions.
2. Reduced CPU Load: By handling data transfers autonomously, DMA frees up the CPU
to perform other operations, improving overall system performance.
3. Efficient Use of Resources: Since DMA can transfer data in bursts without needing
constant CPU interaction, it optimizes the use of both CPU and memory.
4. Multitasking Capability: DMA enables multitasking by allowing the CPU to perform
other tasks while data is being transferred, enhancing the system's overall throughput.

Disadvantages of DMA:

1. Complexity: Implementing DMA requires additional hardware components, such as the

DMA controller, and may involve additional complexities in programming and system
design.
2. Data Contention: During DMA transfers, the DMA controller takes control of the
system bus, which could cause conflicts or delays in other processes that require access to
the bus.
3. Limited Control: DMA bypasses the CPU’s control, which can lead to less flexibility or
oversight over the data transfer process. In certain cases, the CPU may need to intervene
for error handling or prioritization.
4. Memory Access Conflicts: DMA operates in parallel with CPU processes, which could
potentially cause conflicts over memory access or bus contention if not managed
properly.

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3. Describe different bus systems with diagram in a microcomputer.

A bus system in a microcomputer refers to the set of physical connections (wires or traces) that
carry data, addresses, and control signals between various components, such as the CPU,
memory, and I/O devices.

Types of Bus Systems in Microcomputers:

1. Data Bus:
o The data bus carries data to and from the CPU, memory, and peripheral devices.
o The width of the data bus (i.e., the number of lines) determines the amount of data
that can be transferred simultaneously. For example, an 8-bit data bus can transfer
one byte of data per cycle, while a 16-bit bus can transfer two bytes.
2. Address Bus:
o The address bus carries the address information to specify the source or
destination of data in memory or I/O devices.
o The width of the address bus determines the maximum amount of addressable
memory. For example, a 16-bit address bus can address 64KB of memory, while a
32-bit address bus can address up to 4GB.
3. Control Bus:
o The control bus carries control signals that manage the operations of the CPU,
memory, and I/O devices.
o These signals include read/write signals, clock pulses, interrupt requests, and bus
request signals.

Diagram:

+---------------------+ +-----------------------+
| CPU | | Memory/ I/O |
| +------------+ |<----->| +------------+ |
| | Address | | | | Address | |
| | Bus | | | | Bus | |
| +------------+ | | +------------+ |
| +------------+ | | +------------+ |
| | Data Bus | |<----->| | Data Bus | |
| +------------+ | | +------------+ |
| +------------+ | | +------------+ |
| | Control Bus| |<----->| | Control Bus| |
| +------------+ | | +------------+ |
+---------------------+ +-----------------------+

4. What is an Interrupt Vector Table? Write the working principle of Interrupt

Vector Table by a microprocessor.

Interrupt Vector Table (IVT):

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The Interrupt Vector Table (IVT) is a special table used by the microprocessor to store the
addresses of the interrupt service routines (ISR) for different interrupts. It essentially provides
the microprocessor with the location of the code to be executed when an interrupt is triggered.

Working Principle of Interrupt Vector Table:

 When an interrupt occurs, the microprocessor uses the interrupt vector table to determine
which ISR to execute.
 Each interrupt type has a specific location (address) in the interrupt vector table.
 The microprocessor looks up the vector address corresponding to the interrupt number,
retrieves the address of the ISR from that location, and then jumps to that address to
execute the interrupt service routine.

The IVT is typically located at the start of memory (from address 0x0000 to 0x03FF in an 8086
system). Each entry in the table contains the address of the ISR for a specific interrupt.

5. Describe any two types of 8086 Interrupt with examples.

Types of 8086 Interrupts:

1. Hardware Interrupts (INTR):

o The INTR (Interrupt Request) pin is used to request an interrupt from an
external device.
o Example: A keyboard or mouse generating an interrupt when a key is pressed or
a click is detected.
o This interrupt is maskable, meaning the microprocessor can ignore it if interrupts
are disabled.
2. Software Interrupts (INT):
o The INT instruction is used in the program to trigger an interrupt.
o Example: An application program might use INT 21h to make a DOS system call
in older x86 systems.
o Software interrupts are typically used for system calls or to trigger specific
operating system routines.

Let me know if you need further clarification!

SESSION 2017-18
CT
108 | P a g e
1. Define Word and Instruction.

 Word:
o A word is the basic unit of data used by a processor. The size of a word depends
on the architecture of the processor. For example, in an 8085 microprocessor, a
word is 8 bits (1 byte), whereas in the 8086 microprocessor, a word is 16 bits (2
bytes). A word is typically the amount of data the processor can process or
operate on in one machine cycle.
 Instruction:
o An instruction is a binary-coded operation that tells the microprocessor what
operation to perform. Instructions can involve arithmetic operations, data transfer,
or control operations. For example, in the 8086 microprocessor, instructions can
include MOV (move), ADD (add), and SUB (subtract).

2. Explain the Difference Between Machine Language and Assembly Language

of the 8085 Microprocessor.

 Machine Language:
o Machine language is the lowest-level programming language, consisting of
binary instructions directly understood by the processor. It uses binary code (0s
and 1s) to represent instructions that the processor executes.
o Example: A machine language instruction for the 8085 microprocessor might look
like 01010000 00000001 (which might represent a particular operation in the
8085’s instruction set).
o It is difficult for humans to read and write, as it involves raw binary codes.
 Assembly Language:
o Assembly language is a higher-level programming language closely related to
machine language but uses mnemonics (symbolic representations) for
instructions, making it easier for humans to read and write.
o Example: An assembly instruction for the 8085 microprocessor could be MOV A,
B (which means move the value in register B to register A).
o Each assembly language instruction corresponds to a specific machine language
instruction. Assembly language is converted to machine code by an assembler.

3. Difference Between Accumulator-based Microprocessor and General-purpose

Register-based Microprocessor.

 Accumulator-based Microprocessor:

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 o In an accumulator-based microprocessor, the primary focus of most operations
is on the accumulator (A) register. The accumulator acts as both a source and a
destination for most operations.
o Operations like addition, subtraction, and multiplication typically involve the
accumulator. The microprocessor uses the accumulator for intermediate storage,
and most arithmetic operations are performed on it.
o Example: In 8085, many instructions like ADD B, MOV A, B, etc., involve the
accumulator directly.
 General-purpose Register-based Microprocessor:
o In a general-purpose register-based microprocessor, multiple registers (besides
the accumulator) are used to store data. These registers allow for more flexibility
in data processing since operations can involve any of the available registers.
o The microprocessor can perform operations between different registers, which
reduces the dependency on a single accumulator.
o Example: In 8086, there are multiple general-purpose registers (like AX, BX, CX,
DX) that can be used in various operations, allowing for more parallelism and
efficient data handling.

4. Explain the Internal Architecture of the 8086 Microprocessor.

The 8086 microprocessor is a 16-bit processor, and its internal architecture includes several key
components:

 ALU (Arithmetic Logic Unit):

o The ALU performs arithmetic and logical operations such as addition, subtraction,
and bitwise operations.
 Registers:
o General-purpose registers: These include AX, BX, CX, DX for performing
arithmetic and data manipulation operations. Each of these is 16 bits wide.
o Segment registers: These include CS, DS, SS, and ES, which are used for memory
addressing and segmentation.
o Pointer and Index Registers: These include SP, BP, SI, and DI, used to manage
memory addresses.
 BIU (Bus Interface Unit):
o The BIU controls the communication between the 8086 and external devices (like
memory and I/O). It handles the address bus, data bus, and control signals.
 EU (Execution Unit):
o The EU executes instructions by decoding them, interacting with the ALU, and
manipulating registers. It fetches instructions and processes them using the
internal registers and ALU.
 Control Unit:
o The control unit decodes instructions and manages the execution of the
instructions. It ensures that the appropriate signals are sent to different parts of the
microprocessor.

110 | P a g e
  Flags Register:
o The Flags Register stores the status of various operations performed by the ALU,
such as carry, zero, sign, overflow, and parity flags.

5. Explain the Addressing Modes of 8086 Microprocessor.

The 8086 microprocessor supports several addressing modes, which determine how the
effective address of an operand is calculated. Here are the key addressing modes:

1. Immediate Addressing Mode:

o The operand is specified explicitly in the instruction itself.
o Example: MOV AX, 5 (Here, 5 is the immediate operand, and it is directly loaded
into AX).
2. Register Addressing Mode:
o The operand is stored in a register, and the register is specified in the instruction.
o Example: MOV AX, BX (Here, the contents of register BX are moved into register
AX).
3. Direct Addressing Mode:
o The operand's effective address is specified directly in the instruction.
o Example: MOV AX, [1234H] (Here, the data located at memory address 1234H is
moved into AX).
4. Indirect Addressing Mode:
o The operand's effective address is specified indirectly using a register (e.g., SI,
DI, BX, BP).
o Example: MOV AX, [SI] (Here, the content of the memory address pointed to by
SI is moved into AX).
5. Based Addressing Mode:
o The effective address is calculated by adding a base register (e.g., BX, BP) to a
displacement (offset).
o Example: MOV AX, [BX + 10H] (Here, the address is calculated by adding BX and
the offset 10H, and the data at that address is moved into AX).
6. Indexed Addressing Mode:
o The effective address is calculated by adding an index register (e.g., SI, DI) to a
displacement.
o Example: MOV AX, [SI + 10H] (Here, the effective address is calculated by
adding the contents of SI and the displacement 10H).
7. Based Indexed Addressing Mode:
o The effective address is calculated by adding a base register (e.g., BX, BP) and an
index register (e.g., SI, DI), plus a displacement.
o Example: MOV AX, [BX + SI + 10H] (Here, the effective address is calculated
by adding the contents of BX, SI, and the displacement 10H).

111 | P a g e
If you need more details or further clarification on any of the topics, feel free to ask!

Let's answer each question in order with clear explanations and simple language:

1. Describe the functions of BIU of the 8086 microprocessor

The BIU (Bus Interface Unit) is one of the two main parts of the 8086 microprocessor. It works
as the interface between the processor and memory or I/O devices. Its main job is to handle
communication with memory and external devices.

Functions of BIU (Bus Interface Unit):

1. Instruction Fetching:
o BIU fetches instructions from memory in advance and stores them in a 6-byte
instruction queue (called prefetch queue). This helps the processor run faster
(pipelining).
2. Address Calculation:
o BIU calculates the physical address of memory by combining the segment
register and the offset.
3. Bus Operations:
o It handles the address bus, data bus, and control signals for memory and I/O
read/write operations.
4. Segment Handling:
o It holds the segment registers: CS, DS, ES, SS. These registers define different
memory areas (code, data, stack, etc.).

2. What is Addressing Mode?

Addressing Mode refers to the way in which the operand (data) of an instruction is specified.

It tells the microprocessor where to find the data—whether it is in a register, in memory, or

directly in the instruction.

3. Determine the Addressing Modes for the Following Instructions:

i) MOV CH, 8
→ Immediate Addressing Mode
(Here, 8 is directly given in the instruction)

112 | P a g e
ii) MOV AX, DS:START
→ Direct Addressing Mode with Segment Override
(START is a memory label, DS:START specifies a specific memory location in the data
segment)

iii) MOV [SI], AL

→ Register Indirect Addressing Mode
(Data is moved to the memory location pointed by the SI register)

iv) MOV SI, BYTE PTR [BP+2][DI]

→ Based Indexed Addressing Mode with Displacement
(It uses BP as base, DI as index, and displacement = 2)

4. Memory Content after Executing MOV [SI], AX

Given:

 DS = 1120H
 SI = 2498H
 AX = 53EFH

Step 1: Calculate Physical Address

Physical address = DS × 10H + SI

= 1120H × 10H + 2498H
= 11200H + 2498H = 13698H

Step 2: Store AX = 53EFH

 AX is 16-bit. It will be stored in memory as 2 bytes:

o Lower byte (AL = EFH) → stored at 13698H
o Higher byte (AH = 53H) → stored at 13699H

Final Memory Content:

 [13698H] = EFH
 [13699H] = 53H

5. Describe the Difference Between:

a) MOV AX, 2437H

113 | P a g e
  This moves the immediate value 2437H directly into AX.
 Immediate Addressing Mode

b) MOV AX, [2437H]

 This moves the value from memory location 2437H (in DS segment) into AX.
 Direct Addressing Mode

6. Draw the Diagram of Flag Register of 8086 & Mention the Function of AF, SF,
IF, DF

Flag Register Diagram:

|15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
|--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|--|
| | | | |OF|DF|IF|TF|SF|ZF|--|AF|--|PF|--|CF|

Important Flags:

 AF (Auxiliary Carry Flag):

o Used in BCD (Binary-Coded Decimal) operations.
o Set if there is a carry from bit 3 to bit 4 during an operation.
 SF (Sign Flag):
o Indicates the sign of the result.
o Set if the result is negative (MSB = 1).
 IF (Interrupt Flag):
o Controls maskable interrupts.
o Set = CPU will respond to INTR interrupt.
o Clear = CPU will ignore INTR interrupt.
 DF (Direction Flag):
o Used in string operations.
o Set = process from high to low memory.
o Clear = process from low to high memory.

Would you like a clean, printable PDF version of this answer for exam preparation?

What is a Channel?

A channel is a communication path or medium that connects two devices and allows data
transfer between them.
In microprocessor systems, channels are often used for input/output (I/O) operations or
memory access, and they help the CPU manage multiple tasks or devices.

114 | P a g e
 What is a DMA Channel?

A DMA (Direct Memory Access) Channel is a dedicated communication path used by the
DMA controller to transfer data directly between memory and I/O devices without involving
the CPU.

Key Points about DMA Channel:

 Each DMA channel is assigned to a specific device (like a disk drive, sound card, or
network adapter).
 Multiple channels can be present in a DMA controller (e.g., 4 or 8 channels).
 The CPU gives control to the DMA controller, which then manages the transfer
through the assigned channel.
 It uses bus arbitration to gain control of the system buses (address, data, control).

Working of a DMA Channel:

1. Device sends a DMA request (DRQ) to the DMA controller.

2. DMA controller sends a Hold request (HRQ) to the CPU.
3. CPU stops its operation and sends a Hold Acknowledge (HLDA).
4. Now DMA controller uses its channel to transfer data from I/O device to memory (or
vice versa).
5. After completing the transfer, it returns control to the CPU.

Example:

Suppose you are copying a large file from a hard drive to RAM.

 Without DMA: CPU reads data from the hard drive, then writes to memory – slow and
busy CPU.
 With DMA: DMA controller uses a DMA channel to move data directly – CPU is free
for other tasks.

Benefits of Using DMA Channels:

 Faster data transfer (CPU not involved)

 Efficient multitasking (CPU can do other jobs)

115 | P a g e
  Improved system performance

Let me know if you'd like a diagram of the DMA data flow using channels.

SESSION 2016-17
SEMESTER
Here is a clear and organized answer to your questions:

1. Define Microprocessor

A microprocessor is an integrated circuit (IC) that contains the central processing unit (CPU) of
a computer. It performs arithmetic and logic operations, controls system activities, and processes
data. It is the brain of a computer system, but it needs external memory and input/output devices
to function.

Difference between Microprocessor and Microcontroller

Feature Microprocessor Microcontroller

Basic CPU + Memory + I/O ports on a single
CPU on a single chip
Definition chip
Needs external memory and I/O
Components Built-in memory, I/O ports, timers, etc.
modules
Usage Used in general-purpose computers Used in embedded systems
Cost and Power Expensive and consumes more power Low cost and low power consumption
Examples Intel 8085, 8086, Core i7 PIC, AVR, ARM Cortex, 8051

Difference between 8085 and 8086 Microprocessor

Feature 8085 8086

Bit Size 8-bit 16-bit
Address Bus 16-bit (64KB memory) 20-bit (1MB memory)
Data Bus 8-bit 16-bit
Instruction Queue No instruction queue 6-byte instruction queue

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 Feature 8085 8086
Memory Segmentation Not available Available
Number of Registers Fewer More (including segment registers)
Clock Frequency Up to 3 MHz 5, 8, or 10 MHz
Released In 1976 1978

How Does the Microprocessor Work?

A microprocessor works in a cycle of fetch → decode → execute:

1. Fetch: It gets instructions from memory.

2. Decode: It decodes the instruction to understand what needs to be done.
3. Execute: It performs the required operation (e.g., arithmetic or logic operation, data
transfer).
4. Control Unit: Sends control signals to coordinate the operation.
5. Registers: Temporarily hold data for quick access.

2a) Draw & Discuss the Internal Block Diagram of 8086

The 8086 microprocessor has two major units:

1. Bus Interface Unit (BIU)

o Handles all data and address transfers on the buses.
o Components: Segment registers (CS, DS, SS, ES), Instruction Pointer (IP),
Instruction Queue (6-byte), Address Calculation.
2. Execution Unit (EU)
o Executes instructions fetched by the BIU.
o Components: ALU, general-purpose registers (AX, BX, CX, DX), control unit,
flags.

Would you like me to draw and send the block diagram image of 8086?

2b) What are the Flags in 8086?

There are 9 active flags in the 16-bit flag register of 8086, divided into status and control
flags:

 Status Flags:
o CF (Carry Flag)
o PF (Parity Flag)

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 o AF (Auxiliary Carry Flag)
o ZF (Zero Flag)
o SF (Sign Flag)
o OF (Overflow Flag)
 Control Flags:
o TF (Trap Flag)
o IF (Interrupt Enable Flag)
o DF (Direction Flag)

2c) Write Down the Difference Between 8085 and 8086 Microprocessor

Already answered above in a detailed table under question 1.

Would you like a summarized one-page PDF of this content for study or print?

Let’s answer your questions clearly and step by step.

Function of Opcode Pre-Fetch Queue in 8086

In the 8086 microprocessor, the Opcode Pre-Fetch Queue is a 6-byte instruction queue that
is part of the Bus Interface Unit (BIU).

Main Functions:

1. Increases Execution Speed (Pipelining):

While the Execution Unit (EU) executes instructions, the BIU fetches upcoming
instructions from memory and stores them in the queue. This allows both units to work in
parallel, increasing throughput.
2. Reduces Memory Access Delays:
Instructions are pre-fetched and ready in the queue, so the EU doesn't have to wait for
memory access.
3. Implements Instruction Pipelining:
This is a basic form of pipelining where fetching and execution overlap.
4. Clears on Jump/Branch:
If a branch (like JMP, CALL, etc.) occurs, the queue is flushed, and new instructions are
fetched from the new address.

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 Effect on Status Flags for the Following Instruction Sequence:
MOV AX, 1234H ; AX = 1234H
MOV BX, 0ABCDH ; BX = ABCDH
CMP AX, BX ; Compares AX - BX (1234H - ABCDH)

What Does CMP Do?

 CMP AX, BX subtracts BX from AX, i.e., 1234H - ABCDH, but does not store the result.
 It sets status flags based on the result of subtraction.

Subtraction:

AX = 1234H = 4660 (decimal)

BX = ABCDH = 43981 (decimal)

1234H - ABCDH = 4660 - 43981 = -39321 (2’s complement result)

This results in a negative value, so let's analyze what happens to the flags:

Flag Description Effect

CF (Carry) Set if there is a borrow Set (since AX < BX)
ZF (Zero) Set if result is 0 Clear (result ≠ 0)
SF (Sign) Set if result is negative (MSB = 1) Set
OF Clear (no overflow in signed
Set if signed overflow occurs
(Overflow) subtraction)
AF (Aux Can’t determine directly without nibble-
Affects BCD operations
Carry) level calc
Set if result has even parity (even #
PF (Parity) Depends on LSB of result
of 1’s)

Final Flag Status After CMP AX, BX:

Flag Status
CF 1 (Set)
ZF 0 (Clear)
SF 1 (Set)
OF 0 (Clear)
PF Depends on lower byte of result
AF Undetermined without exact bit-level subtraction

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Would you like me to explain how to calculate Parity Flag (PF) or Auxiliary Carry (AF) in this
context?

Certainly! Here's a detailed and beginner-friendly explanation of your questions, clearly

separated and explained with proper headings.

❶ Write an Assembly Language Program to Add Two Numbers of 8-bit Data

Stored in Memory Locations 4200H and 4201H, and Store the Result in 4202H
and 4203H

This program will:

 Add two 8-bit numbers from memory.

 Store the result as a 16-bit value (to handle carry/overflow) in two memory locations:
4202H (low byte) and 4203H (high byte).

; Assuming use of 8086 assembly language

MOV SI, 4200H ; Load source address

MOV AL, [SI] ; Load first number into AL
INC SI ; Point to 4201H
MOV BL, [SI] ; Load second number into BL
ADD AL, BL ; Add the two numbers, result in AL, carry in CF
MOV CL, 00H ; Clear CL to hold high byte (carry)

JC CARRY_SET ; Jump if carry flag is set

JMP STORE_RESULT

CARRY_SET:
INC CL ; If carry, set CL = 01H

STORE_RESULT:
MOV SI, 4202H
MOV [SI], AL ; Store lower byte of result
INC SI
MOV [SI], CL ; Store higher byte (carry if any)
HLT

Explanation:

 AL holds the result of addition.

 If there's a carry, we set CL = 1, and store it as the higher byte.
 So 4202H has the sum, and 4203H has the carry (if any).

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❷ Describe Arithmetic and Program Execution Transfer Instructions of 8086
Microprocessor

Arithmetic Instructions:

These perform mathematical operations like addition, subtraction, increment, and decrement.

Instruction Meaning
ADD A, B Adds B to A (A = A + B)
SUB A, B Subtracts B from A (A = A - B)
INC A Increments A by 1
DEC A Decrements A by 1
ADC A, B Add B + Carry to A
SBB A, B Subtract B + Borrow from A
CMP A, B Compares A and B (A - B, result not stored, only flags affected)
NEG A Two’s complement of A (0 - A)
MUL B Unsigned multiply (AL × B)
IMUL B Signed multiply

Program Execution Transfer Instructions:

These instructions change the flow of program execution.

Instruction Meaning
JMP label Unconditional jump to label
JE / JZ Jump if equal / zero flag is set
JNE / JNZ Jump if not equal / zero flag is not set
JC Jump if carry flag is set
JNC Jump if no carry
CALL Call a procedure (saves return address)
RET Return from procedure
LOOP Loop using CX register
INT Software interrupt

❸ What is MINIMAX Mode Operation of an 8086 Microprocessor?

The 8086 microprocessor can operate in two modes based on the pin MN/MX̅
(Minimum/Maximum mode):

Minimum Mode (Single Processor System):

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  Activated when MN/MX̅ = 1.
 Used when only one 8086 CPU is used.
 8086 directly generates all control signals like RD, WR, ALE, etc.
 Simple and cheaper design.

Think of this as "self-managed mode".

Maximum Mode (Multiprocessor System):

 Activated when MN/MX̅ = 0.

 Used when multiple processors or coprocessors (like 8087) are used.
 Control signals are generated by an external bus controller (like 8288).
 Allows coordination between multiple CPUs.

Think of this as "teamwork mode", needing a bus manager.

Feature Minimum Mode Maximum Mode

Pin MN/MX̅ High (1) Low (0)
System Type Single processor Multiprocessor
Control Signals By 8086 By external controller
Simplicity More simple More complex

Would you like a diagram of minimum vs maximum mode operation of 8086?

Certainly! Here's a clear and beginner-friendly explanation of both topics:

1. Explain Different Types of Registers in 8086

Microprocessor Architecture
The 8086 microprocessor has a number of registers, each serving a specific purpose. They are
grouped into the following main categories:

A. General Purpose Registers (GPRs)

Used for general data storage and arithmetic operations.

Register Description
AX (Accumulator) Used for arithmetic, logic, and data transfer. Commonly holds results.
BX (Base) Used as base pointer in addressing.

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 Register Description
CX (Count) Used as counter in loops and shifts.
DX (Data) Used in multiplication/division and I/O operations.

Each of these 16-bit registers can be split into 8-bit:

 AH/AL (high/low of AX)

 BH/BL, CH/CL, DH/DL

B. Segment Registers

Used to divide memory into segments for better memory management.

Register Description
CS (Code Segment) Points to the code segment (instructions).
DS (Data Segment) Points to the data segment.
SS (Stack Segment) Points to the stack segment (for push/pop).
ES (Extra Segment) Used for additional data storage or string operations.

C. Pointer and Index Registers

Register Description
SP (Stack Pointer) Points to top of the stack.
BP (Base Pointer) Used to access parameters in the stack (esp. in procedures).
SI (Source Index) Used in string operations (source string).
DI (Destination Index) Used in string operations (destination string).

D. Instruction Pointer and Flags

Register Description
IP (Instruction
Holds offset address of next instruction to be executed.
Pointer)
Contains status flags (like Zero, Sign, Carry, etc.) that indicate result of
FLAGS Register
operations or control processor behavior.

2. What Are the Features of 8086 Microprocessor?

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The Intel 8086 is a 16-bit microprocessor introduced in 1978. It was a powerful upgrade from
the 8-bit 8085.

Key Features:

Feature Description
Data Bus Width 16-bit (can handle 16 bits of data at a time)
20-bit (can address up to 1 MB of memory: 2²⁰ = 1,048,576
Address Bus Width
bytes)
Instruction Queue 6-byte prefetch queue (supports pipelining)
14 total: including 4 general-purpose, 4 segment, pointer/index,
Registers
IP, and FLAGS
Memory Segmentation Supports segment-based memory (code, data, stack, extra)
Minimum Mode (single CPU) and Maximum Mode
Operating Modes
(multiprocessor)
Clock Speed Typically 5, 8, or 10 MHz
Multiplication & Division Supports both unsigned and signed operations
Supports Assembly
Like MOV, ADD, SUB, MUL, JMP, CALL, etc.
Instructions
Supports Interrupts Hardware and software interrupts supported
I/O Address Space Separate 64 KB I/O space (via IN and OUT instructions)

If you want, I can also give you a diagram of 8086 register structure or internal architecture.
Would you like that?

Here's a detailed explanation of all three questions, with easy-to-understand language and
structured format:

1. What is the Maximum Memory Size That Can Be

Addressed by 8086?
Answer:

The 8086 microprocessor has a 20-bit address bus, which means it can generate 2²⁰ =
1,048,576 unique addresses.

Therefore, the maximum memory that 8086 can address is:

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 1 MB (1 Megabyte = 1024 × 1024 bytes)

How?

 8086 uses segment:offset addressing.

 It combines a 16-bit segment and a 16-bit offset to create a 20-bit physical address.
 So, memory address = (Segment × 10H) + Offset.

2. Explain the Working Procedure of 8255A

(Programmable Peripheral Interface) with Block Diagram
What is 8255A?

The 8255A is a Programmable Peripheral Interface (PPI) used to connect input/output

devices (like keyboards, LEDs, sensors, etc.) with the microprocessor (like 8086).

Features:

 3 I/O ports: Port A, Port B, and Port C.

 Port C can be split into two 4-bit ports: PC upper (PC7–PC4) and PC lower (PC3–
PC0).
 Can be programmed in 3 modes:
o Mode 0: Simple I/O
o Mode 1: Handshake I/O
o Mode 2: Bidirectional data transfer (only for Port A)

Block Diagram of 8255A:

┌────────────┐
│ Data Bus │ ←→ 8-bit Data Lines
└────┬───────┘
│
┌────────▼────────┐
│ Read/Write │ ←─ Control from CPU (RD, WR, CS)
│ Logic │
└────┬────┬───────┘
│ │
┌──────▼─┐ ┌▼────────┐
│Group A │ │ Group B │
│(PA + PCU)│(PB + PCL)│
└────┬───┘ └────┬────┘
│ │

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 ┌──▼──┐ ┌──▼──┐
│Port A│ │Port B│
└─────┘ └─────┘
┌──────────────┐
│ Port C │ ← Split into PC7-4 (PCU) and PC3-0 (PCL)
└──────────────┘

Working Procedure:

1. Control Word is sent by the CPU to configure ports (input/output).

2. Based on mode, ports behave accordingly:
o Mode 0: Output or input directly.
o Mode 1: Input/output with handshaking (uses Port C bits).
o Mode 2: Bi-directional communication (only for Port A).
3. CPU communicates through RD/WR/CS signals.
4. Data transfer between CPU and devices happens via ports.

3. Differentiate Between Hardware and Software

Interrupt
Feature Hardware Interrupt Software Interrupt
Triggering Triggered by an external device or Triggered by program instruction (like
Method hardware pin INT)
Keyboard press, Timer overflow, I/O
Examples INT 21H, INT 10H
device
Control Line Uses INTR, NMI pins in 8086 No hardware pin; internally executed
Speed Fast (real-time device interaction) Slower; depends on software logic
Perform BIOS/DOS functions or
Use Case Respond to external events
system calls
INTR is maskable, NMI is non- Cannot be masked, but can be
Masking
maskable controlled in code

Would you like me to draw and send you a labeled diagram of 8255A?

Here’s a simple and clear explanation for all three questions:

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 1. Explain the Block Diagram of the 7-Segment Display
Interface and Its Operations
What is a 7-Segment Display?

A 7-segment display is an electronic display device used to show decimal numbers (0–9) and
some hex digits (A–F) using 7 LEDs arranged in the shape of the number 8. Each segment is
labeled a to g.

--a--
| |
f b
| |
--g--
| |
e c
| |
--d--

Block Diagram (Basic Concept):

┌───────────────┐ ┌───────────────┐ ┌───────────────┐
│ Microprocessor│ ─────▶ │ Decoder/Driver│ ─────▶ │7-Segment Display│
└───────────────┘ └───────────────┘ └───────────────┘

Components:

 Microprocessor (e.g., 8086): Sends binary data to be displayed.

 Decoder/Driver (e.g., 7447): Converts binary/BCD data into segment signals.
 7-Segment Display: Lights up segments to display the number.

Operation:

1. Microprocessor sends binary-coded decimal (BCD) value to the decoder/driver.

2. The decoder activates specific segments (a–g) of the 7-segment display.
3. The display lights up the segments to form digits (like 0–9).

2. Discuss How Memory Chips and I/O Devices Are

Interfaced to a Microprocessor
Why Interface?

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To allow the microprocessor to read/write data to memory or I/O devices, they must be
properly connected and addressed.

Memory Interfacing:

 Address Bus: Selects a specific memory location.

 Data Bus: Transfers actual data.
 Control Lines:
o RD (Read): When microprocessor wants to read.
o WR (Write): When it writes data.
o MEMR/MEMW: Indicate memory read/write.

I/O Interfacing:

Two methods:

 Isolated I/O: Separate I/O and memory space. Use special instructions like IN and OUT.
 Memory-Mapped I/O: I/O devices are treated as memory locations.

How it works:

 Microprocessor uses address bus to identify the device/memory.

 Sends control signals to read or write.
 Data moves through the data bus.

3. Differentiate Between CALL and JMP Instructions

Feature CALL Instruction JMP Instruction
Jumps to a new location in
Purpose Calls a subroutine (procedure)
program
Return Address Stores return address on the stack Does not save return address
Used for altering normal program
Uses Used for calling reusable functions
flow
Related Must use RET to return back to main
No need for RET, it's just a jump
Instruction program
Instruction Type Two-step: CALL → Subroutine → RET One-step transfer of control
CALL 2000H (go to subroutine at JMP 3000H (jump to address
Example
2000H) 3000H)

Would you like a diagram of the 7-segment display interface with labels?

128 | P a g e
Let’s answer your questions one by one in a simple, clear way:

1. Write the Features of 8251 (USART) Memory

Interface
The Intel 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter)
chip used to interface serial I/O devices with the microprocessor.

Features of 8251:

1. Supports both asynchronous and synchronous transmission.

2. Can handle full-duplex serial communication.
3. Has a built-in baud rate generator (using external clock).
4. Provides error detection (parity, overrun, framing error).
5. Offers programmable character length, stop bits, parity bit.
6. Uses control word and mode word to configure transmission mode.
7. Supports transmitter ready (TxRDY) and receiver ready (RxRDY) status.
8. Has separate transmitter and receiver sections.
9. Communicates with microprocessor via data bus (D0–D7).
10. Uses RD, WR, CS, and RESET signals for control and memory interface.

2. Construct a Formula for Calculating Interfacing

Memory Chip Capacity and Size of Memory Locations
Memory Chip Capacity Formula:

To calculate memory chip capacity and address range:

Memory Capacity=2n bytes\text{Memory Capacity} = 2^n \text{ bytes}

Where:

 n= number of address lines used.

 Each memory location stores 1 byte (in byte-addressable memory like in 8086).

To calculate address range:

If a chip is K × 8, then:

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  It stores K × 1024 locations (Kilo = 1024).
 Address range = from 0000H to (K × 1024 - 1) in hex.

Example:

 An 8K × 8 EPROM = 8 × 1024 = 8192 = 2¹³ bytes

o So, it needs 13 address lines.
o Address range per chip = 0000H – 1FFFH (for 8K).

3. Interface Circuit of Two 8K × 8 EPROM and Two 8K

× 8 RAM Chips with 8086
Given:

 Two 8K × 8 EPROM = 2 × 8K = 16K EPROM

 Two 8K × 8 RAM = 2 × 8K = 16K RAM

Total = 32K Memory Interfaced

Address Map Suggestion (Even/Odd Bank for 8086):

Chip Address Range Chip Select Signal

EPROM 1 00000H – 01FFFH CS0 (Even bank)
EPROM 2 00001H – 01FFFFH CS1 (Odd bank)
RAM 1 02000H – 03FFFH CS2 (Even bank)
RAM 2 02001H – 03FFFFH CS3 (Odd bank)

Interface Circuit Overview (Simplified):

Address Bus (A0–A19)
│
┌───────────────┐
│ Address Decoder│ ◄── Decodes A15–A19 to generate 4 Chip Selects
└───┬────┬──────┘
│ │
┌───────▼────▼────────────┐
│ Memory Chips │
├─────────────────────────┤
│ CS0 → EPROM 1 (Even) │ ← A0 = 0

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 │ CS1 → EPROM 2 (Odd) │ ← A0 = 1
│ CS2 → RAM 1 (Even) │ ← A0 = 0
│ CS3 → RAM 2 (Odd) │ ← A0 = 1
└─────────────────────────┘

 A0: Used by 8086 to select even/odd bank.

 A13–A0: Used inside each chip for internal addressing.
 A15–A19: Sent to decoder to generate chip select signals.

Would you like me to draw and send you a diagram of this memory interfacing circuit for better
visualization?

Here is a simple and clear comparison between synchronous and asynchronous data
transmission:

Difference Between Synchronous and Asynchronous

Data Transmission
Feature Synchronous Transmission Asynchronous Transmission
Uses a common clock signal shared No shared clock; timing is managed
Clock Signal
between sender and receiver. using start/stop bits.
Data Data is sent in a continuous stream Data is sent one byte/character at a
Transmission or blocks. time.
Start and stop bits are used with each
Start/Stop Bits Not required (since clock is used).
character.
Slower, because of extra bits
Speed Faster due to continuous data flow.
(start/stop).
More complex (needs
Complexity Simpler (no need for external clock).
synchronization).
Used for high-speed communication Used for low-speed communication
Use Case
(e.g., networks, memory). (e.g., serial ports, keyboard input).
Examples Ethernet, USB, SPI RS-232, UART

Summary:

 Synchronous = fast, needs clock, efficient for large data.

 Asynchronous = simple, self-timed, good for small/irregular data.

Would you like a diagram to visualize the timing difference between them?
131 | P a g e
SESSION 2015-16
SEMESTER
Let’s go through these questions step by step:

Why is the Microprocessor Viewed as a Programmable

Device?
A microprocessor is considered a programmable device because it can execute different tasks
based on the instructions given to it by a program. It doesn’t perform a fixed, hard-coded
function. Instead, its actions are controlled by software that provides the instructions for the
microprocessor to follow.

Key reasons:

 The microprocessor's behavior can be changed by altering the program or software

instructions.
 It uses machine-level instructions, which can be written in high-level programming
languages like C, assembly, or even directly in machine code.
 The microprocessor executes a sequence of instructions, and depending on those
instructions, it can perform arithmetic, logic operations, control flow, and interact with
external devices.

How Does the Microprocessor Work?

A microprocessor works by following the fetch-decode-execute cycle (also known as the
instruction cycle). It interacts with the memory, inputs, and outputs, performing a series of
operations.

Basic Steps in Microprocessor Working:

1. Fetch: The microprocessor gets an instruction from memory.

2. Decode: The instruction is decoded to understand what action needs to be performed.
3. Execute: The action described by the instruction is executed (like performing a
calculation or moving data).
4. Store: The result may be stored in memory or sent to an I/O device.

This cycle repeats continuously to perform tasks.

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 What is Machine Cycle, Instruction Cycle, Fetch, and
Execute Cycle?
1. Machine Cycle:

The machine cycle is the time taken by the microprocessor to complete a basic operation like
reading, writing, or performing an arithmetic operation. It includes several clock pulses.

For example, the 8086 microprocessor needs 4 clock cycles for each machine cycle (this can
vary with different microprocessors).

2. Instruction Cycle:

The instruction cycle is the entire process that a microprocessor follows to fetch, decode, and
execute an instruction. The instruction cycle typically consists of multiple machine cycles.

Steps in an Instruction Cycle:

 Fetch the instruction (from memory).

 Decode the instruction.
 Execute the instruction.

The instruction cycle could take multiple machine cycles, depending on the complexity of the
instruction.

3. Fetch Cycle:

The fetch cycle is part of the instruction cycle and refers specifically to the process where the
microprocessor:

 Retrieves the instruction from memory.

 The program counter helps in pointing to the memory address from where the
instruction is fetched.

In this cycle:

1. The microprocessor sends the address to memory.

2. The instruction at that address is loaded into the instruction register.

4. Execute Cycle:

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The execute cycle is the part of the instruction cycle where the microprocessor executes the
instruction that was fetched and decoded. This could involve:

 Performing arithmetic or logical operations (e.g., ADD, SUB).

 Transferring data between registers or to/from memory.
 Jumping to a different instruction if needed (conditional or unconditional jumps).

Summary of Cycles:

 Machine Cycle: The basic cycle for a single operation (e.g., read/write).
 Instruction Cycle: The overall cycle that includes fetch, decode, and execute.
 Fetch Cycle: The cycle where the microprocessor fetches the instruction from memory.
 Execute Cycle: The cycle where the fetched instruction is executed.

Would you like a more detailed breakdown or diagram of these cycles?

Let's break down the answers to these questions one by one:

How is the Clock Signal Generated in 8086?

In the 8086 microprocessor, the clock signal is generated using an external oscillator connected
to the microprocessor. This clock signal is used to synchronize the various operations and cycles
of the microprocessor.

Clock Signal Generation Process:

1. External Oscillator: A crystal oscillator or an external clock generator is used to provide

a regular clock pulse.
2. The frequency of the clock is typically controlled by a crystal or an external clock
generator that provides a clock signal at a specific frequency.
3. This clock is fed to the Clock Input pin (CLK) of the 8086, and the microprocessor uses
this signal to perform its operations synchronously.

Clock Frequency in 8086:

 The 8086 can operate at a maximum clock frequency of 10 MHz in its original
configuration. However, the actual clock frequency depends on the version of the 8086
microprocessor and the external clock used.

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  Typically, the clock speed is half of the microprocessor’s internal processing speed due
to the internal pipeline architecture.

What is Addressing Mode?

Addressing mode refers to the way in which the operand (data) of an instruction is accessed. It
determines how the microprocessor identifies the memory location or register where the data is
stored or to be operated on.

Types of Addressing Modes:

 Immediate Addressing: Operand is directly specified in the instruction.

 Register Addressing: Operand is in a register.
 Direct Addressing: Operand is in a specific memory location.
 Indirect Addressing: Address is specified indirectly (using pointers or indices).
 Indexed Addressing: The address is computed by adding an index value to a base
address.
 Based Addressing: The address is computed by adding a base register value to the
operand’s address.

Determine the Addressing Modes for the Following

Instructions:
i) MOV CH, 8

This instruction moves the immediate value 8 into the CH register.

 Addressing Mode: Immediate Addressing

 Reason: The operand (8) is directly provided as part of the instruction.

ii) MOV AX, DS:START

This instruction moves the value from the memory location START in the data segment (DS) to
the AX register.

 Addressing Mode: Segmented Addressing (Based Addressing)

 Reason: The address is provided by using the segment register (DS) and a direct
memory location (START).

135 | P a g e
iii) MOV [SI], AL

This instruction moves the value in the AL register into the memory location pointed to by the
SI (Source Index) register.

 Addressing Mode: Indirect Addressing

 Reason: The operand’s address is indirectly specified by the SI register. The value in SI
points to the memory location.

Summary:

 MOV CH, 8: Immediate Addressing

 MOV AX, DS:START: Segmented Addressing (Based Addressing)
 MOV [SI], AL: Indirect Addressing

Would you like more details on any of these topics or another example?

Let's break down your questions and go through the answers step by step:

1. Explanation of PUSH, POP, and AAA Instructions

a) PUSH Instruction

The PUSH instruction is used to push data onto the stack. It decrements the stack pointer
and stores the operand (data) at the memory location pointed by the stack pointer.

 Syntax:
 PUSH operand
 Example:
 PUSH AX

This pushes the contents of the AX register onto the stack. The stack pointer (SP) is
automatically decremented, and the data is stored at the memory location [SS:SP].

b) POP Instruction

The POP instruction is used to pop data from the stack. It loads the operand from the stack
and increments the stack pointer.

136 | P a g e
  Syntax:
 POP operand
 Example:
 POP AX

This pops the data from the stack into the AX register. The stack pointer (SP) is
automatically incremented after the data is removed from the stack.

c) AAA (ASCII Adjust After Addition) Instruction

The AAA instruction is used to adjust the result of an ASCII addition operation. When
performing arithmetic operations on ASCII values, the result may not be valid as an ASCII
character, so the AAA instruction corrects the result.

 Syntax:
 AAA
 Example:
 ADD AL, 30H ; AL = '3' + '4' = 37H (incorrect ASCII)
 AAA ; Adjust the result for ASCII addition

After executing the AAA instruction, the result will be adjusted back into a valid ASCII
range.

2. How is the Physical Address Obtained from the Logical Address?

In the 8086 microprocessor, the logical address is composed of two parts:

 Segment Address: The 16-bit segment base address (points to the segment).
 Offset Address: The 16-bit offset (or displacement) from the segment base.

To obtain the physical address, the microprocessor combines the segment base and offset:

Formula:
Physical Address = (Segment Address × 16) + Offset Address

Where:

 Segment Address is the 16-bit segment base.

 Offset Address is the 16-bit offset from the segment.

3. Calculating the Physical Address

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Let's calculate the physical address for the following examples:

i) Segment Base Value: B186H, Offset: 0128H

Using the formula:

Physical Address = (Segment Address × 16) + Offset Address

1. Convert B186H to decimal:

B186H = 45446 (decimal)
2. Multiply the segment base by 16:
B186H × 16 = B1860H.
3. Add the offset (0128H):
B1860H + 0128H = B1988H.

Thus, the physical address is:

B1988H.

ii) ES: 882EH, DI: 0442H

Here, we need to calculate the physical address using ES (Extra Segment) and DI (Destination
Index):

1. Convert ES = 882EH to decimal:

882EH = 34958 (decimal)
2. Convert DI = 0442H to decimal:
0442H = 106 (decimal)
3. Multiply the segment base (ES) by 16:
882EH × 16 = 88280H.
4. Add the offset (DI):
88280H + 0442H = 88722H.

Thus, the physical address is:

88722H.

Summary of Calculations:

1. Segment Base B186H, Offset 0128H → Physical Address = B1988H.

2. ES: 882EH, DI: 0442H → Physical Address = 88722H.

Let me know if you'd like further clarification or more examples!

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Let’s break down your questions step by step:

1. Basic 8086 Bus Cycle

In the 8086 microprocessor, the bus cycle refers to the sequence of events that occur when the
processor communicates with memory or I/O devices. It includes the fetch, decode, and execute
stages, but in more detail, it specifically involves interactions with the address, data, and control
buses.

Basic 8086 Bus Cycle:

1. Address Cycle:
o The processor places the address of the memory location or I/O device on the
address bus.
o The memory read/write operation is then specified by the control bus.
2. Memory Cycle:
o If it's a read operation, data is retrieved from memory or I/O and placed on the
data bus.
o If it's a write operation, data from the data bus is written to memory or I/O.
3. Control Signals:
o The control bus carries signals such as MEMR (memory read), MEMW
(memory write), and IOR (I/O read), which control the operation of memory and
I/O devices.
4. Data Transfer:
o After the address is set, the appropriate data is either read from memory or
written into memory.

The 8086 microprocessor uses these bus cycles to handle operations like reading from or
writing to memory or performing I/O operations.

2. What Happens in the 8086 Processor When:

i) Overflow of Sum Occurs During Addition of Signed Numbers

In the 8086 microprocessor, when adding signed numbers, an overflow occurs if the result
exceeds the capacity of the destination register (i.e., it cannot fit in the register width).

 For example, adding two large positive signed numbers or two large negative signed
numbers might lead to a result that cannot be represented within the range of the signed
number format.
 Overflow Flag (OF): When an overflow occurs, the Overflow Flag (OF) in the flag
register is set to 1.
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Example:

 If you add 127 (7F in hexadecimal) and 127 (7F in hexadecimal) in an 8-bit register,
the result is 254 (FE in hexadecimal). However, 254 cannot be represented as an 8-bit
signed number (since the range of signed 8-bit values is from -128 to 127). Hence, the
overflow flag will be set.

ii) Overflow of Quotient Occurs During Division Operation

In 8086, the Overflow Flag (OF) also gets set when an overflow occurs during a division
operation. This happens if the result exceeds the storage capacity of the registers used for storing
the quotient and remainder.

 In 16-bit division (using DX:AX for the dividend), an overflow occurs if the quotient
cannot fit in the AX register or if the remainder cannot fit in the DX register.
 Overflow Flag (OF): If the quotient or remainder overflows, the Overflow Flag (OF) is
set to 1.

Example:

 If you divide a large dividend (e.g., FFFFH in DX:AX) by a small divisor (e.g., 2), the
quotient might not fit in the AX register, causing an overflow.

3. Content of Flag Register After Execution of Addition 65D1 and 2359

Let’s perform the addition of 65D1H and 2359H and examine the flag register.

1. Step-by-Step Addition:
2. 65D1H

 2359H

8B2AH

The result is **8B2AH** (which is a positive number).

2. **Flags after Addition**:

- **Carry Flag (CF)**: No carry occurs as the result fits within 16 bits.
Therefore, **CF = 0**.
- **Overflow Flag (OF)**: There’s no overflow because the result is within
the 16-bit signed range. Therefore, **OF = 0**.
- **Sign Flag (SF)**: The result **8B2AH** is positive, so **SF = 0**.
- **Zero Flag (ZF)**: The result is non-zero, so **ZF = 0**.

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- **Auxiliary Carry Flag (AF)**: No carry between bit 3 and bit 4 during the
addition, so **AF = 0**.
- **Parity Flag (PF)**: The result **8B2AH** has an even number of 1s in its
binary representation (**1000101100101010**), so **PF = 1**.

### **Flag Register Content After Addition**:

- **CF = 0**
- **OF = 0**
- **SF = 0**
- **ZF = 0**
- **AF = 0**
- **PF = 1**

---

### **4. Show the Contents of Memory Locations After Execution of `MOV
[SI], AX`**

#### **Given**:
- **DS = 1120H**
- **SI = 2498H**
- **AX = 53EFH**

Let’s break this down:

- **MOV [SI], AX** means that the contents of the **AX register** (which is
**53EFH**) will be moved to the memory location pointed to by the **SI
register**.

- **DS = 1120H** and **SI = 2498H**. The effective memory address is

calculated by combining **DS** and **SI**:

Effective Address = DS × 16 + SI = 1120H × 16 + 2498H = 11200H + 2498H = 13798H

- The contents of memory at address **13798H** will be **53EFH** (the value

in **AX**). Since **AX** is a 16-bit register, it will be split into two 8-
bit values and stored in consecutive memory locations:

- **Memory[13798H] = EF** (low byte of AX)

- **Memory[13799H] = 53** (high byte of AX)

---

### **Summary**:

1. **Basic 8086 Bus Cycle**: It involves the address cycle, memory cycle, and
data transfer cycle.
2. **Overflow in Addition of Signed Numbers**: The Overflow Flag (OF) is set
when the result exceeds the signed number range.
3. **Overflow in Division**: The Overflow Flag (OF) is set if the quotient or
remainder overflows.
4. **Flags after Addition**: The flags after adding **65D1H** and **2359H**
are **CF = 0, OF = 0, SF = 0, ZF = 0, AF = 0, PF = 1**.

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5. **MOV [SI], AX**: The contents of memory at **13798H** and **13799H** will
be **EF** and **53**, respectively, based on the values in **AX**.

---

Let me know if you need further clarification or examples!

Let’s address each question in detail:

1. Purpose of Interrupts and Interrupt Processing Flow

Purpose of Interrupts:

Interrupts are used in microprocessors to handle asynchronous events (events that occur
independently of the processor's current execution). When an interrupt occurs, the processor
temporarily suspends its current execution to handle the interrupt, processes it, and then resumes
its previous task.

Key Purposes of Interrupts:

 Improved efficiency: Instead of continuously checking if a certain condition is met, the

processor can focus on other tasks and only respond when an interrupt occurs.
 Real-time processing: Interrupts allow for fast responses to important events (e.g.,
hardware signals, I/O operations).
 Resource management: Interrupts help handle resource sharing, enabling multitasking
on microprocessors.

Interrupt Processing Flow:

Here is the general flow of interrupt processing:

1. Interrupt Occurs: When an interrupt signal is received (either from hardware or

software), the Interrupt Request (IRQ) is sent to the processor.
2. Processor Interrupt Acknowledgment: The processor checks the Interrupt Enable
Flag (IF) in the flag register. If enabled, the interrupt is acknowledged.
3. Context Saving: Before servicing the interrupt, the processor saves the current state (e.g.,
registers, flags) to the stack.
4. Interrupt Vector: The processor fetches the interrupt vector, which points to the
interrupt service routine (ISR) for the corresponding interrupt.
5. ISR Execution: The processor executes the interrupt service routine (ISR) associated
with the interrupt.
6. Context Restoration: After processing the interrupt, the processor restores the saved
context from the stack.
7. Return from Interrupt: The processor resumes execution from the point where it was
interrupted.

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Here’s a simple Interrupt Processing Flow Diagram:

+------------------+
| Interrupt Occurs |
+------------------+
|
V
+----------------------+
| Processor Acknowledges |
| the Interrupt |
+----------------------+
|
V
+------------------------+
| Save Context (Registers)|
+------------------------+
|
V
+--------------------------+
| Fetch Interrupt Vector |
+--------------------------+
|
V
+---------------------------+
| Execute ISR (Interrupt |
| Service Routine) |
+---------------------------+
|
V
+----------------------------+
| Restore Context |
+----------------------------+
|
V
+----------------------------+
| Return to Main Program |
+----------------------------+

2. Difference Between Maskable and Non-Maskable Interrupts

Maskable Interrupts (IRQ):

 Definition: Maskable interrupts can be disabled (masked) by the processor. This means
that the processor can temporarily ignore these interrupts.
 Example: Hardware interrupts, such as those for I/O devices, can be masked by
clearing the Interrupt Enable (IF) flag.
 Usage: These are used when the processor is busy with higher-priority tasks and needs to
ignore certain interrupts temporarily.

Non-Maskable Interrupts (NMI):

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  Definition: Non-maskable interrupts cannot be disabled by the processor, meaning they
always have priority and cannot be ignored.
 Example: Critical hardware errors, like power failure, are non-maskable interrupts that
need immediate attention.
 Usage: These are reserved for situations where immediate attention is required, like
power failure or system crash scenarios.

Key Differences:

Feature Maskable Interrupt Non-Maskable Interrupt

Masking Capability Can be masked (disabled) Cannot be masked
Priority Lower priority (can be delayed) Higher priority (immediate)
Examples I/O interrupts Hardware failure (power loss)
Processor Flag Can be cleared (IF flag) Always enabled (cannot disable)
Interrupt Type IRQ NMI

3. What is Pipelined Architecture? How is it Implemented in 8086?

Pipelined Architecture:

A pipelined architecture allows the processor to execute multiple instructions in parallel by

overlapping different stages of instruction execution. In this architecture, the CPU is divided into
stages, and each stage works on a different instruction.

 Stages of Pipeline:
1. Fetch: The instruction is fetched from memory.
2. Decode: The instruction is decoded to determine the operation.
3. Execute: The operation is executed (e.g., ALU operations).
4. Memory Access: Data is read from or written to memory if needed.
5. Write-back: The result is written back to the register.

This parallelism improves the instruction throughput of the CPU, increasing its performance.

Pipelining in 8086:

The 8086 microprocessor uses a form of pipelining, but it’s not as advanced as in modern
CPUs. The 8086 has a two-stage pipeline consisting of:

1. Pre-fetch Queue:
o The 8086 uses a 6-byte pre-fetch queue to store instructions that are fetched in
advance.
o While the current instruction is being executed, the next instructions are fetched
and stored in the queue.
2. Execution:
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 o After the instruction is fetched from the queue, the processor decodes and
executes it.
o The pre-fetch queue allows the processor to fetch the next instruction while the
current instruction is being executed, leading to efficient use of the CPU's time.

Although the 8086's pipelining is simple (it only uses a pre-fetch queue), it still improves
performance by overlapping fetch and execution cycles.

Pipelining in 8086:

 Fetch: While the current instruction is being executed, the next instruction is fetched and
stored in the pre-fetch queue.
 Decode: The instruction is decoded, and the CPU begins executing it.
 Execute: The instruction executes, but the next instruction is already ready to be
decoded.

Summary:

1. Interrupts allow the processor to handle external events efficiently. Interrupt processing
involves saving the context, processing the interrupt, and restoring the context.
2. Maskable Interrupts can be disabled by the processor, while Non-Maskable
Interrupts cannot be ignored and have higher priority.
3. Pipelined Architecture enables parallel processing of instructions, and in 8086,
pipelining is implemented using a pre-fetch queue that fetches instructions while others
are being executed.

Let me know if you'd like further clarification!

DMA Controller (Direct Memory Access Controller)

What is DMA?

DMA (Direct Memory Access) is a feature that allows peripherals (e.g., I/O devices like disk
drives, sound cards, etc.) to directly transfer data to or from the memory without the involvement
of the CPU. This reduces the CPU’s workload and speeds up data transfer.

DMA Controller:

The DMA Controller is a special hardware component that manages data transfer between I/O
devices and the system’s memory. It takes over control of the system bus to directly move data
between I/O devices and memory, bypassing the CPU, which speeds up data transfer and reduces
CPU overhead.

Architecture of the 8237 DMA Controller:

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The 8237 DMA Controller is an integrated circuit designed to manage DMA operations. It
provides channels for memory-to-memory, memory-to-peripheral, and peripheral-to-memory
transfers.

Architecture of 8237 DMA Controller includes the following key components:

 DMA Channels: 8237 has 4 independent DMA channels (Channel 0 to Channel 3) for
data transfer.
 Control Registers: These are used for configuring and controlling DMA operations.
 Request Line (DREQ): The line that an external device uses to request a DMA transfer.
 Acknowledge Line (DACK): The line used by the DMA controller to acknowledge that
a DMA request is accepted and data transfer can begin.
 Status Register: Contains flags to indicate the status of each DMA channel.
 Bus Control Lines: These are used to take control of the system bus and allow DMA
data transfer.

Here is the Block Diagram of the 8237 DMA Controller:

+------------------------+
| Control Registers |
+------------------------+
| Channel 0 | Channel 1 |
| Channel 2 | Channel 3 |
+------------------------+
|
+----------------------------+
| DMA Request (DREQ) |
| & Acknowledge (DACK) |
+----------------------------+
|
+----------------------+
| Memory/Peripheral |
+----------------------+
|
+------------------+
| CPU (Bus Cycle) |
+------------------+

Key Functions:

 DMA Request (DREQ): I/O devices use this line to signal that they need to transfer
data.
 DMA Acknowledge (DACK): When the controller acknowledges a request, data is
transferred.
 Channel Control: Each channel is independently controlled by the DMA controller to
facilitate transfers between devices and memory.

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 Interrupt Controller 8259A:

The 8259A is a programmable interrupt controller used to manage multiple interrupt sources in a
microprocessor system. It allows the CPU to handle interrupts more efficiently by prioritizing
interrupt requests and enabling/disabling specific interrupts.

Internal Organization of 8259A Interrupt Controller:

The 8259A interrupt controller provides a mechanism for handling interrupts in a system by
providing control over interrupt requests. It can manage multiple interrupt sources and prioritize
them.

Here’s the internal organization of the 8259A Interrupt Controller:

+-----------------------------------+
| Interrupt Control Registers |
+-----------------------------------+
| Command Register (ICW1, ICW2) |
| Interrupt Mask Register (IMR) |
| Priority Register (IRR) |
| End of Interrupt Register (EOI) |
+-----------------------------------+
| | |
| | |
+------------------------+------------------------+
| IRQ Lines |
+-----------------+ +-----------------+ +-----------------+
| IRQ0 (Timer) | | IRQ1 (Keyboard) | | IRQ2 (Cascade) |
+-----------------+ +-----------------+ +-----------------+
| |
V V
+-------------------------+
| CPU (INTERRUPT SERVICE) |
+-------------------------+

Key Components:

1. Interrupt Request Lines (IRQ0 to IRQ7): These lines receive the interrupt requests
from various peripherals. Each interrupt line corresponds to a specific device (e.g., IRQ0
for the timer, IRQ1 for the keyboard, etc.).
2. Interrupt Mask Register (IMR): It is used to mask (disable) specific interrupts. Each bit
in the IMR corresponds to an interrupt request line. If the bit is 1, the interrupt is
disabled; if 0, the interrupt is enabled.
3. Interrupt Request Register (IRR): This register holds the interrupt requests from
devices. It indicates which devices are requesting an interrupt.
4. Priority Register: This register holds the priority level of the active interrupt requests.
The 8259A uses a priority scheme to determine which interrupt to service first.
5. End of Interrupt (EOI) Register: This register is used to send an EOI signal to the
8259A when an interrupt service routine has been completed, signaling that the processor
can handle another interrupt.
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 6. Initialization Command Word (ICW1, ICW2, ICW3, ICW4): These are command
words that initialize the interrupt controller. ICW1 starts the initialization sequence,
ICW2 provides the interrupt vector base, ICW3 defines the cascade configuration, and
ICW4 sets the operating mode.

Features of 8259A:

 It can handle up to 8 interrupt sources (IRQ0 to IRQ7).

 Supports priority management: The controller allows the CPU to service interrupts in
order of priority.
 Programmable: The interrupt priority, masking, and other configurations are
programmable.
 Supports cascading of multiple 8259A controllers to handle more than 8 interrupt
sources (i.e., up to 64 interrupt requests).

Summary:

1. DMA Controller (8237) allows direct data transfer between memory and peripherals,
reducing CPU load. It includes channels for multiple data transfers.
2. Interrupt Controller 8259A efficiently manages and prioritizes interrupts from multiple
devices, with features like masking, priority management, and the ability to cascade
multiple controllers.

If you need more detailed information on any of these components, feel free to ask!

Operating Modes of 8255A (Programmable Peripheral Interface)

The 8255A is a versatile Programmable Peripheral Interface (PPI) used to interface the
microprocessor with I/O devices, enabling the microprocessor to communicate with peripherals
like keyboards, displays, sensors, etc. It has three primary operating modes:

1. Mode 0 (Basic Input/Output Mode)

 Purpose: This is the simplest mode of operation for interfacing the microprocessor with
I/O devices. It supports basic digital input and output operations.
 Operation:
o Each of the 8 pins of Port A, Port B, and Port C (which are divided into two 4-bit
halves) can be individually programmed as input or output.
o Data can be read from or written to the port.
o There is no handshake involved in this mode.

Example Use: A basic push-button interface for input or a simple LED control for output.

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2. Mode 1 (Strobed Input/Output Mode)

 Purpose: This mode is designed for devices that require data to be latched. It is suitable
for situations where a peripheral device (like a sensor or keyboard) needs to send data to
the microprocessor in a controlled manner using strobe signals.
 Operation:
o Data is transferred to or from the microprocessor via a strobe signal, which
controls when data is read or written.
o Port A or Port B operates in input or output mode, and Port C provides control
signals (such as the strobe signal) to synchronize data transfers.

Example Use: Interfacing with a keypad, where the microprocessor can read the keys when the
strobe signal is triggered.

3. Mode 2 (Bidirectional Bus I/O Mode)

 Purpose: This mode allows for bidirectional data transfer, making it suitable for
interfacing with devices that require two-way communication (e.g., data transfer between
the microprocessor and memory or other peripherals).
 Operation:
o Port A is used in this mode for bidirectional data communication.
o Port C controls the direction of data flow (input or output) using two control
signals (called Read/Write).
o It allows data to be written to or read from Port A in both directions, depending
on the control signals.
o This mode provides handshaking signals that control when data is transferred.

Example Use: A communication interface between the microprocessor and another device,
where both devices can send and receive data (e.g., communication with a printer).

Microprocessor Interface with Memory and I/O

Microprocessors typically communicate with memory and I/O devices through a system of buses
(address bus, data bus, and control bus). These buses are used to transmit the necessary
information to access memory locations or interact with I/O devices.

1. Microprocessor and Memory Interface:

The memory interface connects the microprocessor with the memory (RAM or ROM) of a
system. Here’s how it works:

 Address Bus: The microprocessor sends an address to the memory. This address
corresponds to a specific memory location.

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  Data Bus: The data is either written to or read from the specified memory location. The
data bus transmits this data.
 Control Bus: The control signals tell the memory whether the operation is a read or
write and when it should occur.

Steps to read data from memory:

1. The microprocessor places the memory address on the address bus.

2. It sends the read signal via the control bus to the memory.
3. The memory sends the data from the specified address back to the microprocessor over
the data bus.

Steps to write data to memory:

1. The microprocessor places the memory address on the address bus.

2. It places the data to be written onto the data bus.
3. The microprocessor sends the write signal to the memory via the control bus.
4. The memory stores the data at the specified address.

2. Microprocessor and I/O Interface:

I/O devices (such as keyboards, sensors, printers) are interfaced with the microprocessor using
various I/O ports (either directly or through peripherals like the 8255 PPI).

 Port-mapped I/O (PM I/O): The I/O devices are treated as if they are memory locations.
The microprocessor accesses them by placing their I/O address on the address bus.
 Memory-mapped I/O (MM I/O): The I/O devices share the same address space as the
memory. The microprocessor uses the same address and data buses to access both
memory and I/O devices.

Steps to read data from an I/O device:

1. The microprocessor sends the I/O address to the I/O device via the address bus.
2. The microprocessor sends a read signal to the I/O device through the control bus.
3. The I/O device places the data on the data bus, and the microprocessor reads it.

Steps to write data to an I/O device:

1. The microprocessor places the I/O address on the address bus.

2. The microprocessor places the data to be sent on the data bus.
3. The microprocessor sends a write signal to the I/O device via the control bus.

Example of interfacing an I/O device (8255):

 The microprocessor places the address of the 8255 in the address bus.

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  The 8255 peripheral can be configured to operate in different modes (Input, Output,
Bidirectional) depending on the requirements.
 The microprocessor communicates with the 8255 to send or receive data.

Summary:

1. 8255A Modes:
o Mode 0: Basic I/O.
o Mode 1: Strobed I/O (used for interfacing devices like keypads).
o Mode 2: Bidirectional Bus I/O (used for communication with devices needing
two-way data flow).
2. Microprocessor Interface with Memory:
o Involves the address, data, and control buses for accessing memory locations
(read/write).
3. Microprocessor Interface with I/O:
o Port-mapped I/O: Treats I/O devices as memory addresses.
o Memory-mapped I/O: Shares address space between memory and I/O devices,
enabling data transfer using the same bus system.

Let me know if you need further details!

1) Function of In-Service Register, Masking Register, and Interrupt Request

Register of 8259

The 8259 Programmable Interrupt Controller (PIC) is used to handle interrupt requests from
external devices. It has several important registers involved in managing interrupts:

1.1 In-Service Register (ISR)

 Function: This register keeps track of the interrupts that are currently being serviced.
 Working: When an interrupt request is acknowledged, the corresponding bit in the ISR is
set to 1. Once the interrupt is processed, the bit is cleared.
 Purpose: It ensures that interrupts that are being handled are not re-triggered.

1.2 Masking Register (MR)

 Function: The masking register is used to control which interrupt requests are enabled
or disabled.
 Working: Each bit in the register corresponds to a particular interrupt. If the bit is set to
1, the interrupt is masked (disabled). If the bit is set to 0, the interrupt is enabled.
 Purpose: It prevents the processing of interrupts that are not yet to be handled or
interrupts that should be ignored during certain operations.

1.3 Interrupt Request Register (IRR)

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  Function: The IRR holds the pending interrupt requests.
 Working: When an interrupt request (IRQ) is raised by an external device, the
corresponding bit in the IRR is set to 1. This register keeps track of all interrupts waiting
to be serviced.
 Purpose: It helps the interrupt controller keep track of multiple interrupt requests,
enabling the system to prioritize them and process them in order.

2) Features of 8254 Programmable Interval Timer

The 8254 Programmable Interval Timer (PIT) is used for time-delay generation and
frequency control in systems. Some of its features include:

 Three independent 16-bit counters: Each counter can be used to generate timed
intervals or specific frequencies.
 Programmability: The 8254 allows you to program the timer to operate in different
modes, such as generating square waves or time delays.
 Multiple Operating Modes: It supports several modes of operation like Mode 0
(Interrupt on Terminal Count), Mode 2 (Rate Generator), Mode 3 (Square Wave
Generator), etc.
 Clock Input: It uses an external clock frequency to generate time intervals.
 Counter Control Register: This register is used to configure the operation and behavior
of the timers.

3) Difference Between 8253 and 8254 Programmable Interval Timers

Both the 8253 and 8254 are programmable interval timers, but there are some differences
between them:

Feature 8253 8254

Counters 3 counters, 16-bit width 3 counters, 16-bit width
Output Mode Fixed output mode Programmable output modes
Slower in terms of clock
Speed Can handle higher clock speeds
frequency
More advanced modes (including more flexible
Mode Support Fewer operating modes
modes)
Internal
Less flexibility in control More flexible in terms of timing operations
Control
Compatibility Used in older systems Used in more modern systems

In short, the 8254 offers more flexibility and better performance compared to the 8253.

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4) Polling Method and Pipeline Method

4.1 Polling Method

 Definition: In the polling method, the CPU repeatedly checks (polls) the status of an I/O
device or peripheral to see if it needs attention. This happens in a loop, where the CPU
checks the device status and handles it if necessary.
 Disadvantage: The CPU spends time checking devices even when no interrupts are
present, which can waste processing power and reduce efficiency.

Example: The CPU checks every few cycles whether a device like a keyboard is ready to send
data.

4.2 Pipeline Method

 Definition: The pipeline method refers to the technique used in processor design where
multiple instructions are overlapped in execution to increase the CPU’s throughput. This
is different from the polling method, as it's related to the processor's internal handling of
instructions, not device management.
 Purpose: It allows multiple stages of instruction execution (fetch, decode, execute) to
happen simultaneously for different instructions, leading to better performance.

Example: An instruction is being fetched while another is being decoded and yet another is
being executed in parallel.

5) Operating Modes of 8254

The 8254 Programmable Interval Timer operates in several modes, each with a distinct
functionality:

Mode 0: Interrupt on Terminal Count

 In this mode, the timer generates an interrupt when the counter reaches zero (terminal
count).

Mode 1: Programmable One-Shot

 The counter generates a single pulse when triggered and then stops until triggered again.

Mode 2: Rate Generator

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  The counter generates a square wave at a programmable rate. The period of the wave can
be adjusted by the value in the timer.

Mode 3: Square Wave Generator

 Similar to Mode 2 but the output is a square wave, continuously generated until the
counter is reset.

Mode 4: Software Triggered Strobe

 The counter generates a strobe pulse on a specific count, controlled by software.

Mode 5: Hardware Triggered Strobe

 Similar to Mode 4, but the strobe is triggered by hardware input rather than software.

6) What Do You Mean by Assembly Language?

Assembly Language is a low-level programming language that is closely related to the

architecture of the computer. It uses mnemonics (human-readable representations) for machine
instructions, making it easier to write than pure machine code.

Advantages of Assembly Language:

 Speed: Assembly programs can be more efficient than high-level languages.

 Control: Provides direct control over hardware.
 Optimization: Allows fine-tuned optimization for specific systems.

Disadvantages of Assembly Language:

 Complexity: It is more complex and harder to read than high-level languages.

 Portability: Programs written in assembly are often hardware-specific, making them
non-portable.
 Time-Consuming: Writing in assembly is slower than writing in high-level languages
because of the low abstraction.

7) Microcomputer System with DMA Controller

Direct Memory Access (DMA) is a feature that allows peripherals to directly access memory
without involving the CPU, enabling faster data transfer.

Basic Architecture of a DMA System:

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 1. DMA Controller (8237): It manages the data transfer between I/O devices and memory.
2. CPU: Initiates the DMA process but does not control data transfer.
3. Memory: Stores data transferred by the DMA controller.
4. I/O Device: Sends or receives data to/from the memory.

DMA Operation:

 The CPU initiates a DMA transfer by informing the DMA controller of the data transfer.
 The DMA controller takes control of the system bus, temporarily suspends the CPU, and
transfers data directly between the memory and the I/O device.
 Once the transfer is complete, the DMA controller signals the CPU that the operation is
finished.

I hope this clarifies everything! Let me know if you need further explanations on any part.

SESSION 2014-15
1) Evolution of Microprocessor

The evolution of microprocessors has been driven by advances in technology, leading to smaller,
more powerful, and energy-efficient processors. Here is a brief overview of the evolution:

1.1 Early Microprocessors (1970s):

 Intel 4004 (1971): The first commercially available microprocessor with a 4-bit
architecture.
 Intel 8008 (1972): The first 8-bit microprocessor, marking the transition to more
powerful processing.

1.2 8-bit Microprocessors:

 Intel 8080 (1974): A significant advancement, it supported more instructions and more
memory, becoming popular in early personal computers and embedded systems.
 Zilog Z80 (1976): A widely used 8-bit processor with an architecture similar to the Intel
8080, but with better support for interrupt handling and I/O operations.

1.3 16-bit Microprocessors:

 Intel 8086 (1978): The first 16-bit microprocessor with a 16-bit data bus and 20-bit
address bus, allowing access to 1MB of memory. This was the precursor to the x86
architecture.
 Intel 80286 (1982): Improved upon the 8086, allowing for protected mode, which
enabled multitasking.

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1.4 32-bit Microprocessors:

 Intel 80386 (1985): Introduced 32-bit processing, enabling more powerful applications
and better multitasking with 4GB of addressable memory.
 Intel 80486 (1989): Featured an integrated floating-point unit (FPU) and improved
performance.

1.5 64-bit Microprocessors:

 Intel Pentium Pro (1995): Introduced 64-bit processing for better performance in
scientific and engineering applications.
 Intel Core i7 (2008): A high-performance 64-bit microprocessor that laid the foundation
for modern CPUs used in laptops, desktops, and servers.

As of today, processors are continually evolving with increased core count, higher clock speeds,
better energy efficiency, and support for parallel processing, such as in AMD Ryzen and Intel
Core series.

2) What Does It Mean by a Bus of a Microprocessor (8-bit, 16-bit, 32-bit)?

In microprocessor terminology, a bus refers to the physical pathways used for communication
between the processor and other components (such as memory and I/O devices).

 8-bit Bus: The processor can transfer 8 bits (1 byte) of data at a time. It can handle an
address space of up to 256 bytes of memory (with an 8-bit address bus).
 16-bit Bus: The processor can transfer 16 bits (2 bytes) of data at a time. It supports a
larger memory address space and allows for better performance in handling larger chunks
of data.
 32-bit Bus: The processor can transfer 32 bits (4 bytes) of data at a time, allowing it to
access a larger memory address space (4GB of RAM or more) and perform more
complex calculations.

Key Impact of Bus Width:

 Performance: A wider bus means the processor can transfer more data at once,
improving speed and processing power.
 Memory Addressing: The size of the address bus determines how much memory the
processor can address. For example, a 32-bit address bus can access up to 4GB of
memory.

3) Difference Between Physical Address and Logical Address

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  Physical Address:
o The actual address in the physical memory (RAM).
o This is the address that the memory management unit (MMU) translates the
logical address into.
 Logical Address:
o Also called virtual address, it is the address generated by the CPU during a
program's execution.
o The logical address is mapped to a physical address by the MMU using paging or
segmentation.

Key Differences:

Property Physical Address Logical Address

The actual address in physical memory
Definition The address generated by the CPU.
(RAM).
Mapping Mapped from logical address by MMU. Needs to be mapped to physical address.
Visible only to the software running on the
Visibility Visible to the memory hardware.
system.

4) Find the Memory Location Addressed by the Processor in 8086

Given:

 Code Segment (CS) = 4000H

 Instruction Pointer (IP) = 9F20H

To find the physical address addressed by the processor:

The formula to calculate the physical address is: Physical Address=(CS×16)+IP\text{Physical

Address} = (CS \times 16) + IP

So: Physical Address=(4000H×10H)+9F20H\text{Physical Address} = (4000H \times 10H) +

9F20H Physical Address=40000H+9F20H\text{Physical Address} = 40000H + 9F20H
Physical Address=49F20H\text{Physical Address} = 49F20H

So, the memory location addressed by the processor is 49F20H.

5) Show the Contents of Memory Locations after the Execution of MOV [SI], AX

Given:

 DS = 1120H

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  SI = 2498H
 AX = 53EFH

The MOV [SI], AX instruction moves the contents of the AX register into the memory location
addressed by the SI register.

Steps to calculate memory location:

 The effective address is calculated using DS and SI.

Effective Address=DS+SI\text{Effective Address} = DS + SI
Effective Address=1120H+2498H=3618H\text{Effective Address} = 1120H + 2498H =
3618H

So, the memory location is 3618H.

After executing MOV [SI], AX, the contents of memory location 3618H will be:

 3618H = EF (low byte of AX)

 3619H = 53 (high byte of AX)

Thus, memory location 3618H will contain EF, and 3619H will contain 53.

6) General Characteristics of 8086 Microprocessor

Here are some general characteristics of the 8086 microprocessor:

 16-bit Processor: The 8086 is a 16-bit microprocessor, meaning it processes 16 bits of

data at a time.
 16-bit Data Bus: It has a 16-bit data bus that can transfer 2 bytes of data at a time.
 20-bit Address Bus: This allows the 8086 to address up to 1MB of memory (2^20 =
1,048,576 bytes).
 Segmented Memory: The 8086 uses segmented memory, which divides memory into
segments like code, data, stack, and extra.
 Clock Speed: It operates at clock speeds of up to 10 MHz.
 Instruction Set: It supports a rich set of instructions, including arithmetic, logical, data
transfer, control, and string instructions.
 Pipelined Architecture: The 8086 has a pipelined architecture that allows for faster
instruction execution by fetching the next instruction while executing the current one.
 Multiple Modes: The 8086 supports both real mode and protected mode (although
protected mode is not used in the 8086).
 Interrupt Handling: It can handle interrupts through the 8259 interrupt controller.

These features made the 8086 a significant improvement over earlier microprocessors like the
8080 and laid the foundation for modern x86 architecture.

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Let me know if you need more clarification!

1) Goal for Instruction Set Design

The primary goal of Instruction Set Design is to create a set of instructions that allows the
processor to execute operations efficiently and effectively, balancing performance, ease of
implementation, and flexibility. Here are the key goals:

1. Simplicity: The instruction set should be easy for the programmer to understand and use.
Simple instructions reduce the complexity of writing and debugging code.
2. Efficiency: The instruction set should allow the processor to execute programs as
efficiently as possible. This involves optimizing for speed and minimizing the number of
cycles required to execute common operations.
3. Completeness: The set of instructions should be comprehensive enough to handle all
necessary computational tasks for general-purpose computing, including arithmetic,
logical operations, data movement, and control operations.
4. Flexibility: The instruction set should be flexible to accommodate a variety of
applications. It should support the ability to address memory, perform calculations, and
handle conditional logic.
5. Orthogonality: The instruction set should minimize exceptions and restrictions. Ideally,
different instructions should use the same modes of addressing and operand types,
allowing for generality and simplicity.
6. Size: The number of instructions should be balanced. Too few instructions may limit the
capability of the processor, while too many may lead to complex design and slow
execution.
7. Compatibility: The instruction set should be backward compatible to ensure that existing
programs can run on newer processors with minimal changes.

2) Explanation of XLAT, PUSH, POP, and XCHG Instructions

XLAT (Translate Instruction)

 Purpose: The XLAT instruction translates the value of the operand through a lookup
table in memory. It is used with the AL register and the BX register.
 Operation: The AL register contains the byte to be translated, and the BX register points
to the base address of the translation table. The value at the memory address BX + AL is
loaded into the AL register.
 Example:
 XLAT

This instruction is commonly used for tasks like character translation or encryption.

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PUSH (Push to Stack)

 Purpose: The PUSH instruction is used to place a 16-bit value onto the stack.
 Operation: It decrements the stack pointer (SP) and then stores the value at the location
pointed to by the stack pointer.
 Example:
 PUSH AX

This will push the contents of the AX register onto the stack, effectively saving its value.

POP (Pop from Stack)

 Purpose: The POP instruction is used to retrieve the 16-bit value from the top of the
stack.
 Operation: It loads the value from the stack into the specified register and increments the
stack pointer (SP).
 Example:
 POP BX

This will pop the value from the stack and store it in the BX register.

XCHG (Exchange)

 Purpose: The XCHG instruction swaps the contents of two registers or a register and a
memory location.
 Operation: It exchanges the values between the two operands.
 Example:
 XCHG AX, BX

This will swap the contents of the AX and BX registers.

3) Intel Predefined Interrupts of 8086

The 8086 microprocessor has a set of predefined interrupt vectors. These interrupt types are a
part of the interrupt system and are used for various hardware and software events.

Types of Predefined Interrupts:

1. Interrupt 0 - Divide Error: This interrupt occurs when there is a division by zero or an
overflow in division. It is triggered automatically by the processor if a division operation
results in an error.
2. Interrupt 1 - Single Step: This interrupt is used for debugging purposes. It causes the
processor to stop after each instruction is executed.

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 3. Interrupt 2 - Non-maskable Interrupt (NMI): This interrupt is used for critical errors
or hardware failures and cannot be disabled by masking.
4. Interrupt 3 - Breakpoint: Similar to the single-step interrupt, but it is triggered by a
INT 3 instruction in the program. It is also used for debugging.
5. Interrupt 4-15: These are software interrupts that the programmer can define and use
in the software for various system operations. They are called using the INT instruction
and are used for system calls, error handling, and custom interrupt handling.

These interrupts allow the processor to handle different events in an organized manner, allowing
for multitasking and error detection.

4) Function of TOY, READY, HOLD, and HLDA in 8085

These signals are part of the 8085 microprocessor's control signals used for managing the
operation of the microprocessor and its interaction with external devices.

TOY (Test Output):

 Purpose: This signal is used to indicate that the processor is in a specific state (usually
when the processor is executing an instruction).
 Operation: This is typically used in debugging or when the external system needs to
know the status of the processor.

READY:

 Purpose: The READY signal is used to synchronize the microprocessor with slower
external devices (like memory or I/O devices).
 Operation: If the external device is ready to send or receive data, the READY signal is
activated. If the device is not ready, the READY line stays low and causes the processor
to wait for the device to be ready before proceeding with further operations.

HOLD:

 Purpose: The HOLD signal is used by external devices to request control of the system
bus, typically when another device needs to perform some operations that require bus
access.
 Operation: When HOLD is activated, the microprocessor relinquishes control of the
system bus.

HLDA (Hold Acknowledge):

 Purpose: The HLDA signal is used to acknowledge the HOLD signal from external
devices.

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  Operation: When the microprocessor receives the HOLD signal, it acknowledges the
request by sending the HLDA signal, indicating that it has given up control of the system
bus.

These functions play a crucial role in ensuring proper synchronization between the
microprocessor and external peripherals, enabling efficient data transfer and system control.

1) Features of Intel 8259A (Programmable Interrupt Controller)

The Intel 8259A is a programmable interrupt controller used in the 8085 microprocessor system.
Some of its key features include:

 Supports Multiple Interrupts: It allows multiple interrupt lines to be connected to the

processor, enabling the handling of more than one interrupt request simultaneously.
 Priority Management: It allows for setting priorities for the interrupts. Higher-priority
interrupts can be serviced first.
 Cascade Mode: Multiple 8259A controllers can be cascaded to handle more than eight
interrupt lines.
 Maskable Interrupts: It provides the ability to mask (disable) specific interrupt requests
using control words.
 Non-Maskable Interrupts: Some interrupts cannot be disabled and are always serviced,
such as the Non-Maskable Interrupt (NMI).
 Programmable Control: The 8259A is programmable via control words, allowing you
to customize interrupt behavior.
 Interrupt Vectoring: It supports automatic interrupt vectoring, which determines which
interrupt service routine should be called based on the interrupt request.
 End of Interrupt (EOI): It generates an EOI (End of Interrupt) signal to inform the
microprocessor that the interrupt has been handled and the system can resume normal
operation.

2) Function of the Accumulator

The Accumulator (A register) is one of the most important registers in the 8085
microprocessor. It is used for:

 Arithmetic and Logical Operations: Most operations, such as addition, subtraction,

logical AND, OR, etc., are performed using the accumulator.
 Storing Results: The result of the operation is stored in the accumulator.
 Data Transfer: It is also used for moving data between registers and memory.
 Input/Output: The accumulator is involved in input and output operations, receiving
data from input ports or sending data to output ports.

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3) What is a Bus? Explain the Bus Structure of the 8085 Microprocessor

A Bus is a system of pathways used for communication between the microprocessor and other
devices (memory, I/O devices, etc.). The bus carries data, address, and control signals.

Bus Structure of the 8085 Microprocessor:

The 8085 microprocessor has three types of buses:

1. Data Bus (8 bits): This bus is used for transferring data between the microprocessor and
memory or I/O devices. The 8085 has an 8-bit data bus, meaning it can transfer 8 bits of
data at a time.
2. Address Bus (16 bits): The address bus carries the address of the memory or I/O device
that the processor wants to access. The 8085 has a 16-bit address bus, allowing it to
address 64KB (65536) memory locations.
3. Control Bus: The control bus is used to send control signals, such as read/write signals,
to indicate whether the processor is reading data from or writing data to memory or I/O
devices. It also includes signals like IO/M (memory or I/O operation) and RD (read) or
WR (write).

4) Features of 8085 Microprocessor

Some of the key features of the 8085 microprocessor include:

 8-bit Processor: It is an 8-bit microprocessor, meaning it processes 8 bits of data at a

time.
 5-Stage Pipeline: The 8085 executes instructions in a 5-stage pipeline, which helps it to
execute instructions efficiently.
 Clock Speed: The 8085 operates at clock speeds ranging from 3 MHz to 5 MHz.
 Address Bus: It has a 16-bit address bus, allowing it to address up to 64 KB of memory.
 Instruction Set: The 8085 has a rich instruction set with a variety of operations for
arithmetic, logic, control, and data transfer.
 Interrupt System: It has 5 interrupt lines, including maskable and non-maskable
interrupts, for handling external events.
 Serial I/O Control: The 8085 includes serial data transmission and reception capabilities
for communication with other devices.
 Low Power Consumption: The 8085 is designed to operate efficiently with low power
consumption, making it suitable for embedded systems.

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5) What Do You Mean by Pipelined Architecture? How is it Implemented in
8086?

Pipelined Architecture:

Pipelining is a technique used in modern processors to increase their throughput (the number of
instructions completed per unit of time). In a pipelined architecture, multiple instruction stages
are overlapped, allowing the next instruction to begin processing before the previous one has
finished.

For example:

 Stage 1: Fetch instruction

 Stage 2: Decode instruction
 Stage 3: Execute instruction
 Stage 4: Write-back result

Each of these stages works in parallel, so while one instruction is being executed, the next
instruction can be fetched and decoded, improving the overall processing speed.

Implementation in 8086:

The 8086 microprocessor uses a two-stage pipelined architecture:

 Fetch Stage: Fetches the instruction from memory.

 Execute Stage: Decodes and executes the instruction.

The pipelining in 8086 allows instructions to be executed more quickly because while the
processor is executing one instruction, it can fetch the next instruction, thus optimizing the
processor's overall performance.

6) What is Channel Property? Explain the Priority Between DMA Channels

Channel Property:

In DMA (Direct Memory Access) systems, a channel is the pathway through which data is
transferred between the memory and I/O devices without the involvement of the processor. Each
channel has specific properties that determine its capabilities, such as:

 Transfer Speed: How quickly data can be moved.

 Address Range: The range of memory addresses that can be accessed.
 Control Signals: The signals used to initiate and control data transfer.

Priority Between DMA Channels:

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In systems with multiple DMA channels, priority determines which channel gets access to the
system bus first when multiple DMA requests are made. Typically:

 Priority Arbitration: DMA channels are assigned priority levels, and higher-priority
channels are allowed to use the bus first.
 Round-robin or Fixed Priority: In some systems, DMA channels are handled in a
round-robin manner (equal priority), while in others, specific channels may be given
fixed priority based on their importance or type of data being transferred.

7) Describe the Function of Different DMA Triggers

In a DMA system, triggers are signals that initiate the data transfer process. Different DMA
triggers include:

 Software Trigger: A software-generated signal triggers the DMA transfer. This is

typically initiated by a program running on the microprocessor.
 Hardware Trigger: An external hardware device triggers the DMA transfer, such as a
peripheral device that signals that data is ready to be transferred.
 External Request Trigger: An external device, such as a sensor or other I/O devices,
generates a request for data transfer, causing the DMA controller to start the process.
 Chain Trigger: Multiple DMA channels can be triggered sequentially or in a chain,
depending on system requirements.

Each trigger type ensures that data transfers occur at the right time without unnecessary
processor intervention, improving system efficiency.

1. Define Opcode and Operand

 Opcode (Operation Code):

The part of a machine instruction that specifies the operation to be performed.
Example: In MOV A, B, the opcode is MOV.
 Operand:
The data or the address on which the operation is performed.
Example: In MOV A, B, the operands are A and B.

2. What Do You Mean by Assembly Language?

Assembly language is a low-level programming language that uses mnemonics to represent

machine-level instructions. It is specific to a particular computer architecture.

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 3. Advantages & Disadvantages of Assembly Language Over High-Level
Language

Advantages Disadvantages
Faster execution (more efficient) Hardware-dependent
Precise control over hardware Difficult to write and debug
Uses less memory Not portable across platforms
Useful in embedded systems Requires deep knowledge of architecture

4. Assembly Code: Input Two Integers and Print Result if Less Than 10
(8086 Example)

Note: 8086 doesn't have built-in I/O. The following is a conceptual code assuming the inputs are
in registers.

; Assume the numbers are stored in AL and BL

MOV AL, 03h ; First number
MOV BL, 05h ; Second number

ADD AL, BL ; AL = AL + BL

CMP AL, 0Ah ; Compare result with 10

JAE SKIP_PRINT ; If result >= 10, jump to skip

; Print operation here (conceptual)

MOV DL, AL ; Move result to DL for display
ADD DL, 30h ; Convert to ASCII
MOV AH, 02h ; DOS interrupt to display character
INT 21h ; Display result

SKIP_PRINT:

This example assumes the use of DOS INT 21h services. In a real system, user input/output
would require proper hardware interfacing or OS calls.

Would you like the same program written in C language or more advanced 8086 format with
input handling?

SESSION 2013-14
SEMESTER
Here’s a detailed and easy-to-understand explanation for your questions:

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 1. Explain the Programming Model of 8085 Microprocessor

The programming model of the 8085 microprocessor refers to the internal structure visible to
the programmer. It includes:

General Purpose Registers:

 B, C, D, E, H, L – 8-bit registers used for temporary storage.

 Can be used in pairs: BC, DE, HL (16-bit operations).

Accumulator (A):

 An 8-bit register used to store arithmetic and logic results.

 It's central to the ALU operations.

Flag Register:

 8-bit register with 5 active flags:

o S (Sign)
o Z (Zero)
o AC (Auxiliary Carry)
o P (Parity)
o CY (Carry)
 Reflects the result of arithmetic/logic operations.

Program Counter (PC):

 16-bit register that holds the address of the next instruction to be executed.

Stack Pointer (SP):

 16-bit register used to manage the stack (LIFO memory structure).

Instruction Register and Decoder:

 Temporarily holds the current instruction and decodes it.

Temporary Register:

 Used internally by ALU during operations.

Timing and Control Unit:

 Generates control signals for memory and I/O operations.

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 2. How Does a Microprocessor Differentiate Between Data and Instruction
Code?

A microprocessor uses control signals and memory organization to distinguish:

 Program Counter (PC) always points to the instruction code memory.

 Instructions are fetched from code memory.
 Operands (data) are fetched based on the instruction logic (from memory or I/O).
 Special control signals like IO/M̅ in 8085 help identify if it's a memory or I/O
operation.

So, it is the control logic and program flow that tells the microprocessor which bytes are data
and which are instructions.

✅ Machine Code for the Instruction JMP 2050H in 8085 Microprocessor

Instruction:

JMP 2050H

This instruction tells the 8085 to jump to the address 2050H unconditionally.

Machine Code:
C3 50 20
Byte Meaning
C3H Opcode for JMP addr16
50H Lower byte of address (2050H)
20H Higher byte of address (2050H)

Note: In 8085, addresses are stored in little-endian format (low byte first, then high byte).

Would you like a list of other jump instructions and their machine codes too?

Here is a clear and simple explanation of all your questions:

168 | P a g e
 1. What is a Flag in Microprocessor?

A flag is a 1-bit status indicator used to show the result of arithmetic and logic operations.

In the 8085 microprocessor, there are 5 important flags in the flag register:

Flag Meaning
S Sign Flag – Set if result is negative
Z Zero Flag – Set if result is zero
AC Auxiliary Carry – Used in BCD ops
P Parity – Set if result has even parity
CY Carry Flag – Set if carry is generated

2. Why Are Program Counter (PC) and Stack Pointer (SP) 16-bit Registers?

Because the 8085 has a 16-bit address bus, it can address up to 2¹⁶ = 65,536 (64 KB) memory
locations.
So, both PC and SP must be 16-bit to store any valid memory address between 0000H and
FFFFH.

 PC needs to hold the address of the next instruction.

 SP needs to point to a location in the stack (in memory).

3. What is the Function of Program Counter in 8085?

The Program Counter (PC) is a 16-bit register that holds the address of the next instruction
to be executed.

 After fetching an instruction, the PC is automatically incremented.

 During a jump, call, or return, PC is updated with a new address.

4. If the Memory Chip Size is 256 × 4 bits, How Many Chips Are Required to
Make Up 1K Bytes?

Step 1: Convert chip size to bytes

 256 × 4 bits = 1024 bits = 128 bytes (since 1 byte = 8 bits)

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Step 2: Required memory = 1K = 1024 bytes

Step 3: Calculate the number of chips:

Number of chips=1024 bytes128 bytes per chip=8\text{Number of chips} = \frac{1024\

\text{bytes}}{128\ \text{bytes per chip}} = 8

Answer: 8 chips are required

5. Give the Taxonomy of Memory

Memory taxonomy (classification) can be divided into:

Primary Memory:

 RAM (Random Access Memory) – Temporary storage

 ROM (Read-Only Memory) – Permanent storage

Secondary Memory:

 HDD, SSD, CD/DVD – Large storage, non-volatile

Cache Memory:

 Faster, smaller memory between CPU and RAM

Registers:

 Smallest, fastest memory inside CPU

Volatile vs. Non-Volatile:

 Volatile (RAM) loses data on power off

 Non-Volatile (ROM, HDD) retains data

6. Calculate the Address Lines Required for a 16K-byte Memory Chip

We use the formula:

Number of address lines=log 2(Memory size in bytes)\text{Number of address lines} =

\log_2(\text{Memory size in bytes})
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log 2(16K)=log 2(16×1024)=log 2(16384)=14\log_2(16K) = \log_2(16 × 1024) =
\log_2(16384) = 14

Answer: 14 address lines are required

7. How to Generate Read/Write Control Signals for Memory and I/O?

The 8085 microprocessor uses control signals and status lines to generate these:

For Memory:

 MEMR̅ (Memory Read)

 MEMW̅ (Memory Write)

Generated using:

 IO/M̅ = 0 → Memory operation

 RD̅ or WR̅ = Active → Based on read/write

For I/O:

 IOR̅ (I/O Read)

 IOW̅ (I/O Write)

Generated using:

 IO/M̅ = 1 → I/O operation

 RD̅ or WR̅ = Active

These signals are decoded using logic circuits (like NAND/AND gates) along with control/status
signals from the 8085.

Would you like diagrams for memory and I/O control signal generation too?

Here's a detailed and easy-to-understand explanation of each question:

a. Illustrate the steps of data flow when the instruction code (8AH – MOV D, A),
stored in location 2006H, is being fetched

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 Instruction: MOV D, A

Opcode = 8A (this tells the processor to move the contents of register A to register D)
Stored at memory location = 2006H

Steps of data flow during opcode fetch:

1. PC points to 2006H
o The Program Counter (PC) holds the address 2006H.
2. Address is placed on the address bus
o The 8085 microprocessor sends the address 2006H via the address bus (split as
high and low using multiplexing).
3. Memory Read (MEMR̅) signal is activated
o Tells the memory to place the data at 2006H on the data bus.
4. Opcode (8A) is placed on the data bus
o Memory puts the instruction 8A on the data bus.
5. Data is read by the microprocessor
o The instruction MOV D, A (8A) is loaded into the Instruction Register.
6. PC is incremented to 2007H
o PC is ready to fetch the next instruction.

This process is called the Opcode Fetch Cycle.

b. Explain the De-multiplexing Process of the Bus AD7–AD0

The 8085 uses time-multiplexed lines AD7–AD0 for:

 Address (A7–A0) in T1 state

 Data (D7–D0) in T2 and later states

De-multiplexing means separating address and data

How it's done:

1. The microprocessor places the lower address (A0–A7) on AD7–AD0 during T1.
2. A control signal ALE (Address Latch Enable) goes HIGH during T1.
3. An external latch (like 74LS373) captures this address using ALE.
4. When ALE goes LOW after T1, AD7–AD0 lines are now used as a data bus.
5. The previously latched address is held in the external latch for memory access.

Result: Address and data are separated using ALE and a latch.

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c. How the Physical Address is Obtained from a Logical Address (in 8086)

In 8086, addresses are 20-bit physical addresses, but instructions use 16-bit segment and 16-
bit offset (logical address).

Formula to convert:

Physical Address=(Segment×10H)+Offset\text{Physical Address} = (\text{Segment} \times

10H) + \text{Offset}

Example:

If CS = 1234H, and IP = 0020H,

Then physical address = 1234H × 10H + 0020H

=12340H+0020H=12360H= 12340H + 0020H = 12360H

This system allows addressing up to 1MB (2²⁰) of memory.

Let me know if you want a diagram for any of these steps!

Here are detailed and simplified answers to each of your questions:

1. Differentiate between accumulator-based and general-purpose register-based

microprocessor:

Feature Accumulator-Based General Purpose Register-Based

Uses a special register (accumulator) for all Uses multiple registers (AX, BX, CX,
Definition
arithmetic and logic operations. DX in 8086) for operations.
Less flexible; only accumulator used for More flexible; any general-purpose
Flexibility
operations. register can be used.
Speed Slower due to limited register use. Faster due to parallel use of registers.
Example Intel 8085 Intel 8086

2. Arithmetic Instructions of 8086 Microprocessor:

 ADD: Adds source to destination. Example: ADD AX, BX

 ADC: Add with carry. Example: ADC AL, BL
 SUB: Subtracts source from destination. Example: SUB AX, BX

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  SBB: Subtract with borrow.
 INC: Increment. Example: INC AX
 DEC: Decrement. Example: DEC CX
 NEG: Two’s complement. Example: NEG AL
 MUL: Unsigned multiply.
 IMUL: Signed multiply.
 DIV: Unsigned divide.
 IDIV: Signed divide.
 CMP: Compares two operands (like subtraction but doesn’t store result).

3. Purpose of DF (Direction Flag) and SF (Sign Flag) in 8086:

 DF (Direction Flag):
o Controls string operations.
o DF = 0 → Auto-increment (forward)
o DF = 1 → Auto-decrement (backward)
 SF (Sign Flag):
o Indicates sign of result.
o SF = 1 → Negative result
o SF = 0 → Positive result

4. 8086 Assembly Program to Add Two 128-bit Numbers Stored in Memory:

; Assume numbers are stored at DATA1 and DATA2, result at RESULT
; Each 128-bit number = 16 bytes = 8 words (16-bit)

MOV SI, OFFSET DATA1 ; Point to first number

MOV DI, OFFSET DATA2 ; Point to second number
MOV BX, OFFSET RESULT ; Point to result location
MOV CX, 8 ; 8 words = 128 bits
CLC ; Clear carry flag

ADD_LOOP:
MOV AX, [SI]
ADC AX, [DI] ; Add with carry
MOV [BX], AX ; Store result
INC SI
INC SI
INC DI
INC DI
INC BX
INC BX
LOOP ADD_LOOP

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5. Discuss the Address Bus and Data Bus Concepts of 8086 Microprocessor:

 Address Bus:
o 20-bit wide
o Can address up to 1MB (2²⁰) memory
o Unidirectional
 Data Bus:
o 16-bit wide
o Transfers data between CPU and memory/I/O
o Bidirectional

6. What is wrong with the MOV BL, CX instruction?

 Invalid Instruction
 BLis an 8-bit register; CX is a 16-bit register.
 You can't move data between different sizes directly.
 Correct way:
o MOV CL, BL (both 8-bit)
o MOV BX, CX (both 16-bit)

7. Describe the User-Defined Hardware Interrupts of 8086:

 8086 allows external devices to interrupt using INTR pin.

 When INTR is active, processor:
o Sends INTA signal (interrupt acknowledge)
o Expects interrupt type number from external device (0–255)
 Control jumps to address from Interrupt Vector Table.
 These are user-defined, not fixed like INT 0 (divide error), etc.

8. Describe the DMA (Direct Memory Access) Data Transfer Process:

 Used to transfer data between memory and I/O without CPU.

Steps:

1. Device sends DMA Request to CPU.

2. CPU responds with HOLD and goes into HOLD state.
3. DMA Controller takes control of buses.
4. Transfers data from memory to device or vice versa.

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 5. Returns control to CPU via HLDA (Hold Acknowledge).

DMA is faster and efficient for bulk data transfer, like from disk to memory.

Let me know if you'd like a diagram for DMA or interrupts!

SESSION 2012-13
CT
Sure! Let’s go through each question one by one in simple and clear language:

1. What are the advantages of an assembly language in comparison with

high-level languages?

Advantages of Assembly Language over High-Level Language:

Advantage Description
Speed Programs written in assembly are faster and use less memory.
Hardware Control Provides direct access to hardware (e.g., memory, ports).
Highly optimized programs can be created for time-critical
Efficiency
systems.
Size Code size is smaller compared to high-level language code.
Useful for Embedded
Ideal where resources (RAM/ROM) are limited.
Systems

However, assembly language is more difficult to learn and write than high-level languages like C
or Python.

2. Describe the three memory mapping techniques.

Memory Mapping Techniques:

1. Memory-Mapped I/O:
o I/O devices are treated as if they are memory locations.

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 o The same instructions (like MOV) used to access memory can be used to access
I/O.
o Takes up memory address space.
2. I/O Mapped I/O (Isolated I/O):
o Separate address space for I/O devices.
o Uses special instructions like IN and OUT.
o Does not consume memory address space.
3. Direct Memory Access (DMA) Mapping:
o Used when DMA controller directly transfers data between I/O and memory.
o Processor is bypassed temporarily.
o Efficient for large data transfer.

3. What is the function of the accumulator?

 The accumulator is a special-purpose register used in arithmetic and logic operations.

 It stores the result of operations like addition, subtraction, AND, OR, etc.
 In 8085, the accumulator is part of the register A.

Example:

MVI A, 05H
ADD B ; Adds value of register B to accumulator A

4. What is a bus? Explain the bus structure of the 8085 microprocessor.

What is a Bus?

 A bus is a group of wires used to transfer data, address, or control signals between
components of a computer system.

Bus Structure in 8085:

Bus Type Width Function

Address Bus 16-bit Carries memory or I/O address (A0–A15)
Data Bus 8-bit Carries actual data between CPU and memory/I/O
Control Bus Various Carries control signals like RD, WR, IO/M, etc.

Note: In 8085, A0–A7 are multiplexed with D0–D7 using AD0–AD7.

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 5. Calculate the address lines required for a 16K-byte memory chip for 8085
microprocessor.

Solution:

 1K = 1024 bytes
 16K = 16 × 1024 = 16384 bytes

We use the formula:

2^n = Number of memory locations

So:

2^n = 16384
=> n = log₂(16384) = 14

Answer: 14 address lines are required to access a 16K-byte memory chip.

Would you like the next set of questions explained?

Here are clear and direct answers to each of your questions related to microprocessor
fundamentals and interfacing:

1. What is the purpose of the TF and IF bits in the FLAG register?

Flag Full Form Purpose

Enables single-step execution. After each instruction, a trap interrupt
TF Trap Flag
occurs for debugging.
Interrupt Enables or disables maskable interrupts. IF=1 → Interrupts are allowed.
IF
Flag IF=0 → Interrupts are ignored.

2. Write the techniques for designing the main memory.

Techniques:

1. Memory Decoding:
o Full decoding: All address lines are used to select unique memory locations.
o Partial decoding: Only some address lines are used (simpler but may cause
mirroring).
2. Address Mapping:

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 oDivide address range for ROM, RAM, and I/O.
3. Memory Chip Selection:
o Use decoder circuits (e.g., 3-to-8 decoder) to select memory chips based on
address.
4. Banking:
o Used in 16-bit systems to combine 8-bit memory chips (even and odd banks for
high/low byte).

3. What is an instruction set? Describe data transfer instructions with

example.

 Instruction Set: A group of predefined commands that a microprocessor understands and

executes (e.g., MOV, ADD, JMP).

Data Transfer Instructions (8085 Examples):

Instruction Function
MOV A, B Copy content from register B to A
LDA 2500H Load accumulator from memory address 2500H
STA 2700H Store accumulator value to memory location 2700H
MVI C, 0AH Move immediate data (0A) into register C

4. Explain RIM and SIM instructions.

Instruction Meaning Function

Read Interrupt - Checks status of interrupt lines (RST7.5, 6.5, 5.5) - Reads
RIM
Mask serial input data
Set Interrupt
SIM - Enables/disables interrupt lines - Sends serial output data
Mask

5. Explain INTR instruction in detail and give the difference from other
hardware interrupts.

INTR (Interrupt Request):

 A general-purpose, maskable interrupt.

 Triggered by external devices.
 Checked only after the execution of each instruction.
 CPU sends INTA (Interrupt Acknowledge) if accepted.

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  Requires external hardware to provide the instruction to execute (usually via data bus).

Difference from other hardware interrupts:

Interrupt Maskable Vector Address Provided Internally?

INTR Yes (external device provides it)
TRAP No
RST7.5, 6.5, 5.5 Yes (fixed vector addresses)

6. Explain the meaning of pending interrupts.

 A pending interrupt is an interrupt request that has occurred but hasn’t been serviced
yet because:
o Interrupts are disabled (IF=0).
o CPU is currently executing a higher priority interrupt.
o Instruction cycle hasn’t reached a point to check for interrupts.

7. Explain in detail the interfacing of an input device with microprocessor

8085.

Steps for Input Device Interfacing:

1. Connect device (e.g., keypad, sensor) to microprocessor via I/O ports.

2. Use 8255 PPI or dedicated input port.
3. Microprocessor issues IN instruction to read input.
4. Device sends data to data bus, which is read into accumulator.

8. Design an interfacing circuit to read data from an A/D converter using the
8255A in memory-mapped I/O.

Block Diagram Summary:

 8255A Port A connected to A/D converter output.

 Port C used for control signals: Start of Conversion (SOC), End of Conversion (EOC).
 Port B (optional): status read.
 Connect 8255A to data bus and control lines.
 Use memory address decoder to assign address range to 8255.

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Example Memory Map:

 Port A: 8000H (data)

 Port C: 8002H (control)
 Control Word Register: 8003H

Code Example:

MVI A, 98H ; Control word to initialize 8255

STA 8003H ; Write to control register

MVI A, 01H ; Send SOC signal

STA 8002H ; Write to port C

WAIT: IN 8002H ; Poll EOC bit

ANI 80H
JZ WAIT

IN 8000H ; Read converted data from port A

Would you like a diagram of this interfacing circuit?

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