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Spi Verilog TB

This document contains a testbench for a digital design module written in Verilog. It initializes signals, toggles a clock, and simulates the behavior of the module by generating random input data. The testbench checks for the completion of operations through a 'done' signal after each input is processed.

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11 views1 page

Spi Verilog TB

This document contains a testbench for a digital design module written in Verilog. It initializes signals, toggles a clock, and simulates the behavior of the module by generating random input data. The testbench checks for the completion of operations through a 'done' signal after each input is processed.

Uploaded by

anglelathow
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

module tb( );

reg clk = 0, rst = 0, newd = 0;


reg [11:0] din = 0;
wire [11:0] dout;
wire done;

always #10 clk = ~clk;

top dut (clk, rst, newd, din, dout, done);

initial begin
rst = 1;
repeat(5) @(posedge clk);
rst = 0;

for(int i = 0; i < 10; i++)


begin
newd = 1;
din = $urandom;
@(posedge dut.s1.sclk);
newd = 0;
@(posedge done);
end

end

endmodule

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