8202008 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 20, NO.

4, JULY/AUGUST 2014

Design Challenges in Silicon Photonics

Wim Bogaerts, Member, IEEE, Martin Fiers, Member, IEEE, and Pieter Dumon, Member, IEEE

Abstract—Silicon photonics is rapidly gaining maturity in high- photonic design automation and discusses the different aspects
bandwidth optical communication, with applications in datacom, of the design gap in silicon photonics.
access networks, and I/O for bandwidth-intensive electronics. Also, We approach this from the point of view of electronic de-
applications are emerging in spectroscopy and sensing. To get the
best performance out of the photonics, co-integration with electron- sign automation (EDA) [7]. Today’s electronics design methods
ics is needed: side-by-side, stacked, or on the same chip. However, allow for a functional approach based on proven component li-
the combination of photonics and electronics introduces a range braries provided by foundries in process design kits (PDK). This
of new problems on the design side: Codesign and cosimulation of foundry approach is already adopted by photonics at R&D level
complex photonic and electronic circuits, tolerance to variability, through several multi-project-wafer services [8]–[11], which
and verification algorithms that can handle photonic circuits. We
will discuss these challenges and give an outlook on how tools need start offering photonic PDKs that enable photonic designers
to evolve to address the needs of photonic-electronic IC designers. to follow a similar design flow. Still, the functionality of these
PDKs is limited, and real photonic-electronic codesign capabil-
Index Terms—Silicon photonics, design.
ity is still missing.
In this paper, we will discuss our view on what constitutes
I. INTRODUCTION the design gap of silicon photonics, and offer perspectives on
the capabilities that are required to close this gap in a satis-
ILICON photonics is rapidly gaining traction as a tech-
S nology platform for complex photonic integrated circuits
(PIC). The technology is enabled by the infrastructure devel-
factory way, such that it becomes possible to design silicon
photonic+electronic circuits for different applications.
First, in Section II, we will give a short background on silicon
oped for silicon electronics, making it possible to define optical
photonics technologies, which we need to analyze in Section III
waveguide circuits with unparallelled precision. Moreover, the
what is needed to enable a photonic+electronic codesign flow.
material system with its high index contrast supports submicron
We will highlight several key challenges: the richness of infor-
waveguides with sharp bends, allowing for dense integration of
mation in a photonic signal that propagates through a waveguide
optical building blocks on one chip. This makes silicon pho-
(Section IV), the need for some multiphysics effects to be han-
tonics the first platform that can accommodate thousands of
dled at the circuit level (Section V), the extreme impact of
photonic components on a single chip [1], [2].
both manufacturing and operation variability on the operation
The main industrial drive for silicon photonics is in optical
of some silicon photonic circuit elements (Section VI), layout
interconnects [3], where optical links should replace electrical
and routing of photonic circuits (Section VII), handling of pho-
links on 10 cm to 2 km spans [4]. Here, the photonics serves the
tonic parasitics (Section VIII) and finally verification algorithms
needs of the electronics, enabling ever larger data bandwidths.
that can handle the peculiarities of optical waveguide circuits
But the potential of silicon photonics, and photonic integrated
(Section IX).
circuits in general, extends to many other applications in spec-
troscopy, sensing [5], and medical diagnostics [6]. For some of
these applications, integration with electronics is needed to pro- II. SILICON PHOTONICS
vide control and read-out functionality. Many strategies exist to
Silicon photonics is a logical evolution of the photonic IC
co-integrate the photonics and the electronics: on one chip, or
technology that emerged in the 1980s. On a PIC, light is pro-
by co-integrating chips. But functionally the photonics and the
cessed and routed on a chip by means of optical waveguides .
electronics behave as a single complex circuit.
There are several material systems for PICs: doped glass, III–V
However, there is a very wide gap between what the tech-
semiconductors, polymers, silicon, and others, each its own ad-
nology can deliver, and the functionality engineers can design
vantages, and all in active use today. Silicon’s key differentiator
and simulate in complex photonic-electronic circuits: Today’s
is the high refractive index contrast in the silicon-on-insulator
design methods and tools are not up to the task. This paper aims
(SOI) platform. This enables tight confinement of light in sub-
to provide some perspectives on the upcoming challenges in
micron waveguide cores, and bends with a radius of only a few
micrometer [12]. This allows integration of many more func-
Manuscript received October 7, 2013; revised December 2, 2013; accepted tional optical building blocks on a single chip.
December 17, 2013. Date of publication December 23, 2013; date of current Unlike in complimentary metal–oxide–semiconductor
version February 14, 2014. (CMOS) electronics, where all functions are executed with a
The authors are with the Photonics Research Group, Ghent University—
IMEC, Department of Information Technology, Gent 9000, Belgium (e-mail: combination of transistors, resistors, diodes and capacitors, the
[email protected]; [email protected]; pieter.dumon@ elementary building on a PIC are quite diverse and impose
imec.be). different requirements. First of all, light should be guided in
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. low-loss waveguides. Distribution and routing also requires
Digital Object Identifier 10.1109/JSTQE.2013.2295882 efficient splitters and waveguide crossings. Coupling light
1077-260X © 2013 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution
requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
BOGAERTS et al.: DESIGN CHALLENGES IN SILICON PHOTONICS 8202008

on and off chip to optical fibers is also a quite challenging

task, especially with submicron silicon waveguides. This is
made more difficult by the fact that optical fibers support two
polarizations of light, but on-chip waveguides are typically
polarization sensitive.
Light covers a wide spectrum. Most PIC technologies are
designed to support the telecom wavelength bands in the
near infrared around 1310nm and 1550nm. For applications in
wavelength-division multiplexed (WDM) communication, sens-
ing or spectroscopy, efficient wavelength filters are needed, con-
sisting of optical delay lines or resonators [13].
Essential functions involve opto-electronic conversion. Con-
verting optical signals into electrical ones can be done with a Fig. 1. Today’s photonic design flow: Ideally, one starts with system specifi-
cation and designs on a progressively detailed level down to the physical layout.
photodiode, which in silicon photonics is usually implemented With verification and testing, one moves again to the behavioral level. However,
in Germanium [14]. Electrical signals can be imprinted on an it is often needed to switch from physical to behavioral and back in mid-flow, or
optical carrier using phase or amplitude modulation; this can even move back to an earlier stage in the flow to perform additional component
optimization.
be done by modifying electrical carrier densities in a silicon
waveguide with an embedded diode or capacitor [15]. Lasers as
a light source can be integrated monolithically in III–V tech- Fig. 1 sketches the stages in a photonic design flow. It starts
nology platforms, but in silicon the light source has to be either at the same level as an electronic flow: specifying the system
bonded [16] or coupled off-chip. requirements. From that, a circuit is composed, and that needs
Fabrication of silicon photonics can build on the infrastruc- to be simulated. On-chip photonic circuit simulation tools are
ture developed for CMOS electronics. This technology is now only now coming of age [19]–[24], and have not been stressed
capable of defining deep submicron features with unprecedented to handle potential complexity of the thousands of mixed active
accuracy in large volumes. the use of silicon as a base material and passive photonic elements supported by silicon photonics
makes reuse of these manufacturing tools possible, but photon- technology. This does not even involve cosimulation with elec-
ics imposes different demands on the processes. Layer thick- tronic circuits, as we discuss further in Section II.
nesses can be different for waveguides than for transistors, and There had never been a real need for large-scale photonic
optical quality (e.g., unwanted absorption, scattering at rough- circuit simulators until the advent of silicon photonics. Also,
ness) is now an important additional requirement. Also, silicon in the first decade of silicon photonics, research was largely fo-
photonic waveguides are extremely sensitive, which imposes cused on physical simulations to construct the photonic building
nanometer-scale tolerances on the fabrication process. Because blocks needed for future circuits. This poses sufficient modeling
of process-induced variability, wavelength-selective filter func- and design challenges in its own right: the high refractive index
tions are difficult to fabricate exactly on spec [17], and therefore contrast often requires brute-force full-wave electromagnetic
will require some form of active compensation. simulations. Full-vectorial brute-force electromagnetic number
For these controlling and driving functions the photonics will crunching of physical geometries is still the most applied de-
require integration with electronics. This can be either monolith- sign method for individual building blocks [25]–[29], or al-
ically, incorporating optical and electrical elements in the same ternatives based on mode expansion [30], [31] and propaga-
wafer-scale process [18], or it can be through hybrid or 3-D tion [32]. These computationally expensive methods replace
integration. As photonic chips become more complex, the elec- the more approximate methods used for low-contrast material
tronic functions will become more integrated, and this imposes systems. And as already mentioned, the high contrast also intro-
requirements on the design side. duces very low tolerance to any variation in geometry. This
makes optimizing devices a computationally intensive task,
and difficult to extract accurate behavioral models for use in
circuit simulations. Therefore, photonic circuit design still in-
III. PHOTONIC VERSUS ELECTRONIC DESIGN volves a lot of physical design iterations of individual building
Today’s photonic IC design is a largely fragmented land- blocks.
scape, largely separated from the world of EDA. With the in- Electronic design automation, on the other hand, has evolved
creasing requirements for electronic control and driver circuitry, to facilitate design of complex circuitry consisting of a lim-
and the integration of optical links in high-speed interconnects, ited set of standard building blocks. To some extent, this has
the design process between photonic and electronic circuits gone at the expense of all-out physical optimization: individual
needs to be integrated. This will require an efficient codesign transistors are not being optimized in the circuit design stage.
flow, including cosimulation between the photonic and elec- Rather, the transistors are being modeled using a behavioral
tronic domain. Given today’s ratio between the photonic IC and model based on prior physical models, theory, and parameters
electronic IC industries, the most likely codesign scenario is extracted from measurements. This is more efficient and has
an integration of photonic capabilities into one or more EDA proven to be accurate, so why is this approach not applied in
environments. photonics?
8202008 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 20, NO. 4, JULY/AUGUST 2014

One of the challenges lies in compiling accurate behavioral accept the richness of photonics, and address some of the key
models for photonic building blocks. As already discussed in challenges discussed in this paper. First steps in that direction
the previous section, photonic circuits consist of a variety of have been made [38], but these do not necessarily scale to all
active and passive building blocks. In addition, most of these photonics applications. This tighter design integration can be
blocks exhibit a behavior that is wavelength-dependent, and in accomplished by native support, or by interfacing with photonic
many cases strongly dependent on temperature and other ef- design tools. Recent developments are progressing in that di-
fects. These effects should be incorporated in the component rection, with schematic editing, mask layout, verification and
model in order to reliably simulate the circuit. We’ll discuss the exporting to a photonic circuit simulator driven from a standard
wavelength-dependence in more detail in the next section, and EDA environment [39].
the influence of temperature in Section V. A problem with com- In the following sections, we describe a number of challenges
pact behavioral models is often their limited validity range: they in more detail, highlighting some fundamental differences be-
only work for a given set of parameters. If the designer moves tween photonics and electronics that make codesign not possible
out of the valid parameter range (either intentionally, or because today, unless with significant approximations. We do this from
of variability effects), additional physical simulations might be the perspective of EDA tools: what needs to be supported, on
required. Ideally, these should be triggered automatically, with- top of the existing electronic design capabilities, to design and
out requiring the user to set up a new simulation environment. simulate photonic integrated circuits.
Today, only a few tools enable this kind of hierarchical model-
ing, and only to a limited extent [21], [33]–[35].
The next step in the photonics design flow is generating the IV. CHALLENGE: RICH SIGNALS
mask layouts for fabrication. This process is disjoint from the Typical simulations of electronic circuits are based on SPICE
circuit design (if any circuit design is actually done outside of a or similar engines, tracking voltages, and currents through the
conceptual schematic), and usually executed in a separate tool. circuit. For analog circuits, the time stepping, which can be
Support for automatic place and routing of photonic blocks is adaptive, is typically one order of magnitude smaller than fastest
minimal. The reason for this will be discussed in Section VII. signals that are expected in the circuit. Depending on the appli-
Quite often, the technology imposed restrictions and limitations cation, this is megahertz to tens of gigahertz.
on the component layout, and this can have an impact on the Photonic circuits handle light, which is basically a very high
actual performance. Especially when designing custom layouts frequency electromagnetic wave, with an oscillation frequency
(which is still the most common way of photonic design), some around 200 THz. Compared to electronic phenomena, as well as
physical simulation might also be needed at the layout level to the data rates of high-speed communications (25-40 Gb/s) this
evaluate the effects of the fabrication process, or to optimize is extremely fast. Simulating the propagation of an optical wave
functionality [36]. through a circuit simulation would require too much time and
Verification of the mask layout is usually done with EDA resources for practical use. Even when simulating an optical link
verification tools, but this is not straightforward as photonic at 40 Gb/s, it would require 10000 samples per bit to capture
layout elements are very unlike typical manhattan-oriented elec- the waveform accurately.
tronic features, with many curvilinear features. Also, extracting Luckily, in most cases the exact shape of the optical wave-
photonic circuit elements from the layout is difficult: Layout- form is not required, as the high-frequencies are generally used
versus-schematic verification is a significant challenge. Verifi- as carrier wavelengths that are modulated at “electronic” speeds.
cation challenges are discussed in Section IX. A photonic-electronic circuit simulation can therefore run with
In the photonic design flow, it is often still necessary to come the same time stepping. For an optical point-to-point link (laser-
back to physical simulation in a later stage in the design flow. modulator-waveguide-photodetector) it suffices to track the in-
Once aspects like variability and parasitics are incorporated into tensity envelope of the optical signal, which could be repre-
the design flow, this will often require additional physical sim- sented by a single number per time step in the circuit simulation.
ulations. This back-and-forth switching between the different But amplitude is a relatively poor representation of light in an
levels in the design flow is error prone, as it often requires a optical circuit, so more information (expressed in floating point
redefinition of the problem in different simulation tools. While numbers) needs to be exchanged to describe the optical signal.
this is not a fundamental problem of photonic design, good data In practice, the required amount of data depends on which ap-
exchange between tools will be essential for a successful design plication and which phenomena one wishes to capture. This is
flow [33]. An integrated flow where transitions between between illustrated in Fig. 2 and in Table I.
design steps is largely automated is therefore desirable. This is As light is a wave, knowledge of the phase is essential to cap-
an area where EDA has paved the way, and where some early ture electromagnetic interference, needed for interferometers or
photonics solutions are appearing [27], [34], [37]. optical resonators. Mechanisms such as phase modulation can
Enabling a design flow for complex PICs will also need also be modeled in the system. Now two numbers need to be
to integrate electronic design. This is a sine qua non if pho- communicated between components in the circuit simulation.
tonic+electronic codesign is to succeed. Today’s EDA tools When phase is used, it is often needed to know the wavelength
support much larger complexity, and integrate more tightly as well, especially with the use of optical wavelength filters.
the transition from circuit design to layout. To bring pho- In addition, as some waveguides can support multiple Eigen-
tonic design into an electronic design flow, EDA tools need to modes, these add another two numbers that need to be handed
BOGAERTS et al.: DESIGN CHALLENGES IN SILICON PHOTONICS 8202008

can be represented by a single S-matrix, which only needs to be

calculated once [23], [43].
The signals need to be passed on between components, which
requires connections through optical pins or ports. Again, these
concepts are different than in electronics, but more similar to
planar microwave/RF design: optical interfaces of components
typically consist of an open-ended waveguide to which another
waveguide needs to be attached. For this attachment to work,
the other waveguide should match the component’s optical port
in waveguide cross section and orientation, to ensure a seamless
interface that does not excite reflections or unwanted scatter-
ing. Also, as already mentioned above, optical waveguides can
carry multiple modes, so this modal information should also be
available in the ports: the scattering matrix should be a gener-
Fig. 2. Information in optical signals. On the horizontal axis, the amount of alized scattering matrix that covers every combination of port
information per simulation time step is presented, while on the vertical axis the
richness of phenomena is illustrated. The amount of information is expressed and mode. These concepts are used for both RF and optical
as “numbers,” i.e. how many floating-point numbers are needed to represent the waveguide circuit design, but of course there are the vast differ-
instantaneous signal at any given time. ences in frequency/wavelength, which resulted in tools that are
optimized for either one or the other.
There is no straightforward solution to incorporate the rich-
over. Usually, a waveguide has at least 2 guided modes, corre- ness of photonic signals into an electronic circuit simulator.
sponding to the TE and the TM polarization. For optical links Simulating electrical circuits in a photonic simulator (e.g. based
with wavelength-division multiplexing, we therefore need these on scattering matrices) is possible, but these will never meet the
four numbers for each wavelength channel. The quantity of performance of today’s SPICE simulators, and have no track
information that needs to be passed between components per record to displace the proven tools. The solution is interfacing
time step in an optical circuit increases quite rapidly, but up simulators for the electronic and photonic domain. In a first
till now the number is still manageable in electronic simulators approximation this can be done using waveform exchange. A
and an optical waveguide connection between two components complete mixed-signal solution where separate photonic and
could be implemented as an array of signal lines. This approach electronic simulations are run in lockstep would be a good so-
can scale up to 8 or 16 WDM channels. lution, but will be a challenge to implement.
However, for accurate simulations a sufficiently fine sampling
of the optical spectrum would be needed. this would allow to
capture crosstalk in WDM links with good accuracy, but also V. CHALLENGE: MULTIPHYSICS
model signal degeneration due to optical dispersion. Sampling Photonics design is essentially multiphysics design. Photonic
the spectrum can rapidly multiply the amount of numbers needed circuit elements interact in various ways with the light but are
with 10 or 100. also affected by other quantities. Apart from the optical domain,
How to propagate these huge amount of numbers through two domains that should be handled as well at the circuit level
a large photonic circuit? In electronic circuits, signal propaga- are temperature and electronic carrier densities.
tion can be accelerated by modified nodal analysis (MNA) [40]. Silicon photonic waveguide elements are significantly af-
Circuits can be reduced using Kirchhoff’s conservation laws. fected by temperature. This means that outside temperature vari-
Unfortunately, while these effort-flow techniques can be ap- ations should be compensated by thermal tuners (i.e. heaters).
plied in other domains (thermal, fluidics, mechanics), photonic This can require a local temperature control with an accuracy
simulation does not follow the same formalisms . MNA requires better than 0.1 K. When applied to a wavelength-selective device
signal quantities that meet power conservation laws (e.g., Volt- this corresponds to a wavelength shift in the response of about
age × Current corresponds to Power). There is no equivalent 10 pm, which can be enough to detune the device [44], [45].
set of quantities to describe optical signals, but there are tech- In addition to outside temperature fluctuations, there can also
niques that allow conversion from scattering-wave formalisms be self-heating: a modulator based on a diode or capacitor will
to MNA [41]. One possible implementation is elaborated by generate heat during operation. Lasers are especially power hun-
Gunupudi et al. in [42]. gry, but also driver electronics can create hot spots that affect
On the other hand, it is possible to reduce large photonic cir- the photonics. Handling the thermal problem at the circuit level
cuits by aggregating passive linear circuit elements. These can is not trivial, as it requires advance knowledge of the physical
be described as a node with a scattering matrix (S-matrix) be- layout of all components, and solving the thermal distribution
tween the input and output ports [23], [24]. Typically, photonic across the chip in sync with the circuit simulation.
circuits consist of larger aggregates of passive circuit elements Electrical carriers also affect the photonic circuits. In silicon
(waveguides, splitters, wavelength filters, ...) that have a linear, the change of free carrier density will result in a change of both
but wavelength dependent, behavior. As long as no active or the refractive index of the silicon as well as its optical absorp-
nonlinear element is present, an aggregate of passive elements tion [46]. This can be used intentionally (e.g., in electro-optic
8202008 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 20, NO. 4, JULY/AUGUST 2014

TABLE I
AMOUNT OF INFORMATION (EXPRESSED IN FLOATING POINT NUMBERS) NEEDED PER TIME STEP WHEN PROPAGATING DIFFERENT TYPES OF SIGNALS

modulators) to modulate signals, but it can also be uninten- VI. CHALLENGE: VARIABILITY
tional. Accidental doping of an optical waveguide, or incorrect
annealing steps might change the local carrier density. The up- The high refractive index contrast of silicon photonics makes
side of carrier-induced effects it that they are typically locally it possible to confine light in a submicron waveguide core.
confined, and that they can be directly controlled by the elec- However, the effective refractive index of the waveguide core
trical circuits connected to the optical circuit. However, carriers is strongly governed by the actual geometry of the cross
can also be generated by the light itself. Even though silicon is section. For a rectangular cross section, this is the width and
quite transparent for optical wavelengths beyond 1.2μm it can height, but also the slope of the sidewalls.
still absorb two photons at the same time (two-photon absorp- To illustrate this more clearly, let us look at a ring resonator.
tion or TPA). This effect is weak, but scales with the intensity this is an optical resonator where the resonance condition de-
of the light. For high optical power, TPA will generate carriers pends on the optical roundtrip length of the ring waveguide, and
that will change the optical properties of the circuit. In addi- this in turn depends on the actual geometry of the waveguide.
tion, the thermalization and recombination of the carriers will Small width or height variations will induce a significant shift
heat up the waveguide from the inside out, and will also in- in the resonance wavelength: for a width change of 1nm, the
duce a change in refractive index. On top of TPA, most silicon wavelength will shift approximately 1nm, which can span more
waveguides also suffer from some linear losses by defects in the than one channel in a WDM system.
lattice structure and at the etched sidewalls.Similar to TPA, this Temperature can be used to tune wavelength-selective de-
absorption induces changes in refractive index. All these sec- vices, so in principle, heating a ring resonator can compensate
ondary non-linear effects are very difficult to include in a circuit for some fabrication imperfections. However, it takes a 12K
model, especially because they have relaxation times on very temperature increase to compensate for 1nm fabrication varia-
different length scales: Free carriers thermalize and recombine tion. Therefore, fabrication precision should be very accurate,
on ns-scale, while thermal effects dissipate on a μs scale. but also, at the component and circuit design stage tolerances
On top of carrier-induced and thermal nonlinearities, silicon should be taken into account [44], [48].
also has an intrinsic nonlinear response to the optical field. The Therefore, the effects of variability should be considered in
Kerr effect also induces a change in refractive index, and like the design stage. It is possible to optimize components at the
TPA this scales with the optical intensity in the waveguide [47]. physical level for tolerance against geometric variations, espe-
Unlike carrier-based or thermal nonlinearities, the Kerr effect is cially if the distributions and the correlations of these varia-
virtually instantaneous. While this makes it somewhat easier to tions are known through careful monitoring of the fabrication
handle in a circuit simulation (little or no memory effects) it can process [17]. This typically requires intensive 3-D electromag-
result in very different responses to optical pulses: short pulses netic simulations, and a careful analysis to translate geometric
with a high peak powers will provoke a different response than variability into functional variability. Also, at the circuit level
longer pulses with a lower peak power, even with the same pulse variability can be addressed in the design phase. For instance,
energy. wavelength filters can be made athermal by adding compensa-
Nonlinear optical phenomena significantly complicate circuit tion circuits [49], [50], or multiple copies of a device can be
modeling: because of the nonlinearity, new frequencies will be added to the circuit as a form of redundancy.
generated in the optical spectrum. In a WDM system with a set of A key challenge is the efficient simulation of circuits with
fixed wavelengths, nonlinearities might cause new wavelengths variability: taking into account statistics and correlation be-
to appear, which should somehow be captured by the circuit tween effects, a given distribution of variable parameters must
model, even if only to ascertain that they will not impact the be propagated through the circuit. This could be done through
performance of the circuit. Monte-Carlo simulations, but careful choice of the parameter
BOGAERTS et al.: DESIGN CHALLENGES IN SILICON PHOTONICS 8202008

Fig. 4. Different parasitic light paths can severely affect the performance of a
Fig. 3. Variability in photonic design. Both fabrication related as well as photonic integrated circuit.
operation sources of variability affect the physical structure. This should be
propagated to the circuit design level to allow an accurate prediction of the
actual yield of the entire device. tical waves have a phase, in some cases it is also needed that
the length of the interconnections can be set exactly, to control
interferences. These are not straightforward, but probably be
space is needed to avoid an unmanageable number of simu-
enabled by existing custom electronic P&R tools.
lations. Getting closure for the variability in photonic circuits
However, probably the largest challenge is that the photonic
covers much more effects than the exploration of slow and fast
circuit is typically only defined in a single layer. But routing a
corners used in electronic design.
complex circuit on a single layer is not straightforward, and of-
Ultimately, the outcome of a variability analysis is a predic-
ten impossible without crossing interconnections. Fortunately,
tion of the circuit yield. The propagation of variability from
photonic waveguides can be engineered to cross without exces-
nominal devices to circuit yield is illustrated in Fig. 3.
sive loss and crosstalk [54], but routing algorithms need to take
this into account and minimize the number of crossings. While
VII. CHALLENGE: MASK LAYOUT it is possible to make multi-layer circuits, efficient optical vias
Photonic layouts are quite different from electronic layouts. are difficult to implement in a high-contrast material system,
As the propagation of electromagnetic waves is entirely gov- this comes with serious performance and integration penalties.
erned by the geometry, this needs to be accurately controlled.
While electronic building blocks usually consist of rectangles VIII. CHALLENGE: PARASITICS
(without considering assist features or optical proximity correc- Today’s waveguide circuits are usually designed by compos-
tions), photonic device layouts consist of curvilinear shapes to ing them of ideal building blocks. However, just as in electronics,
define smooth waveguide bends. there are parasitic mechanisms that can disturb the operation of
Silicon photonic waveguides are typically fabricated in a sin- the circuit. Some of these parasitics could already be simulated
gle device layer of crystalline or amorphous silicon embedded in at the design stage. Most of the unwanted effects include light
oxide. However, different patterning layers can be defined with that does not end up in the place where it is supposed to be.
different etch depths [13], and sometimes additional material is This parasitic light can interfere constructively or destructively,
added to the device layer [51]. Given the high sensitivity to geo- complicating the calculation of the actual net result of the para-
metric variations, very accurate overlay between these different sitics.
patterns is required. Also, parasitic effects of patterning must Some examples of photonic parasitic effects are shown in
be corrected with suitable proximity corrections [52]. Optimiz- Fig. 4. They include (back)reflections at discontinuities [55],
ing the lithography conditions for a specific type of pattern is [56], distributed scattering at roughness, unintended coupling to
not really possible. Unlike critical layers in electronic designs, adjacent components and excessive absorption and stray light
photonic waveguide layers often contain a mix of isolated and propagating in cladding modes or the substrate. In addition,
dense features of different dimensions and shapes. Also, local optical nonlinearities can be considered as parasitics, as devices
and global density plays an important role in pattern fidelity [53]. models might not take into account local high intensities within
Today’s silicon photonic circuits all rely on tiling to guarantee a building block.
a uniform pattern density, but some photonic components rely
on larger unetched areas (e.g., arrayed waveguide gratings and
echelle gratings [13]). IX. CHALLENGE: VERIFICATION
Another difficulty is placement and routing (P&R). Photonic At the end of the design flow the layout should be verified
waveguides need to observe a minimum bend radius to avoid before it is sent for manufacturing. Like in electronics, the first
high propagation losses. Also, sufficient spacing is needed be- line of verifications is a design rule check of the mask layers,
tween routing waveguides to avoid evanescent coupling. At the to verify minimum critical dimensions, overlays and density
interfaces with the component ports, the routing waveguides checks. Such rules are already in use in today’s photonic design
also need to match the port’s waveguide geometry, as well as flows, making use of the tools available for electronic DRC [57],
angle, to avoid backreflections and scattering. Given that op- although some photonic design tools support DRC specifically
8202008 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 20, NO. 4, JULY/AUGUST 2014

photonic design cannot always be captured in an abstract model.

EDA tools should also facilitate curvilinear design and verifica-
tion tools need to be extended to support photonic concepts for
functional verification.

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[Online]. Available: http://www.ipkiss.org Department of Information Technology (INTEC) at
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Circuits, San Francisco, CA, USA, Jan. 2012, vol. 8265. tonics at Ghent University, and coordinates the activ-
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