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Laser Photonics Rev., 1–20 (2014) / DOI 10.1002/lpor.201300183

Abstract Planar waveguides with ultra-low optical propaga-

tion loss enable a plethora of passive photonic integrated cir-
cuits, such as splitters and combiners, filters, delay lines, and
components for advanced modulation formats. An overview
is presented of the status of the field of ultra-low loss wave-
guides and circuits, including the design, the trade-off between
bend radius and loss, and fabrication rationale. The character-
ization methods to accurately measure such waveguides are
discussed. Some typical examples of device and circuit ap-
plications are presented. An even wider range of applications
becomes possible with the integration of active devices, such

ARTICLE
as lasers, amplifiers, modulators and photodetectors, on such

REVIEW
an ultra-low loss waveguide platform. A summary of efforts to
integrate silicon nitride and silica-based low-loss waveguides
with silicon and III/V based photonics, either hybridly or hetero-
geneously, will be presented. The approach to combine these substrate is discussed and an application example of a high-
integration technologies heterogeneously on a single silicon bandwidth receiver is shown.

Ultra-low loss waveguide platform and its integration with

silicon photonics
Martijn J. R. Heck1,∗ , Jared F. Bauters2 , Michael L. Davenport3 , Daryl T. Spencer3 ,
and John E. Bowers3

1. Introduction large physical distance. Even more specific, the input and
output nodes of the fibers used in these applications are
The inventions of the laser and the optical fiber have been preferably close to each other to reduce footprint and to
pivotal to the success of the field of photonics in many appli- increase the level of control and stability. In practice often
cations. First among these is optical telecommunications, the whole system needs to be in the same box, on the same
where the low-loss optical fibers can guide the modulated card, in the same package or, ultimately, on the same chip,
laser signal for distances in excess of 100 km, without the to improve performance metrics such as size, weight and
need for repeaters. But fibers are also used for other appli- power consumption (SWaP). To this end fiber coils are of-
cations, e.g., as distributed sensors for real-time structural ten used, but these do not scale down to the package and
monitoring or to set up ubiquitous interconnected sensor chip level and they do not provide the low cost and high
networks. All of these applications make use of the fact that volume manufacturing advantages that are needed. Higher
the low propagation losses of about 0.2 dB/km for standard levels of integration will be required for the most demand-
single-mode fiber (SMF), operating at wavelengths around ing applications, particularly if cost is an issue. Additional
1.55 μm, allow a signal to travel tens of kilometers and con- key advantages of photonic integration are the polarization
nect various nodes, e.g., transmitters, receivers and sensors, stability, the lithographic precision of the design of delay
that are distributed over a large area and distance. lines, and the elimination of large coupling losses between
Other fiber-optic based applications, such as fiber-optic functional components.
gyroscopes, variable-delay lines, optical buffers for packet Advances in photonic integrated circuits (PICs) are be-
switching, opto-electronic oscillators, and narrow-band fil- ing driven by the ever-increasing demand for bandwidth
ters, also make use of the low propagation losses of the in telecommunications. Typically, routing, switching and
optical fiber. However, the key difference with telecommu- filtering functions are performed by PICs fabricated on a
nications and sensor applications, as described above, is silica-based or silicon nitride based platform [1]. In such a
that the propagation is exclusively used to bring a delay to platform, doped silica, silicon oxynitride (SiON), or sto-
the signal, not to bridge two nodes that are separated by a ichiometric silicon nitride (Si3 N4 ) is used for the light

1
Department of Engineering, Aarhus University, Finlandsgade 22, 8200 Aarhus N, Denmark
2
Aurrion Inc., USA
3
Department of Electrical and Computer Engineering, University of California Santa Barbara, USA
∗
Corresponding author: e-mail: [email protected]


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2 M. J. R. Heck et al.: Ultra-low loss waveguide platform and its integration with silicon photonics

guiding core. The core is embedded in a silicon oxide

upper and lower cladding. Typically, such PICs are fab-
ricated on thermally oxidized silicon wafers. Only passive
components and thermo-optic tuners are available in the
silica-based platforms.
For transceiver applications, active components, such
as lasers, high-speed modulators and detectors are required.
The indium phosphide (InP) based integration platform is
ideally suited for this application, since these lasers operate
in the wavelength range of 1250 nm – 1600 nm, cover-
ing the low-loss transmission windows in an optical fiber.
This platform has rapidly gained maturity over the last two
decades and integration complexity has increased exponen- Figure 1 Overview of planar waveguide propagation loss as a
tially [2], driven by demanding high-bandwidth long-haul function of bend radius. Data for silica and silicon nitride before
applications [3, 4]. InP-based PICs are also moving into 2008 (red, open), recent silicon nitride (red, solid) [16–38], silicon
shorter reach and higher volume applications, e.g., data- (blue) [39–43], indium phosphide (green squares), and gallium
com, enabled by cost effective fabrication technologies [5]. arsenide (green triangles) [44–46, 76] are given. Straight wave-
The lowest-cost and highest-volume approach how- guide loss data are shown at 60-mm radius. The bend radius is
ever is the silicon-on-insulator (SOI) technology, which defined as the smallest bend radius for which these losses are
is enabled by a CMOS-compatible fabrication infrastruc- reported. Data are shown for wavelengths in the 1.3 – 1.6 μm
ture. The capacity demand of exascale datacenters, both in range.
volume and bandwidth, drive the use of SOI-based inter-
connects [6, 7]. However, no efficient lasers can be made
monolithically on the SOI platform and SOI-based trans- tectors [8, 9]. Prime applications can be found in optical
mitters require pre-fabricated laser diodes that are sepa- interconnects [10, 11].
rately bonded to the chip. To summarize this introduction, there is a need for
These three platforms, i.e., the silica-based, the InP- higher levels of integration of fiber-optic systems. At the
based, and the SOI platforms, are considered to be the same time, platforms for photonic integration have matured
most mature photonic technologies and fabrication can be and diversification takes place by heterogeneous electronic-
done using well-established process flows in commercial photonic integration, following the trend of “More than
foundries and generic platforms. An overview of these plat- Moore” [13]. This leads to the interesting question of
forms is given in Table 1, where the (relative) strengths whether fiber-optic systems can benefit from PIC devel-
and weaknesses are summarized. As can be seen, none of opments, as driven by telecom and datacom applications,
these platforms cover all functionalities. A breakthrough to enable fully integrated ‘fiber-like’ photonic systems on
step for a fully functional, low-cost and CMOS-fabrication a chip. In this paper we argue that this moment is here and
and packaging infrastructure compatible platform was the that the technology to achieve this has been demonstrated.
invention of the hybrid silicon platform. In this platform an We will review two major technology breakthoughs of the
InP-based epitaxial layer stack is wafer bonded to a fully last few years to support this claim.
processed SOI wafer, thereby heterogeneously integrating The first major breakthrough is the development of
InP-based active components, such as lasers and high-speed ultra-low loss waveguides (ULLWs) in a silicon nitride
modulators, with SOI-based passives, modulators and de- based integration platform. Figure 1 shows how the state-of-
the-art waveguide propagation loss has decreased by over
an order of magnitude over the last few years, down to
Table 1 Qualitative overview of the strengths and weaknesses less than 0.1 dB/m. It can clearly be seen that there is
of the main integration PIC platforms, taken from [12]. NA = not a trade-off between the bend radius and the propagation
available; + = possible; ++ = good; +++ = best option; SoC = loss. Typically higher-index-contrast waveguides need to
system on a chip; SiP = system in a package. be used for tighter bends, which increases the scatter loss.
In Sect. 2 we review these design trade-offs for ULLWs and
Hybrid in Sect. 3 the fabrication technology. In Sect. 4 we discuss
InP Silica Silicon Silicon the measurement techniques that are required to charac-
terize such low losses accurately. We further review some
Lasers +++ NA NA +++
device examples that can be realized in the ULLW platform
Photodetectors +++ NA ++ +++ in Sect. 5, thereby showing that the ULLW platform has the
Modulators ++ NA + ++ same functionalities, but with improved performance as
Passive devices + +++ ++ ++ compared to the general silica-based platforms, as shown
Wafer level packaging NA +++ +++ +++ in Table 1.
Although we focus this review on waveguides operat-
Electronic SoC and SiP
integration NA +++ +++ +++
ing in the 1.3 – 1.6 μm wavelength range, i.e., the telecom
wavelengths, we note that silicon nitride and silica-based


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Laser Photonics Rev. (2014) 3

waveguides have operating windows down to the ultraviolet

wavelengths. Recent results show low propagation losses
of silicon nitride waveguides of 0.5 dB/cm at 660 nm [14]
and below 1 dB/cm at the 532 – 900 nm wavelength range
[15]. These losses are higher than the values obtained at the
telecom wavelengths, as shown in Fig. 1. The most likely
cause is increased Rayleigh scattering. However, these re-
sults allow for an ultra-broadband integration platform.
The second breakthrough is the heterogeneous integra-
tion of ULLWs with silicon and hybrid silicon photon-
ics. Such a platform allows for the combination of lasers,
high-speed modulators, and detectors with long delay lines
and low-loss and high-resolution filters on a single PIC. In
Sect. 6 we will review the developments in this field. We
will discuss the trade-offs that have to be made in the fab-
rication technology to enable such a platform and to keep
the front-end process compatible with existing CMOS fab-
rication infrastructure.
Finally in Sect. 7 we will discuss the impact this new
technology can have on applications like gyroscopes, oscil-
lators, optical buffers and tuneable delay lines. We show that
integrated optical buffers can be scaled up to ∼1 μs storage
time. Gyroscopes should be able to achieve 0.1 ◦ /h res-
olution, using ULLW-based technology. Single-mode and
mode-locked lasers can have long, low-loss cavities and
will benefit through a reduced linewidth and lower phase
noise. We estimate that lasers with linewidths well below
1 kHz are achievable. Phase noise of mode-locked lasers
can be pushed down to around –100 dBc/Hz at 10 kHz
offset.

Figure 2 A comparison of (a) optical fiber and (b) planar wave-

guide propagation loss spectra. Total modeled propagation loss
2. Ultra-low loss waveguide design rationale is shown with solid lines. Modeled additive contributions to the
total loss are shown with dashed lines. The markers in the planar
Like optical fiber, the silica and silicon nitride waveguides waveguide loss spectrum are extracted from data in [19].
in Fig. 1 are generally made up of amorphous core and
cladding materials. Therefore, one expects to find sources
of loss in these planar waveguides that are similar to those bulk scattering loss, dominates due to the higher index con-
found in optical fiber. The solid line in Fig. 2(a) shows trast materials as well as the larger root-mean-square (RMS)
the total propagation loss spectrum modeled for a 2-km- amplitude of the sidewall roughness that is typical of pla-
long optical fiber coiled around a 127-mm-diameter spool nar core etching processes. Furthermore, the ratio of the
[47]. The propagation loss spectrum of single-mode optical interface roughness correlation length to the wavelength of
fiber, with its low loss windows near the 1310 and 1550 nm propagating light is typically smaller for planar processes,
wavelength regimes, takes shape from additive absorption, and this also yields higher interface scattering loss [48].
scattering, and macro-bend loss contributions [47]. In the At wavelengths sufficiently far from impurity absorp-
lowest loss regimes, the propagation loss is dominated by tion loss peaks (e.g. 1550 nm in Fig. 2(b)), the planar
radiative scattering from the bulk materials that make up the waveguide loss is typically dominated by scattering from
fiber [48]. The solid line in Fig. 2(b) shows the total propa- the core-cladding interfaces. This loss can be lowered via
gation loss spectrum modeled for a GeO2 -doped silica core fabrication steps, such as a photoresist reflow, that reduce
planar waveguide spiral delay having a 5-mm minimum the RMS amplitude of the line edge roughness resulting
bend radius [19]. from the planar lithography and etch processes. Yet, RMS
Though the planar waveguide loss spectrum is also the amplitudes below 0.1 nm are often required to achieve in-
sum of scattering, absorption, and macro-bend loss contri- terface scattering loss on the order of the bulk scattering
butions, the total propagation loss is about three orders limit for most optical grade materials [49]. From interface
of magnitude larger than that of optical fiber. Impurity scattering loss theory, one sees that reducing the waveguide
hydrogen absorption losses are generally larger in planar index contrast or modal core confinement will also lower
waveguides due to the lower temperature processes used scattering loss [50]. Yet, macro-bend radiation loss will in-
for fabrication. Also interface scattering loss, rather than crease and eventually dominate the total propagation loss

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4 M. J. R. Heck et al.: Ultra-low loss waveguide platform and its integration with silicon photonics

The doped silica and Si3 N4 loss lines intercept the lowest
reported loss values for each technology [19, 52], whereas
the Si line projects what is achievable if thin Si layers of
high quality are used [53]. From the figure, it is clear that
ultra-low loss can be achieved with higher-index-contrast
materials if the interface roughness is low, and the core
geometry is optimized. Furthermore, using a higher index
contrast along with this “design by geometry” approach
permits low propagation loss across a large range of bend
radii using a single stoichiometric material. Figure 3(b)
shows the optimum geometries found by the model to gen-
erate Fig. 3(a). For doped silica cores, the modal core con-
finement ranges from 66 – 81%, such that the quality of
the core material is emphasized at all bend radii. For the
higher-index-contrast Si3 N4 and Si cores, the modal core
confinement varies between 2.5 – 47% and 0.7 – 10%, re-
spectively, across the bend radii in the simulation. Thus the
quality of the cladding material immediately surrounding
the core is particularly important in the low-confinement,
lowest loss core geometries.
Though the amplitude of a waveguide’s transfer func-
tion is important for yeilding low loss and high performance
PICs, the phase is equally important to the performance
of the many waveguide components relying on spatial
or temporal multi-beam interference, e.g., the ring res-
onator and grating based components discussed in Sect. 5.
Figure 4(a) shows the phase birefringence (i.e. the differ-
ence between the transverse electric (TE) and transverse
magnetic (TM) effective indices) of the waveguides mod-
eled in Fig. 3(a,b). The birefringence is generally 3 – 4 or-
Figure 3 (a) Propagation loss versus bend radius modeled for ders of magnitude larger in the higher-index-contrast cores
GeO2 -doped silica, Si3 N4 , and Si channel waveguide technolo- due to the higher-aspect-ratio geometries required to min-
gies. The bend loss is modeled with Photon Design’s FIMMWAVE imize scattering loss. This large birefringence can be ben-
software, and the scattering loss is calculated from the same 2D eficial to components and systems on the chip [55]. Yet,
mode solution using the method described in [50]. RMS sidewall it must be handled carefully at the chip edge in applica-
roughness of 30 nm and 9 nm are used for the doped silica and tions where the PIC interfaces with an optical fiber mode
Si3 N4 cores such that each line intercepts the lowest reported of arbitrary polarization [56, 57].
loss for each technology [19, 52]. The RMS sidewall roughness Figure 4(b) shows the deviation in TE effective index
of 5 nm reported in [53] is used for Si. One should note that the with changing vertical (dneff /dt) and lateral (dneff /dw) core
5 nm roughness value that sets the Si loss limit can be reduced dimensions for the three technologies. The standard devia-
in small bend radius regimes where more recent advances in Si
tions of the waveguide phase errors due to interfacial rough-
sidewall roughness reduction [54] can be applied. RMS surface
ness are proportional to the product of these values with the
roughness of 0.3 nm and roughness correlation lengths of 50 nm
are used for all technologies. (b) The optimum core geometry for
RMS amplitude of the interface roughness [58]. The core
each core type is used at each bend radius. All simulations are geometries of all three technologies have low sensitivity
performed for λ0 = 1550 nm and for TE polarization. to deviations along the lateral direction. The higher-index-
contrast materials are generally 3 orders of magnitude more
sensitive to perturbations in the vertical dimension than
if the index contrast or core confinement is decreased too doped silica cores. Thus, the higher-index-contrast tech-
much. This tradeoff between bend and scattering losses, nologies rely on smooth top and bottom core-cladding in-
which is experimentally illustrated by Fig. 1, is of primary terfaces for achieving good phase transfer characteristics.
importance in the design of planar waveguides. A good phase transfer characteristic can be qualified exper-
Figure 3(a) shows the minimum single-mode wave- imentally from the performance of components fabricated
guide propagation loss versus bend radius modeled for with a given technology. For example, the low crosstalk
low-index-contrast (n = 0.75%) doped-silica, medium- measured for arrayed waveguide gratings (AWGs) fabri-
index-contrast (n = 23.4%) stoichiometric Si3 N4 , and cated with the Si3 N4 technology, as discussed in Sect. 5
high-index-contrast (n = 41.3%) Si cores. The plot is and in [59], is indicative of a good phase transfer charac-
generated from a numerical minimization of total scattering teristic.
and bend propagation losses with respect to variable single- In this section, we discussed design considerations for
mode core thickness and width at a given bend radius [51]. ultra-low loss waveguides. In doing so, we focused on


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Laser Photonics Rev. (2014) 5

choosing the correct waveguide index contrast and core

geometry for achieving good waveguide amplitude and
phase transfer characteristics. In reality, the waveguide de-
sign cannot be separated from the fabrication technology
and application. For example, lower-index-contrast mate-
rials will always perform favorably if the top and bottom
core/cladding interfaces of the waveguide cannot be made
sufficiently smooth. Likewise, a waveguide having an index
contrast of 0.75% will never achieve ultra-low propagation
loss at a bend radius below 1 mm. Some applications require
only chip-scale routing of a few centimeters total, and so it
is more appropriate in these cases to use a higher loss core
geometry with tighter bending capability or a geometry that
can be realized using more readily available standard layer
thicknesses. Still, for other applications requiring tens of
meters of optical delay or ultra-narrowband filter character-
istics, the thin and wide optimum core geometries discussed
in this section are important. Thus, a suitable index contrast
and/or core geometry must be chosen with the fabrication
technology and eventual application in mind.

3. Fabrication technology

In this section, we discuss the 100 and 200–mm substrate

fabrication technology used to achieve ultra-low propa-
gation loss in the Si3 N4 ULLW platform. A schematic
overview of the process is shown in Fig. 5. The process
begins with a 15-μm thick layer of SiO2 that is thermally
grown on a Si substrate. Ultra-high Q resonators fabri-
cated with thermally grown SiO2 indicate that this material
can have a Rayleigh scattering loss coefficient below 0.6
(dB·μm4 /km) [60]. The high growth temperature is also
beneficial to the exclusion of impurity hydrogen, which
Figure 4 (a) Phase birefringence (neff,TE – neff,TM ) modeled for can form molecules having overtone absorption loss peaks
the core geometries and materials of Fig. 3(a) and Fig. 3(b). in the C band (as seen in Fig. 2(a,b)). In Fig. 5(a), a thin
(b) Derivatives in neff,TE for the core geometries and materials. film of stoichiometric Si3 N4 is deposited via low-pressure
All simulations are performed for λ0 = 1550 nm. chemical vapor deposition (LPCVD). Such films have RMS
surface roughness below 0.5 nm, as measured by atomic-
force microscopy. Photolithography and dry etching are

Figure 5 A schematic overview of the pro-

cesses used to fabricate the waveguides dis-
cussed in this paper.

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6 M. J. R. Heck et al.: Ultra-low loss waveguide platform and its integration with silicon photonics

then used to define the cores, as shown in Fig. 5(b). For

100–mm substrate fabrication, contact lithography is used
along with a reflow of the photoresist on a hotplate in order
to achieve low line edge roughness. Fabrication on 200–mm
substrates is performed in a complementary metal-oxide-
semiconductor (CMOS) compatible cleanroom using pro-
jection lithography for which no reflow is necessary. In
Fig. 5(c), a thin encapsulating oxide is deposited and fol-
lowed with a high temperature anneal at 1050 – 1150 ◦ C
for 7 to 3 hours in an N2 environment (lower tempera-
ture requires longer time) to drive out the hydrogen and
minimize the optical absorption through N-H and/or O-H
bond resonances [33]. This layer is deposited to allow for
surface planarization. In Fig. 5(d), the protrusion caused
by deposition over the core etch is removed via chemical
mechanical polishing (CMP). Finally, an upper cladding
layer is added via chemical vapor deposition (Fig. 5(e.i)) or
through O2 plasma-enhanced bonding of another thermally
grown SiO2 wafer (Fig. 5(e.ii)). Deposited upper claddings
undergo the same anneal as the encapsulation oxide. For
the wafer bonded case, the stack is annealed at 950 ◦ C
for 3 hours in order to strengthen the bond. We note that
LPCVD-deposited oxide is limited to a thickness of around
∼3 μm, hence the two-step approach for depositing a thick
top cladding.

4. Ultra-low loss waveguide characterization

and results

The cut-back method, wherein the insertion loss of a wave-

guide is measured before and after being cleaved to shorter
length, is most commonly used to measure propagation loss
[19]. To ensure adequate measurement accuracy, the on-
chip loss must be larger than the variation in coupling loss.
While an optical fiber scientist may have a 100 km spool
of ultra-low-loss fiber for performing a cut-back measure-
ment, it would take over 100 m of ultra-low-loss planar
waveguide on a chip to measure with the same accuracy
using this method. Such large structures take up valuable
mask space that could be better utilized by other devices
and test structures. The cleaving and polishing of planar
waveguides also tends to yield a greater variation in cou-
pling loss. Furthermore, it is difficult to diagnose spectrally
flat point losses due to fabrication defects, which are more Figure 6 (a) A schematic optical backscatter reflectometer
common in planar processing, using such a “black box” (OBR) [61], and pictures of red light propagating in two planar
method. waveguide test structures. The red light is used for illustrative pur-
Figure 6(a) shows a simplified diagram of a backscatter pose only. (b) Example backscatter data measured in two Si3 N4
reflectometer (see [61] for details) along with photographs waveguides of the type shown in (a).
of red light propagating in two spiralled planar wave-
guide test structures. In the reflectometer, reflected light
in the measurement arm undergoes a group delay relative the structure is measured. Plots of the measured reflectivity
to the light in the reference arm. Thus, a difference tone γ τ in two such structures are shown in Fig. 6(b). In the s-bend
(where γ is the rate of laser tuning and τ is the group delay) structure, the large reflections at the input and output
is generated at the second coupler as the source frequency is facets are used to measure the mean group index of wave-
linearly swept. By sampling the interferogram generated by guide in the structure. The decay in measured backscatter
the backscatter from a planar waveguide structure and tak- from within the waveguide is fit to measure the propaga-
ing a Fourier transform, the distributed reflectivity within tion loss in the waveguide, which is similar to a cut-back


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data (i.e., the windowing function is moved in increments

smaller than the window size, resulting in a different bin-
ning in the Fourier transform) as well as the error in each
fit point. Figure 7(b) shows the critical bend radius (the
radius at which bend loss is equal to 0.1 dB/m) measured
for 40 and 50 nm cores by using the spiral-in structure from
Fig. 6(b). As one expects, the critical bend radius is larger
for waveguides having lower modal core confinement. The
dashed lines show the critical bend radii simulated using
the bend loss model in Sect. 2.
Though optical backscatter measurements allow for
quick and accurate determination of the waveguide am-
plitude and phase characteristics, the data are limited to
the wavelength regime of the tuneable laser used in the
measurement. A broadband measurement of the amplitude
characteristic can be used to more accurately measure the
centers of impurity absorption losses and to diagnose the
limiting loss contribution. Figure 8 shows a broadband in-
sertion loss measurement of two s-bend spiral structures.
The accuracy of the measurement is too low to measure
ultra-low loss, so the characteristics are normalized to the
values measured with the OBR. Loss spectra for 100 and
40 nm thick cores are shown. The 100 nm thick waveg-
uide has a deposited upper cladding, while the 40-nm
Figure 7 (a) Total propagation loss (circles) vs. wavelength for a thick waveguide has a wafer-bonded thermal oxide up-
40-nm-thick by 13-μm-wide waveguide with bonded thermal ox- per cladding. Due to the higher modal core confinement
ide upper cladding. The solid lines are modeled scattering and of the 100-nm thick core, the N-H loss peak is more pro-
absorption loss fits to the data. (b) The critical bend radius ex- nounced. The waveguide also shows a large impurity peak
tracted from 40 and 50-nm-thick cores versus core width. Simu- near 1310 nm, presumably due to impurities in the de-
lated values are shown by dashed lines. posited upper cladding. Both waveguides have OH− loss
peaks near 1390 nm as was shown in Fig. 2(a,b). Still, the
measurements indicate that techniques for further lowering
measurement though only one wavelength sweep is re- the amount of impurity hydrogen in the waveguide films
quired to obtain a large number of data points [52]. With should be investigated.
the spiral-in structure, the backscatter can be fit in order to
determine the waveguide’s bending capability [52]. Since
fits of backscatter within the waveguides are performed,
the measurement accuracy does not depend on the fiber-to-
chip coupling loss. Unless otherwise noted, loss data are
presented for TE polarization.
Figure 7(a) shows the loss fit results for a Si3 N4 wave-
guide s-bend spiral structure. The spectral dependence of
the propagation loss is simple to obtain from OBR mea-
surements by moving a windowing function of a given fre-
quency width through the interferogram before taking the
Fourier transform and fitting the backscatter data (i.e., only
one source sweep is necessary). Since the Fourier trans-
form is taken after the windowing function, the resolution
of the backscatter data decreases as the window is narrowed
such that the frequency window cannot be made arbitrarily
small [52]. Unlike the spectra in Fig. 2(a,b), the loss in-
creases with decreasing wavelength over the section of the
C band measured. This is primarily due to the first overtone
absorption of the impurity N-H molecule, which one would
expect to see in the loss spectra of a Si3 N4 waveguide.
Sufficiently far away from the absorption peak, ultra-low
propagation loss of (0.045 ± 0.04 dB/m) is measured, as Figure 8 Propagation loss spectra measured with an OSA and
shown in the inset. The inset also shows how the error bars the broadband light source made up of 4 combined LEDs. The
of the measurement are calculated from the spread in fit source spectrum is shown in the inset.

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8 M. J. R. Heck et al.: Ultra-low loss waveguide platform and its integration with silicon photonics

5. Ultra-low loss waveguide devices platform [67]. A recent InP resonator for angular sensing
and circuits demonstrated an intrinsic Q of 1.2 million with an FSR of
1 GHz [76]. Such a demonstration is a step towards inte-
ULLWs as standalone devices have only a very limited grated laser gyroscope systems on chip, but further reduc-
usefulness, for example, as a robust and polarization main- tion in loss is necessary for competitive sensitivity less than
taining replacement for a fiber coil in delay lines or gyro- 10◦ /hr. The lowest semiconductor loss to date was achieved
scopes. In general, for these planar ULLWs to be practically with a shallowly etched silicon ridge waveguide utilizing
useful, it is necessary that functional components can be in- resist reflow and oxidation-based smoothing to achieve a Q
tegrated. Such functional components need to be fabricated of 22 million at an FSR of 5.35 GHz [40].
using the same process flow, so as not to compromise the Early phosphorus doped silica resonators at large bend
ultra-low loss performance. In the following we will re- radii have demonstrated up to 30 million intrinsic Q at a 1.1-
view recent results on passive components, such as high-Q GHz FSR [18]. This waveguide coupled resonator Q was
resonators, grating and AWG-based filters, and tuneable not surpassed until development of the ULLW platform de-
delay lines. Also we will present an overview of the efforts scribed here. Recent results on the ULLW platform, using
to integrate waveguide components in multiple vertically 50 – 100-nm thick cores, yielded ultra-high Q resonators
stacked layers, i.e., three-dimensional integration. The re- that operated at 1060 nm, 1310 nm, and 1550 nm [70].
sults in this section show the versatility of the technology The highest extracted intrinsic Q values of 28 million at
and we can argue that this technology presents an ultra-low 6.5-GHz FSR were obtained at 1310 nm. These Q val-
loss platform, with building blocks for a plethora of passive ues were most likely limited by excess leakage loss in the
functionalities. weakly coupled regime. Further experiments on the direc-
tional couplers showed that appreciable round trip loss was
added with increased coupling strength, hindering the Q
factor. Currently, record intrinsic Q factors as high as 5
5.1. High-Q ring resonators and 55 million, at 20 and 3.3-GHz FSR, respectively, have
been demonstrated [69]. The thickness of the ULLW core
Narrow bandwidth, high-Q ring resonators are useful de- layer was 90 and 40 nm respectively for these FSRs and
vices that can be quickly implemented on a ULLW platform the waveguide width was kept in a proper single mode
using directional couplers. The periodic nature of the notch, regime to insure spectrally pure resonances. Figure 9(a)
or bandpass, filtering has allowed for their use in various plots the spectral dependence of the ULLW resonators at
ranges of filtering applications. Planar waveguide based 20–GHz and 3.3-GHz FSR, which show the lowest losses
resonators have typically been used in wavelength divi- near 1580 nm, similar to the ULLW delay lines. Figure 9(b)
sion multiplexed (WDM) applications, where bandwidths plots the spectral response of a 55 million Q resonator with
of multiple gigahertz are required [62]. However, high- a 3.3-GHz FSR, as measured with a narrow linewidth tune-
performance applications, such as microwave photonic fil- able laser.
ters, low-noise oscillators, and other stable frequency ref- Other Si3 N4 platforms have focused on higher confine-
erences, require bandwidths in the Megahertz range, with ment structures that require thicker LPCVD Si3 N4 layers.
corresponding loaded Q values over 107 and propagation These approaches allow for low losses at micrometer bend
losses below 0.1 dB/cm. radius, and thus very large gigahertz to terahertz range FSRs
In addition to narrowband microwave photonic filters and correspondingly higher finesse values. In [38], two lay-
and frequency references, dielectric waveguide resonators ers of Si3 N4 are deposited with a SiO2 intermediate layer
are interesting for their use in compact sensing applications. to create a high confinement mode. This dual layer Si3 N4
In biological sensing [63], an effective index perturbation waveguide geometry has shown resonator intrinsic Qs of
can be measured in the presence of liquid or gas substances. 3.2 million at 20-GHz FSR, with a bend radius down to
Alternatively, the spectral absorption profile of a specific 70 μm. In [32,74], some of the stress issues of thick, 910-nm
species can be determined if the resonator maintains low Si3 N4 layers were solved with a multi-step deposition and
losses into the visible wavelengths, such as the ULLW plat- intentional stress relief to achieve intrinsic Qs of 7 million
form [70]. Integrated high Q resonators can enhance the at 250-GHz FSR. With an even higher FSR of 1.4 THz,
sensitivity of these systems through an increase in Q and the intrinsic Q was 3 million. In [35, 68], a multiple layer
scalability to arrays of sensors. integration approach was taken by using thick 200 nm –
Previously, the ultra-high Q regime has been limited 400 nm Si3 N4 resonators and vertically coupled to output
to laser cooled atoms [64], bulk Fabry-Pérot cavities [65], waveguides. Si3 N4 -Si3 N4 coupling results at 660 nm for
and amorphous or crystalline glasses that require prism visible sensing show intrinsic Qs of 5·105 at 1.1-THz FSR.
or specialized tapered fiber coupling [66]. To achieve Q With Si3 N4 -SOI coupling and high temperature anneals of
values larger than 107 in an integrated resonator, losses in 1100 ◦ C, intrinsic Qs of 20 million at 130-GHz FSR and
the silicon, III/V, silica, and silicon nitride platforms have 2 million with single mode 530-GHz FSR were demon-
been pushed down, as shown in Fig. 1. strated on a compact, multiple platform solution near
InP-based waveguides typically have losses in the range 1550 nm, as shown in Fig. 10.
of 0.1 – 1 dB/cm, and up to 106 intrinsic Qs, with the ad- The drive for decreasing waveguide losses pushes the Q
vantage of direct incorporation of gain on the same material of integrated resonators, as discussed. Another promising


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Figure 10 (a) Illustration and infrared camera image of an ex-

cited Si3 N4 resonator on SOI waveguide. (b,c) Corresponding
spectral sweep results in the C band. Pictures and data taken
from [35].
Figure 9 (a) Intrinsic Q factors of ULLW resonators at 2 different
FSRs in the C+L bands. (b) Laser sweep of a 40-nm Si3 N4 , 3.3-
GHz FSR resonator’s through and drop port, showing an intrinsic
Q of 55 million. The fitted drop port insertion loss has been taken
into account.

approach that should be mentioned is to make the record-

performing whispering gallery mode (WGM) resonators
compatible with further integration on the same chip. The
work in [60, 81] shows how previously reported circular
WGM disk resonators have been implemented into a wave-
guide platform where the optical mode can achieve low loss
with proper etching angle of the silica on silicon pillars.
With this increased control of processing, resonator Qs up
Figure 11 State of the art resonator intrinsic Q factor versus
to 875 million at 4.2-GHz FSR have been demonstrated. free spectral range (FSR), comparing planar waveguide coupled
However, this platform requires continuous bending for platforms [18, 19, 22, 32, 35, 38, 40, 46, 69–76] against whispering
confinement, and is not yet coupled with output waveguides gallery mode resonators (WGM) requiring specialized fiber or
for chip based integration. prism output coupling [60, 77–81].
As a comparison, Fig. 11 shows the intrinsic Q, which is
directly related to propagation loss, for multiple waveguide
coupled platforms for a range of corresponding FSRs. As 5.2. Sidewall gratings
can be seen, the Q decreases for increasing FSR, which is
consistent with the overview shown in Fig. 1. In the same Waveguide gratings are a key component in the photonic in-
figure the intrinsic Qs of various WGM devices that re- tegration toolbox. These can be used as in-line and reflective
quire specialized tapered fiber or prism coupling are shown. spectral amplitude and phase filters and enable well-known
Although dedicated WGM devices outperform planar in- devices such as the distributed-feedback (DFB) laser. Typ-
tegrated devices by orders of magnitude, such integrated ically gratings are added to the device or PIC in a sep-
resonators are currently able to achieve Qs on the order of arate process step, making use of holographic or e-beam
1 to 100 million. With these values, high-end applications lithography. Using sidewall gratings makes the process
like microwave photonics are within reach of this integrated simpler, since waveguides and gratings are defined in the
technology and a clear path for further integration into full same lithographic step [82]. This approach is particularly
PICs is available. interesting for the ULLW platform, since the fabrication

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5.3. Arrayed-waveguide gratings

Arrayed-waveguide gratings (AWGs) are key components

for optical communication systems, where they are used
for (de)multiplexing WDM signals. Silica AWGs, based
on silicon-oxynitride or doped silicon-oxide cores, are the
components of choice in such systems and numerous de-
signs with varying bandwidth, channel number and spacing,
footprint, and operating wavelength have been reported [1].
Silicon nitride based AWGs are typically used for small-
footprint applications [92] and visible light applications
[93], since the high index contrast makes such AWGs less
tolerant to fabrication errors and typically increases the in-
sertion loss and channel crosstalk.
The work in [94] shows that AWGs based on high-
aspect ratio Si3 N4 waveguides, with low confinement, have
high performance. Negligible insertion losses (<0.5 dB)
and crosstalk levels better than -30 dB are shown for a 16-
channel 200-GHz AWG for operating wavelengths around
1310 nm and 1550 nm. Transmission spectra are shown
in Fig. 13. This result shows that the ULLW platform
is well suited to integrate high-performance AWGs. The
Figure 12 (a) Top down SEM image of a fabricated Si3 N4 side- CMOS compatible fabrication technology seems to make
wall grating, with a period of 520 nm. (b) Measured reflectivity such silicon-nitride-based AWGs the technology of choice
spectra of four 200-μm long gratings for TE light. The fine oscilla-
tions are due to the 3-mm Fabry-Pérot cavity created by the diced
input facet and the grating. Pictures and data taken from [83].

technology can make use of the CMOS infrastructure and

hence waveguide and grating patterns can be defined in a
deep-UV lithography step, e.g., 248 nm or 193 nm. More-
over, etching through the Si3 N4 core layer and having both
an upper and lower silicon-oxide cladding makes the ap-
proach very tolerant as etch depth variations do not affect
the grating strength.
An example of such a sidewall grating in the ULLW
platform is shown in Fig. 12(a) [83]. As can be seen in
Fig. 12(b), the coupling strength is determined by the grat-
ing depth, i.e. the difference in width along the waveguide.
This means that the coupling strength is lithographically de-
fined and can be varied by mask design only. Also, by mask
design only, more complex grating transfer functions can
be realized, such as apodized gratings and multiple-channel
gratings [84–86]. Another approach is to use very low cou-
pling strength to realize long gratings, having fiber Bragg
grating-like performance. Such gratings were simulated in
a spiral configuration in [87].
Other applications of interest using this grating technol-
ogy are the realization of on-chip optically pumped sources,
where the Si3 N4 waveguides and gratings define the cavity
and the overlap with an optically pumped Erbium-doped
alumina cladding layer provides the gain. With this ap-
proach, both DFB and distributed-Bragg grating (DBR)
lasers have been realized [88, 89]. As another application
we want to mention vertical grating couplers, to couple Figure 13 (a) Picture of fabricated ULLW-based AWG, as re-
light in and out of the chip. Coupling of the PIC to SMF ported in [94]. (b) Measured spectral response of all the chan-
was reported with 4.2 dB loss and a large 1-dB bandwidth nels in the wavelength range around 1310 nm for this AWG. The
of 67 nm [90, 91]. resolution is 0.1 nm. Graph taken from [94].


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5.5. Multi-layer integration

Complex PICs and networks on a chip often require a

densely interwoven network of waveguides where multiple
crossings cannot be avoided. To avoid prohibitive cumu-
lative loss and crosstalk levels, several studies have been
done in the last few years on three-dimensional integration,
where two or more ULLW planes are vertically intercon-
nected. The challenge here is to have low loss and low
crosstalk waveguide crossings in different layers, while at
the same time having low insertion loss and robust vertical
couplers. Several approaches have been proposed and we
will briefly review the results.
In [102] a vertical directional coupler is reported, as
shown in Fig. 15(a). The insertion loss is 0.2 dB and wave-
guide crossings have a 0.25-dB loss. However the coupling
ratio is heavily affected by the stress-optic effect, which
means that the design actually has to be calibrated with
the process flow or, e.g., stress-relieving trenches have to
be etched. A more robust design is presented in [103],
where adiabatically tapered couplers are used, as shown in
Fig. 15(b). These couplers show 0.2-dB insertion loss and
Figure 14 (left) Schematic of the tuneable delay chip with the 0.4 dB loss per crossing. In both cases the crossing loss
respective delay length for each stage. The inset shows the switch
layout, consisting of thermo-optic phase tuners and directional
couplers. (right) Optical output of the 4-bit tuneable delay for all
24 delay settings. Picture and data taken from [101].

for complex PICs that require active components, as will

be discussed further in Sect. 6 [59, 112].

5.4. Tuneable delay lines

On-chip tuneable delay lines find many applications. Ex-

amples include optical packet buffers and synchronizers
[31] and delay lines for microwave photonics and phased
array antennas [95]. The clear advantage of on-chip delay
lines over fiber delay lines is the lithographic waveguide
length control. This means that more accurate delays can
be fabricated.
Tuneable delay lines for microwave photonic applica-
tions are often implemented using ring resonator based
tuneable group delays [96–99]. This allows for a compact
footprint, but limits the signal bandwidth to a few Gigahertz
only. In beam-forming antennas such an approach may lead
to squinting of the beam, caused by a frequency-dependent
delay. This can be avoided by a broadband approach, such
as a true-time delay (TTD) line. In [100] an 8-bit TTD was
shown with a maximum delay of 256 ps. By making use
of the ULLW technology, the maximum delay can be in-
creased, as shown in [101]. In this case a 4-bit TTD was
reported, having a maximum delay of over 12 ns using
thermo-optic switches. The broad bandwidth of such TTDs Figure 15 Multi-layer integration using (a) directional coupler
makes them attractive for telecommunication applications [103], (b) tapered coupler [102], and (c) coupling by ring resonator
such as optical packet buffers. [107].

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12 M. J. R. Heck et al.: Ultra-low loss waveguide platform and its integration with silicon photonics

tions, layer thickness uniformity, and built-in material stress

and strain gradients.

6. Integration with silicon and hybrid silicon

photonics

As highlighted in Table 1, a silica-based platform has a lim-

ited set of building blocks, restricted to passive components
and low-speed thermo-optic phase tuners. No high-speed
active components and sources are available. Silicon-based
photonics, however, lacks high-quality and low-loss passive
components for demanding applications, such as telecom-
munications. This gives a clear rationale why one would
like to integrate these platforms together. In this section
we will review first the recent efforts on the integration of
silica-based photonics with silicon and germanium photon-
ics. Then we will discuss the fabrication technology that
can be used to actually integrate ULLWs into a silicon and
hybrid silicon photonics platform.

6.1. Monolithic integration of silicon and silica

photonics

Silica PICs can be integrated with silicon and III/V based

PICs using a so-called photonic motherboard approach
[108]. This is a hybrid integration technology, where the dif-
ferent PICs have to be packaged and aligned with each other.
Such an approach does not scale well with volume in terms
of cost reduction. Applications include semiconductor opti-
Figure 16 (a) 8-channel CWDM receiver [114], (b) 16-channel cal amplifier (SOA)-based regenerators and switches, burst-
VOA array [113] and (c) wavelength selective switch [116]. mode receivers, optical memory elements and integrated
phase-locked loops [109, 110].
A much more scalable and robust approach is to inte-
grate silicon and silica components monolithically, using
is too high for practical applications. Similar work has CMOS-compatible fabrication processes on large 200-mm
been done on multi-layer integration of silicon with Si3 N4 diameter wafers. The most intuitive and straightforward ap-
waveguides [104]. proach is to deposit silica-based waveguide layers on top
An interesting approach to bring the crossing loss down of a processed SOI wafer. Transitions from silicon to silica
is presented in [105]. A ring resonator is used as a reso- waveguides can be made by, e.g., inverse taper couplers
nant coupler (Fig. 15(c)), thereby enhancing the coupling [111]. Both Si3 N4 [112] and silicon-rich SiOx [113] are
strength between the two vertically separated layers. Low used as core material for the passives, which have to be de-
waveguide crossing losses of 0.04 dB per crossing and an posited at low temperature to avoid any detrimental effect
insertion loss of 0.6 dB are reported. Since this design re- on the SOI-based photonics and possibly electronics.
lies on accurate lateral and vertical coupling gaps, the latter A major reason for the integration of silica-based com-
being defined by chemical-mechanical polishing, the ro- ponents on the silicon photonic platform are the AWG
bustness against process variations seems lower than the (de)multiplexers. The lower index contrast of Si3 N4 and
approach in [103]. Moreover, the inherently narrow-band SiOx with the surrounding SiO2 cladding decreases phase
operation of the coupler requires active thermal tuning of errors in the AWG arms, leading to better crosstalk and
the rings for most applications. We note that this resonator- lower loss than silicon-based AWGs. Also the thermo-optic
based design can be further expanded with multiple ver- coefficients of these materials are lower than that of silicon
tically stacked rings to increase the vertical coupling dis- and hence the AWGs are less temperature dependent. As a
tance, as discussed in [106]. last point, we note that by using a square core design, the
In conclusion, it can be stated that currently no approach waveguide can be made with low polarization dependence
for multi-layer integration is available that can simultane- i.e., having a low birefringence [113].
ously achieve low insertion loss, low crossing loss and that Various demonstrations based on this technology have
is robust against process variations, such as linewidth varia- been reported. Among these are an 8-channel CWDM


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Figure 17 Schematic overview of the integra-

tion process used to integrate ULLWs on a
silicon photonics platform [122]. Steps include
(a) thermal oxidation of an SOI wafer, (b) pro-
cessing and CMP of an ULLW wafer, (c) bonding
these together, (d) remove the silicon substrate of
the SOI wafer and (e) its buried oxide layer. Here-
after silicon photonic processing can be done (f).

receiver with 20-nm channel spacing [114], a 40-channel and is schematically shown in Fig. 17. First the ULLW
DWDM photodiode array operating at 40 Gbps per chan- circuitry is fabricated, polished and annealed. A thermally
nel [112], and a 16-channel receiver with flip-chip bonded oxidized SOI wafer is then bonded using an oxygen plasma
trans-impedance and limiting amplifiers, operating at assisted process and annealed at 950 ◦ C. Hereafter the sili-
1.25 Gbps per channel [113]. Also an array of 10 DWDM con substrate is removed using the buried oxide layer as an
modulators is reported, operating at 25 Gbps per channel etch-stop. Then the buried oxide is also removed, leaving a
[115]. Other applications for switching and routing include crystalline and flat silicon layer on top of the ULLW wafer.
a wavelength selective switch for flexgrid [116] and a vari- We note that alternatively a process similar to the Smart-
able optical attenuator array, operating at 100 MHz, for, Cut process can be used, where the bonded silicon wafer
e.g., channel selection [111]. A delay-line interferometer is ion implanted with hydrogen and then sliced by a heat
for demodulation of phase-shift-keyed (PSK) formats was treatment [119].
reported in [117]. The silicon processing can then be done on a smooth
This overview of demonstrators shows the validity of and clean surface, much like using an SOI wafer as a starting
depositing silica-based waveguides at low temperature for point. This allows for high-resolution deep-UV lithography
the applications of multiplexing and filtering. A drawback on the silicon and the complete process flow remains com-
is the large residual stress in the low-temperature wave- patible with the CMOS fabrication infrastructure and with
guides, which increases the birefringence, but this can be the established silicon photonics processes. We note that the
overcome by a multi-layer-core approach [118]. However, silicon lithography step, which takes place after the bond-
for applications that rely on low-loss waveguides, as intro- ing step, can be aligned to markers etched in the ULLW
duced above, the main drawback of this approach are the layer. This means that alignment in the wafer bonding step
high propagation losses of the silica waveguides, ranging is not critical.
from 60 dB/m for the SiOx [111] to 2 – 3 dB/cm for the The light can be coupled between the silicon and
Si3 N4 [112] approach. The main reason for the higher loss the ULLW layer by using tapered couplers, as shown in
is the low temperature budget, which does not allow for Fig. 18(a). Coupling losses of about 0.4 dB per transition
the high-temperature anneal, as discussed above. In the fol- with a 20-nm 3-dB bandwidth and losses of 0.8 dB per
lowing we will discuss an approach that can overcome this transition with a 100-nm 3-dB bandwidth for two different
issue. taper designs have been reported [122]. Figure 18(b) shows
a picture of a realized test chip. The ULLW loss for these
100-nm thick Si3 N4 waveguides was reported at 1.2 dB/m,
6.2. Silicon and hybrid silicon on ULLW platform which is in line with the best-case results shown in Fig. 1.
An interesting observation here is that this approach
To achieve ultra-low loss values as indicated in Fig. 7, does not significantly add steps to the total process flow for
lengthy thermal anneals of 1000 ◦ C to 1200 ◦ C are re- silicon photonics, when the fabrication of the actual SOI
quired. To fit this into the thermal budget of the process wafer itself is taken into account. The silicon layer trans-
flow, such waveguides need to be fabricated before the sil- fer to the ULLW stack can be similar to the fabrication
icon, and possibly the III/V, processing. A process flow of SOI, which means that this can be a robust, high-yield,
that can accommodate these anneals was reported in [122] and relatively low-cost process, which can be done in a

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components has solved this problem and the hybrid silicon

platform is now mature and being commercialized [8, 9].
Since the process flow described in Fig. 17 is fully com-
patible with silicon photonics, in principle it should also be
compatible with the hybrid silicon platform. The first results
of such an integration effort were presented in [59]. In this
work hybrid silicon-InGaAs photodiodes were integrated
on top of an ULLW platform. This was done by bonding
a III/V die on top of the silicon circuit. Hereafter the III/V
photodetectors were processed in a back-end process, using
a process similar to the work described in [121]. A cross-
section and a schematic of the photodiode are shown in
Fig. 19. An 8-channel photodiode array integrated with an
ULLW AWG, having 3 nm channel spacing, was success-
fully realized, with the channels operating up to 50 Gbps, in
principle allowing for a fully integrated 400-Gbps receiver
front end.
These results show that III/V-based components can
be heterogeneously integrated on an ULLW platform.
This should hold for lasers too, but it has to be noted
that the thermal bottleneck is increased due to the thick
layer of silicon-oxide. Techniques like flip-chip bonding or
microfluidic microchannel cooling should be considered.
Another technique to heterogeneously integrate III/V pho-
todiodes with silica is to use micro-mirrors etched at an an-
gle. This technique was successfully used to make a (dual

Figure 18 (a) Schematic of the structure used to couple light

between ULLW and silicon waveguide layers. (b) Picture of the
realized chip, showing ULLWs, silicon waveguides and coupling
tapers. Pictures taken from [122].

CMOS-compatible environment. This approach is the only

heterogeneous or monolithic integration platform known
that can combine Si3 N4 -based waveguides with silicon
photonics, while keeping their ultra-low loss performance.
It can be argued that this approach is equally valid for
combining silicon photonics with low-loss doped-silica or
silicon-oxynitride-based waveguides, although the thicker
core layer is more demanding on the required CMP process
(Fig. 17(b)). Also we want to point out that integration with
CMOS-electronics is possible in this way, using a CMOS
photonic approach as, for example, mentioned in [120].
It is clear from Table 1 that the platforms described
in this section, where ULLWs are integrated with sili- Figure 19 (a) SEM picture of a completed hybrid silicon-InGaAs
con photonics, offer increased functionality. However, the photodiode with underlying Si3 N4 waveguide. (b) Schematic of
highest-speed modulators and detectors and most impor- hybrid photodiode with tapered silicon coupler and Si3 N4 strip
tantly efficient optical sources are still not available. In sili- waveguide. Nominal doping levels are given in parenthesis. The
con photonics the heterogeneous integration of III/V based SiO2 layers are not shown. Pictures taken from [59].


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polarization) quadrature phase shift keyed (DP-QPSK) re- We expect this technology to have a huge impact on
ceiver [123, 124]. This approach also ensures low wave- various existing and novel applications. Based on the re-
guide losses. In [125] an approach was taken to integrate viewed results obtained with ULLWs and further integra-
Si3 N4 waveguides monolithically with a quantum-dot laser tion into complex PICs, we can make some estimates here.
on a GaAs substrate. However, this approach had relatively In the following we will discuss prospects for optical packet
high Si3 N4 propagation losses of 11 dB/cm. buffering, gyroscopes, low-noise lasers, and opto-electronic
oscillators.
An application that can benefit in a straightforward way
7. Discussion and future perspective from long delay lines and decreased losses due to integra-
tion is an optical packet buffer [126–129]. For 1000-byte
We have shown that over the last few years, the optical packets at 40 Gbps, delay line lengths corresponding to at
propagation losses of waveguides integrated in planar cir- least 25 ns are required. This can be achieved with 5-m
cuit layouts have dropped by an order of magnitude, now long ULLWs. If we assume 20-dB of loss can be tolerated
reaching sub-0.1 dB/m loss values. This is enabled by using before regeneration is required, the total storage time can
stoichiometric Si3 N4 -based waveguide cores with a ther- be calculated. With coupling losses of ∼1 dB [122] to an
mal silicon-oxide cladding. Such waveguides outperform on-chip hybrid silicon SOA or 2R regenerator [130–132]
III/V-based waveguides, silicon waveguides, doped silica and ∼0.1 dB/m propagation loss, ULLW delays or storage
and silicon-oxynitride waveguides on all integration scales, times of ∼1 μs can be achieved, i.e. 40 times the packet
from nanophotonic microrings to fiber-like larger footprint length.
ULLWs, as was shown in the overview of Fig. 1. Additional Fully integrated gyroscopes have been proposed in lit-
reductions in loss will occur with improved lithography to erature, with target resolutions of 10 ◦ /h [76, 133]. The
reduce edge scattering and deuterium process gasses to re- technology reviewed in this paper shows that resonators
duce hydrogen absorption. with a Q of about 100 million are possible on a fully in-
For ULLWs to be practically useful, functional com- tegrated PIC. As compared to the work reported in [76],
ponents and a robust fabrication technology are required. that implies that resolutions of 0.1 ◦ /h should be achiev-
We have reviewed high-Q resonators, grating and AWG able, bringing such PICs on par with bulky ring laser gyro-
based filters, splitters, couplers, and combiners, and fully scopes and fiber optic gyroscopes for the most demanding
integrated PICs, using thermo-optic switches. These results applications. We further note that the large birefringence
prove the versatility of this technology and its building [55] and high power handling capability of the wave-
blocks, and show that a passive ultra-low loss integration guide [134] and the integration of high-power photodiodes
platform is now available. [135] will allow for a further boost in sensitivity and noise
The main strength of using Si3 N4 /SiO2 as waveguide reduction.
materials is the compatibility of the materials and fabrica- Another interesting application is on-chip single-mode
tion technology with the well-quantified, mature, and robust narrow-linewidth lasers. A gain element (SOA) can be inte-
CMOS fabrication infrastructure. This means that there is grated with an ULLW to extend the laser cavity, much like
maximum control over the design dimensions, i.e. deposited an external-cavity laser. If we assume this ULLW to have in-
layer thicknesses and lithographic resolution based on deep- significant losses, which is valid for cavities up to a few me-
UV lithography. Moreover, the use of stoichiometric Si3 N4 ters, and assume all other design parameters to stay the same
leads to tight control over the index of refraction. The ap- (SOA length and mirror strength), the Schawlow-Townes
proach of design-by-geometry, i.e., optimizing waveguide linewidth ν scales with the cavity length L according to
performance by dimensional control only, while sticking ν ∼ L−2 [136]. Typical DFB laser have lengths of 0.3 –
to a single high-index core material, is shown to be a very 1 mm and linewidths in the range of 1 – 10 MHz. It can eas-
valid approach, which currently outperforms all other ap- ily be seen that the fundamental linewidth limit is pushed
proaches. We also reported results obtained with PICs fab- below 1 kHz when cavities longer than 10 cm are used. Of
ricated in a CMOS foundry, which proves the compatibility course, other (technical) noise sources can still broaden this
with its infrastructure in practice. linewidth. Also care has to be taken to ensure large enough
A purely Si3 N4 /SiO2 based platform is limited in func- side-mode suppression when the cavity increases. Using an
tionality, however, to passives and possibly thermo-optic ULLW cavity with a low coupling strength sidewall grating
phase tuning. Acknowledging the strengths of this plat- can ensure that by creating a narrow-bandwidth reflection
form, over the last few years a strong push has developed spectrum [83].
to heterogeneously integrate it with silicon and germanium Similarly, low-noise mode-locked lasers can benefit
photonics and with III/V and hybrid silicon III/V photon- from an increased cavity length. According to the work in
ics. We have reviewed the various approaches and showed [137] the phase noise corner frequency scales linearly with
how these approaches lead to PICs with impressive func- cavity length, assuming a lossless cavity extension, as can
tionalities, performance, and levels of integration. As a last be done using ULLWs up to a few meters. With a typical
point we reviewed the fabrication technology trade-offs and f−2 phase noise slope for quantum-limited noise perfor-
highlighted a unique fabrication flow that is able to com- mance [138], this means that the phase noise drops −20 dB
bine real ULLW performance with both silicon and III/V for every factor of ten in cavity length increase. Low-noise
functionalities. high-repetition rate mode-locked lasers, e.g., for microwave

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16 M. J. R. Heck et al.: Ultra-low loss waveguide platform and its integration with silicon photonics

photonics applications, can then be realized by harmon-

the Silicon Photonics Center at the University of California
ically mode-locking a long-cavity laser. As an exam- Santa Barbara.
ple, state-of-the-art fundamentally mode-locked lasers at
10 GHz show a phase noise of −60 dBc/Hz at 10 kHz Jared F. Bauters received his BSEE
offset [139]. By 100× harmonically locking a 100-MHz from the University of Notre Dame in
cavity, corresponding to a 1-m ULLW cavity, phase noise 2008 and his MSEE from the University
performance of −100 dBc/Hz (−140 dBc/Hz) at 10-kHz of California Santa Barbara in 2010. He
(1 MHz) offset can be expected. Supermode noise has to obtained the PhD degree from UCSB in
be suppressed though, e.g., by using an intracavity etalon 2013, where he worked on the design,
fabrication, and characterization of opto-
[140, 141]. Similarly, on-chip oscillators benefit from long
electronic devices using an integrated sil-
and high-Q cavities as the phase noise scales with Q−2
icon and ultra-low-loss, silica-based pla-
according to Leeson’s equation [142]. nar waveguide platform. He currently works for Aurrion Inc.,
This overview of estimates shows the potentially huge Santa Barbara.
impact the integration of ULLWs can have on PICs and their
applications, improving performance by orders of magni- Michael L. Davenport received the Un-
tude as compared to the state-of-the-art. Together with the dergraduate degree in optical engineer-
prospect of a CMOS-compatible technology for most of ing from the University of Alabama,
the process flow, this means that high-end PICs and appli- Huntsville, in 2007, and the Masters de-
cations can become available in large volume at low cost. gree in electrical Engineering from the
University of California, Santa Barbara,
Moreover, we want to point out that the close integration of
in 2009, where he is currently pursuing
a PIC allows for energy-efficient performance of both pho-
the Ph.D. degree in electrical engineer-
tonics, and high-bandwidth electronic control loops and ing. His current research interests include
drivers, making this an extremely promising and versatile low-noise mode-locked lasers for applications in optical net-
technology for compact, ubiquitous and/or hand-held tech- works.
nology.
Daryl T. Spencer received the B.S. in en-
Acknowledgements. We thank Josh Conway, Sanjay Raman gineering physics from the University of
and Scott Rodgers at DARPA, James Adleman and Bill Jacobs Tulsa, in 2010, and the M.S. degree in
at SPAWAR, Rene Heideman and Arne Leijnse at Lionix, Arnold electrical and computer engineering from
Chen, Alexander Fang, and Greg Fish at Aurrion, Jon Barton, the University of California, Santa Bar-
Michael Belt, Dan Blumenthal, Jock Bovington, Demis John, bara, in 2012, where he is currently work-
Renan Moreira, Molly Piels, Sudha Srinivasan, Jason Tien at ing towards the Ph.D. in electrical and
UCSB, Daoxin Dai at Zhejiang University, and Sam Dimashski computer engineering as an NSF Fellow.
at Northrup Grumman for discussions and assistance. We thank His research involves the active integra-
DARPA MTO for funding much of this research under the E-PHI tion of ultra-high quality factor monolithic resonators for high
and iPhoD programs, with grant numbers HR0011-12-C-0006 performance microwave systems.
and HR0011-09-C-0123.
John E. Bowers is a Professor in the De-
partment of Electrical and Computer En-
Received: 18 November 2013, Revised: 14 February 2014
gineering, University of California Santa
Published online: 10 March 2014 Barbara, where he is the Fred Kavli Chair
in Nanotechnology and the Director of
Key words: silicon photonics, photonic integrated circuits, inte-
the Institute for Energy Efficiency. He
grated optoelectronics, integrated optics, planar waveguides, res-
received the M.S. and Ph.D. degrees
onators, gratings, silica-on-silicon, hybrid silicon photonics, het-
from Stanford University, Stanford, CA.
erogeneous integration.
He was also with AT&T Bell Laboratories
and Honeywell. He has authored or coauthored eight book
Martijn J. R. Heck is Associate Profes- chapters, 450 journal papers, and 700 conference papers. He
sor in the Department of Engineering, holds 52 patents. Dr. Bowers is a member of the National
Aarhus University, Denmark, where he Academy of Engineering, and a Fellow of the Optical Soci-
works on photonic integration and its ap- ety of America (OSA) and the American Physical Society. He
plications. He received the M.Sc. degree is a recipient of the OSA Holonyak Prize, the IEEE LEOS
in applied physics and the Ph.D. degree William Streifer Award, and the South Coast Business and
from the Eindhoven University of Tech- Technology Entrepreneur of the Year Award. He was the re-
nology, in 2002 and 2008, respectively. cipient of the EE Times Annual Creativity in Electronics Award
From 2007 to 2009, he was a Postdoc- for Most Promising Technology for the hybrid silicon laser in
toral Researcher at the COBRA Research Institute and the 2007.
Laser Centre, Vrije Universiteit, Amsterdam. From 2009 to
2013, he was Research Scientist and Associate Director of


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Laser Photonics Rev. (2014) 17

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