COMSATS UNIVERSITY ISLAMABAD

Department of Electrical & Computer Engineering

Course name: Digital Logic Design (CSC 241)

Lab title: Boolean Function Implementation using Universal Gates

Submitted by:
Student Name Registration #
1. Nayyab Kanwal FA23-BCE-088
2. Saman Kalsoom FA23-BCE-099
3. Zufishan Abbasi FA23-BCE-116

Submitted to: Dr.Irfan Ullah

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Objectives

• This lab is designed to simulate and implement any logic function using universals gates
(NAND/NOR).
• To build the understanding of how to construct any combinational logic function using
NAND or NOR gates only.

Equipment Required:
• KL-31001 Digital Logic Lab
• Logic gates ICs
o 4011 quad 2-input NAND

Lab Tasks:
In-Lab: Implementing any logic expression by using only NAND gates

Lab Task 1: Verification of NOT function:

Fig.1(NOT gate using NAND gate)

Inputs Output
A A¢
0 1
1 0

Table 1

ii. Experimental verification:

Inputs Output
A A¢
0 1
1 0

Table 2

Circuit Diagram:

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iii. Proteus simulation:

Explanation:
The NOT gate, implemented using a NAND gate, inverts the input signal. When the input is
logic 0, the output is logic 1, and when the input is logic 1, the output becomes logic 0. This is
verified both theoretically and through experimental results, where the truth table for both
confirms the inversion of the input. The Proteus simulation also shows the expected behavior,
confirming the proper functioning of the NOT gate.

Lab Task 2: Verification of AND function:

Fig.2(AND gate using NAND gate)

INPUTS OUTPUT
A B F=AB
0 0 0
0 1 0
1 0 0
1 1 1

Table 3

ii. Experimental verification:

INPUTS OUTPUT
A B F=AB
0 0 0
0 1 0
1 0 0
1 1 1

Table 4

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 Circuit Diagram:

iii. Proteus simulation:

Explanation:
The AND gate is implemented using two NAND gates, where the first NAND gate
provides the complement of the input, and the second NAND gate inverts it back. When both
inputs are logic 1, the output is logic 1, otherwise, the output remains logic 0. The truth table
confirms this behavior through both theoretical and experimental verification. The Proteus
simulation further demonstrates the correct output for each combination of inputs.

Lab Task 3: Verification of OR function:

Fig.3(OR gate using NAND gate)

INPUTS OUTPUT
A A¢ B B ¢ F=A+B
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 1

Table 5

ii. Experimental verification:

INPUTS OUTPUT

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 A A¢ B B¢ F=A+B
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 1

Table 6

Circuit Diagram:

iii. Proteus simulation:

Explantion:
The OR gate is constructed using three NAND gates, where the inputs are inverted first, and
then combined to produce the final output. When both inputs are logic 0, the output is logic 0.
When either input is logic 1, the output becomes logic 1. This behavior is confirmed through
theoretical verification, matching the experimental truth table, and further validated by the
Proteus simulation, ensuring correct functionality of the OR gate design.

Lab Task 4: Verification of XOR function:

Fig.3(XOR gate using NAND gate)

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 TruthTable:

INPUTS OUTPUT
¢
A A B B¢ AB¢
AB ¢ F=A’B+AB’
0 1 0 1 0 0 0
0 1 1 0 1 0 1
1 0 0 1 0 1 1
1 0 1 0 0 0 0

Table 7

ii. Experimental verification:

INPUTS OUTPUT
¢
A A B B¢ AB¢
AB ¢ F=A’B+AB’
0 1 0 1 0 0 0
0 1 1 0 1 0 1
1 0 0 1 0 1 1
1 0 1 0 0 0 0

Table 8

iii. Proteus simulation:

Explantion:
The XOR gate is designed using NAND gates, where both A'B and AB' are derived by
inverting the inputs and using combinations of NAND gates to generate the exclusive OR
functionality. When the inputs are different, i.e., one is logic 1 and the other is logic 0, the output
is logic 1. If both inputs are the same, the output remains logic 0. Theoretical and experimental
truth tables align, confirming the XOR operation, and the Proteus simulation demonstrates the

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accurate functioning of the XOR gate.
Lab Task 5: Verification of XNOR function:
i. Theoretical Verification:
Diagram:

Fig.4(XNOR gate using NAND gate)

TruthTable:

INPUTS OUTPUT
¢
A A B B¢ AB ¢
AB ¢ F=AB+A’B’
0 1 0 1 0 1 1
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 1

Table 8

ii. Experimental verification:

INPUTS OUTPUT
¢
A A B B¢ AB ¢
AB ¢ F=AB+A’B’
0 1 0 1 0 1 1
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 1

Table 9

Circuit Diagram:

iii.Proteus simulation:

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Explantion:
The XNOR gate is implemented using NAND gates to realize the equation \( F = AB + A'B' \).
This gate outputs logic 1 when both inputs are the same (either both logic 0 or both logic 1). For
different inputs, the output is logic 0. The theoretical truth table, verified through experiments,
confirms this behavior, showing logic 1 when inputs are equal. The Proteus simulation
accurately demonstrates the XNOR gate’s performance, matching the expected truth table
outputs.

Post Lab:
Task 01: Simulate NAND, XOR and XNOR gates in Proteus software, by using only NOR
gates. Verify their truth tables.

i. NAND gate by using NOR gate:

INPUTS OUTPUT
¢ ¢
A A B B F= A¢+B¢
0 1 0 1 1
0 1 1 0 1
1 0 0 1 1
1 0 1 0 0

Table 1

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Proteus Simulation:

ii. XOR gate by using NOR gate:

INPUTS OUTPUT
¢
A A B B¢ ¢
AB ¢
AB F= A¢B+ AB¢
0 1 0 1 0 0 0
0 1 1 0 1 0 1
1 0 0 1 0 1 1
1 0 1 0 0 0 0

Table 1

Proteus Simulation:

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 iii. XNOR gate by using NOR gate:
TruthTable :

INPUTS OUTPUT
¢
A A B B¢ AB ¢
AB ¢ ¢
A B+ AB ¢
F= (A¢B+ AB¢ )¢
0 1 0 1 0 0 0 1
0 1 1 0 1 0 1 0
1 0 0 1 0 1 1 0
1 0 1 0 0 0 0 1

Table 2

Proteus Simulation:

Critical Analysis:
The lab involves implementing and verifying logic functions (NOT, AND, OR, XOR, XNOR)
using NAND gates and subsequently NOR gates. Theoretical, experimental, and simulation
approaches in Proteus are used for verification. Each gate's implementation is tested through
detailed truth tables and circuit diagrams. The final step involves constructing NAND, XOR, and
XNOR gates using NOR gates and validating their functionality through simulations. This
comprehensive exercise aims to solidify understanding of constructing logic functions with
universal gates and ensure accuracy in practical applications.

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