Fundamentals of Sigma-Delta ADCs
Jinseok Koh, Ph.D.
Texas Instruments Inc.
Dallas, TX
IEEE SSCS Dallas Chapter, June 2007
Why Analog to Digital Conversion?
ü Naturally occurring signals are analog signal
ü Human beings perceive and retain information in analog form
ü BUT, Analog signal is more sensitive to noise than digital signal
Jinseok Koh (
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How Analog to Digital Conversion?
110
101 101
101 101
101
100
100 100
011
010 010
010 010
001
000
t1 t2 t3 t4 t5 t6 t7 t8 t9
1. Sample analog signal
2. Quantize sampled analog signalà Quantization noise
3. Faster sampling time, better accuracy
4. Higher quantization levels, better accuracy
Continuous Time Signal
Amplitude
fB, band of Time
interest Signal
Power
0 fC fB
Frequency
Signal frequency, fC = band of interest, fB (Maximum frequency of the signal)
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Typical Architecture for Analog to Digital Conversion
ADC
Continuous Sampled Digital
Analog
Time Signal Analog Signal Signal
Signal
Anti
Aliasing Quantization DSP
S/H
Filter
Nyquist Rate vs. Oversampled
Modeling of Quantizer
• Quantizer is non-linear building block
– Need modeling for simplifying the analysis
• White additive noise assumptions
– It is not fulfilled in many applications, However
– It makes analysis easy and makes possible the use of z-tansformation
Quantization Noise
• Quantity of in-band noise depends on the over-sampling ratio
– SNR = 10log(s x2) -10log(s n2) +3.01r(dB), where
– s x2 and s n2 are input signal power and in-band noise power respectively, and
– r is defined by over-sampling ratio, fs/2fb=2r
Pervez M. Aziz, “An overview of sigma-delta converters,”IEEE Signal processing Magazine, pp 61-84, Jan. 1996
Over-sampling and Noise Shaping
Every doubling of sampling frequency
1 RLVH leads approximately 3 dB enhancement in SNR
%DQGRI ,QW
HUHVW
IV IV IV
Noise shaping pushes quantization noise
to higher frequency resulting in suppressing
Q. noise in the band of interest
How to Shape the noise?
H(z) 1
Y(z) = ⋅ X(z)+ ⋅ E(z)
1+ H(z)G(z) 1+ H(z)G(z)
STF NTF
If H(z) = z-1/1-z-1 and G(z)=1, NTF and STF will be:
Y(z) Y(z)
NTF = = 1− Z −1 STF = = Z −1
E(z) X(z)
Jinseok Koh (
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Jinseok Koh (
[email protected])
Jinseok Koh (
[email protected])
Example, 2nd order Sigma-Delta ADC
Output of the 1st integrator Output of the 2nd integrator
ü The dynamic range at the output of the two integrators is limited
ü Input signal attenuation by 6 dB
Jinseok Koh (
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Noise Shaping
2nd order
1st order
Band of interest
In-band quantization noise is suppressed more with 2nd order
Single-bit or Multi-bit ? S
Single Bit
• Feedback DAC inherently linear. So no HD distortion.
• Need a faster Amplifier
• Lower SQNR for a given modulator order
Multi Bit
• Gives higher SQNR
• Relaxed opamp specs due to smaller step size
• DAC non-linearity is a performance limit
• Require dynamic element matching
Summary
• Sigma-delta ADC provide trade-offs between:
– Power consumption,
– Over-sampling ratio (OSR)
– System performance (SNR)
• High OSR implies:
– Lower number of quantization levels
– Lower modulator order, but
– More demanding settling requirements for the analog building blocks
A Sigma-Delta ADC with a built-in Anti-aliasing filter
for Bluetooth receiver in 130 nm digital process
Jinseok Koh
Wireless Analog Technology Center
Texas Instruments Inc.
Dallas, TX
Published in CICC2004
Introduction
• RF input signal is amplified by two stage Amplifier, LNA and TA.
• TA output is down converted and filtered by Direct-Sampling Mixer
(DSM).
• IFA amplifies mixer output signal operating at 75 Mhz.
• Sigma-Delta ADC converts 75 MHz IFA output to 37.5 MHz digital
words.
ADC Requirements
• 60 dB Dynamic range at 1 Mhz signal bandwidth
– 2nd order sigma-delta ADC
– 5 level quantizer
– 37.5 MHz sampling frequency.
• Gain Control
– O dB and 14 dB gain option is required for system AGC
function.
• Low Power consumption
• Low cost
Noise budget
Noise Budget Conditions:
1. Fs=37.5 MHz
600
2. BW=1 MHz
3. 5 level Flash
500
400 (unit = µV)
Noise [uVrms]
Noise_tot Quant. Amp. kT/C Ref
564 561 75 18.8 18
300
200
100
0
Noise Quant. Amp. kT/C Ref
Noise Sources
• Quantization noise is a dominant noise source.
– Unit capacitance element is selected based on considering
mismatch effect.
– Noises from amplifier and reference buffer are not critical.
– Power consumption of amplifier is minimized since noise from it
is negligible compared to the high in-band quantization noise.
Jinseok Koh (
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Required building blocks
FIR Filter Decimation Buffer
by 2 3bit
Input
Sigma-Delta out
2 x1
ADC
• Based on power consumption and noise analysis, following
functions are required.
– Decimation by Two: sampling frequency 37.5 MHz can
provides enough Dynamic Range utilizing 5 level flash ADC.
– Anti-alias filtering: Decimation by two function causes folding
noise.
– Buffering: buffer amplifier is required to avoid charge sharing
between Switched capacitor FIR filter and sampling circuits in
Sigma-Delta ADC.
Proposed Architecture
Vin Z-1 Z-1
2 a2
1 - Z-1 1 - Z-1
b1 b2
3 Bit
OUT
ILA Decoder
• Decimation, anti-aliasing filtering is merged with sampling
circuits.
– Saved power consumption and silicon area since it avoids
the buffer.
• Second order Sigma-Delta ADC with 5 level flash.
• ILA DEM is used to suppress mismatch energy from DAC in
feedback loop.
FIR Anti-aliasing Filter
y ( n) = x (n ) + 3 x( n − 1) + 3 x( n − 2) + x( n − 3)
-80 dB at 36.5 MHz
• 60dB attenuation is required to suppress folding noise by
system simulations.
• Third order FIR filter is chosen and provides 80 dB attenuation
at folding frequency band edge.
Jinseok Koh (
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FIR Anti-aliasing Filter and Decimation
P1 P2 P3
Input P1 Cp1 I2 P2 Cp2 I1 P3 Cp3 I3
P1
Cp1, 3Cp1
I2 P1 I1 I1 P2 I3
I3 P3 CM
P2
P1 P2
Cp2, 3Cp2
3Cp1 I3 3Cp2 I3 P3 3Cp3 I1
P3
Cp3, 3Cp3
I3 I3 P1 I3 I3 P2 I1 I1 P3 P4
Cp4, 3Cp4
P4 P5 P6 P5
P4 Cp4 I2 P5 Cp5 I1 P6 Cp6 I3
Cp5, 3Cp5
5 level Vrefp P6
I2 P4 I1 I1 P5 I3 P6 DAC
I3 Vrefm Cp6, 3Cp6
I1
P4 3Cp4 I1 P5 3Cp5 I2 P6 3Cp6 I2
I2
I1
I1 P4 I2 P5 I2 P6
I3
• 6 phase clock signals are utilized to implement FIR filter.
• On Pi phase, input is sampled at Cpi and 3Cpi capacitors,
• On I3 phase, Cp3, 3Cp2, 3Cp1 and Cp6 is dumped into
integrating capacitor.
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Gain control
High Gain mode
LG
Csh CM
HG
N1
Input
N2
Cs
N2 N1
• Gain control function is implemented in FIR sampling block by
adding the high gain mode switched capacitor circuits in
parallel with each capacitor in SC FIR filter.
• Gain is defined by the ratio between sampling capacitors and
integrating capacitor (C M).
Comparator
VINP Ci
Cr
REFP
N2 OUTM
COMP
Ci
VINM OUTP
N2
Cr
REFM LATCH
N1 N2
• Switched capacitor comparator is used to build 5 level
quantizer.
• Capacitor ratio between Ci and Cr is chosen to have threshold
voltage for each comparator.
• Capacitor size is optimized to be minimum considering
decision speed, resolution (mismatch) and offset.
Jinseok Koh (
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Two Tone Measurements
f1 = 1 MHz f2 = 2.2 MHz
Number of FFT : 65536
IM3
• -8 dBFS sine signals at 1 MHz (f1) and 2.2 MHz (f2) are applied.
• -80 dBc IM3 shows at 200 kHz.
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Measured SNDR
SNDR vs. Input 60 dB SNDR at –4 dBFS input
70
60
50
SNDR [dB]
40
High Gain
30
Low Gain
20
10
0
-70 -60 -50 -40 -30 -20 -10 0
Input Amplitude [dBFS]
• Peak SNDR for high gain mode is smaller since harmonics
come earlier than low gain mode due to amplifier speed.
Jinseok Koh ([email protected])
Performance summary
Technology 130nm Digital CMOS Process
Sampling Frequency 37.5 MHz
Signal Bandwidth 1 MHz
Peak SNDR1 60 dB
Peak SNDR2 57 dB
Dynamic Range 67 dB
Overall Dynamic Range 77 dB
Input Range 1.4 Vpp (differential)
Power Consumption 1.6 mW
Voltage Supply 1.58 V
Core Area 0.2 mm 2
• Sinusoidal signal at 360 kHz is used for performance measurements.
• Peak SNDR1 : when 0 dB gain option is selected.
• Peak SNDR2 : when 14 dB gain option is selected.
Conclusion
• Second order 5 level Sigma-Delta ADC with built-in anti-
aliasing filter is realized.
• Decimation by two function relaxed settling and slew rate
requirement.
• SC FIR filter for anti-aliasing is merged with sampling circuit.
– Achieved power saving and cost reduction
• Two step gain control increases overall Dynamic Range.
– Relax the automatic gain control burden in bluetooth
system.
• Building block parameters are optimized based on noise
analysis and realized low power consuming ADC.
66dB DR 1.2V 1.2mW Single-Amplifier
Double-Sampling 2nd-order ? S ADC for
WCDMA in 90nm CMOS
Jinseok Koh
Wireless Analog Technology Center
Texas Instruments Inc.
Dallas, TX
Published in ISSCC2005
Objectives
• For a given performance requirement, power consumption and
area are optimized by:
– Increasing sampling frequency à Double sampling technique
– Increasing modulator order à Single Amplifier topology
– Higher number of levels in Quantizer à 5-level quantizer with ILA
Double sampling
• Advantages:
– Efficient technique to double the OSR
• Doesn’t need faster op-amp settling
• Provides improvement of SQNR by 6n+3 dB (n=order)
• Disadvantage:
– Mismatch between capacitors creates noise folding
&X Noise Folding
3 &' 3
9 LQ
3 3 Alternating Gain Effect
3 &' 3
3 3 Inherent Capacitor Mismatch
Jinseok Koh (
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Noise Folding In Double Sampling
• Alternating gain effect
à Noise at Fs/2 is folded into Signal bandwidth
Noise folding Noise folding
(Input sampling circuit) (DAC in feedback path)
gain : 1
gain : 1 ?C
gain :
?C C D2
gain :
CD2
•Noise at Fs/2 is suppressed by •No filtering on quantization noise
- Anti-aliasing filter
- Pre-filtering
Conventional Double Sampling DAC
• On P1 phase,
Stored charge in CD1 :
CD1(Vrefp-Vrefm)
•On P2 phase,
Stored charge in CD2 :
CD2(Vrefp-Vrefm)
• Requires two sets of
switched capacitor DACs
• Mismatch on stored
charge causes alternating
gain effect
Proposed SC DAC element for double sampling
• Advantages of this approach vs. conventional approach:
– Only one pair of capacitors needed
– No “alternating-gain”effect
– No additional circuitry needed for matching purposes
Operation of Proposed SC DAC element
On P1 Phase: On P2 Phase:
• On phase P1 the charge transferred to Integrating Capacitor is:
– Qu = Cd(Vrefp-Vrefm)
– Qu is equal to the charge stored into Cd
– This charge will be used during next integration phase
Conventional 2nd Order Sigma-Delta ADC
Each Summing Node requires an Amplifier
• Conventional Sigma-delta ADC:
– Needs an amplifier per summing node
– Poles and zeros are chosen by ai and bi ,where i=1,2
Single Amplifier 2nd Order Sigma-Delta ADC
Summing node
z −1 1−p⋅z −1−q⋅z−2
STF = NTF =
1−p⋅z −1−q⋅z−2 + z −1G(z)
−1 −2 −1
1 − p ⋅ z − q ⋅ z + z G(z)
Jinseok Koh ([email protected])
SNDR vs. Input power
SNDR vs. Input
70
60
50
SNDR [dB]
40
30
20
10
0
-70 -60 -50 -40 -30 -20 -10 0
Input Amplitude [dBFS]
• 63dB peak SNDR happens at -3dBFS input sinusoidal
Die Photography for dual channel ADCs
I-channel Q-channel
• Implemented in 90nm 5 metal digital CMOS process
Jinseok Koh (
[email protected])
Performance Summary
Technology 90 nm Digital CMOS
Signal Bandwidth 1.94 MHz
Clock Frequency 38.4 MHz
Sampling Frequency 76.8 MHz
Peak SNDR 63 dB
Dynamic Range 66 dB
Input Range 1.5 Vpp (differential)
Voltage Supply 1.2 V
Power Consumption 1.2 mW per ADC
2
Core Area 0.2 mm per ADC
Conclusions
• Second order 5 level Single Amplifier Sigma-Delta ADC with double
sampling technique was realized in 90 nm CMOS.
• By using double sampling technique, OSR is doubled with no
increase of power consumption and silicon area.
• Single-capacitor double-sampling DAC solved “alternating-gain”
error effect.
• 2nd order modulator is implemented using a Single-amplifier
architecture. Higher order modulator is feasible.
• Low power consumption: 1.2mW for WCDMA, measured with a 1.2V
power supply.
• 66dB dynamic range was achieved in 1.94MHz bandwidth.
