Modeling of

Combinational
and Sequential
Logic Circuits
using Verilog
HDL

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

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 Basic syntax for multiple-input gates is:
Multiple_input_Gate_type [instance_name] (output, input1, input2,……..inputn);

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
 Basic syntax for multiple-output gates is:
Multiple_output_Gate_type [instance_name] (output1, output2,……..outputn, input);

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 Basic syntax for tristate-gates is:
Tristate_type [instance_name] (output,input,control);

Out=in if con=1
Else out=Z

Out=in if con=0
Else out=Z

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 Out=in if con=1
Else out=Z

Out=in if con=0
Else out=Z

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

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 module adder_4bit (S, COUT,A,B);
output [3:0]S ;
output COUT ;
input [3:0] A ;
input [3:0] B ;
wire [2:0]C;
FullAdder FA0(S[0],C[0],A[0],B[0],1'b0);
FullAdder FA1(S[1],C[1],A[1],B[1],C[0]);
FullAdder FA2(S[2],C[2],A[2],B[2],C[1]);
FullAdder FA3(S[3],COUT,A[3],B[3],C[2]);
endmodule
MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
 module FS(a,b,c,difference,borrow);
input a,b,c;
output difference,borrow;
wire l,m,n,o,p;
xor g1(l,a,b);
xor g2(difference,l,c);
and g3(n,m,b);
and g4(p,b,c);
and g5(o,m,c);
or g6(borrow,n,o,p);
not g7(m,a);
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

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 module srffgl(s,r,clk,q,qb);
input s,r,clk;
inout q,qb;
wire s1,r1;
nand n1(s1,s,clk);
nand n2(r1,r,clk);
nand n3(q,s1,qb);
nand n4(qb,r1,q);
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module srffgl(d,clk,q,qb);
input d,clk;
inout q,qb;
wire s1,r1;
nand n1(s1,d,clk);
nand n2(r1,d,clk);
nand n3(q,s1,qb);
nand n4(qb,r1,q);
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 moduleRegister4 (Q3,Q2,Q1,Q0,D3,D2,D1,D0,Clock,ClearN);
Output Q3,Q2,Q1,Q0; // output data
Input D3,D2,D1,D0; // input data
Input Clock,ClearN; // clock and clear
DFF FF0 (Q0,D0,Clock,ClearN);
DFF FF1 (Q1,D1,Clock,ClearN);
DFF FF2 (Q2,D2,Clock,ClearN);
DFF FF3 (Q3,D3,Clock,ClearN);
endmodule
MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
 module ripple_count(j,k,clock,reset,q,qb);
input j,k,clock,reset;
output wire [3:0]q,qb;
jkff JK1(j,k,clock,reset,q[0],qb[0]);
jkff JK2(j,k,q[0],reset,q[1],qb[1]);
jkff JK3(j,k,q[1],reset,q[2],qb[2]);
jkff JK4(j,k,q[2],reset,q[3],qb[3]);
endmodule
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 module SRFF(q,s,r,clk);
input s,r,clk;
output q;
reg q;
always @(posedge clk)
begin
case({s,r})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bx;
endcase
end
endmodule

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 module dff(clk,D,Q);
input clk;
input D;
output Q;
reg Q;
always @(posedge clk)
begin
if(clk==1)
Q=D;
else
Q=0;
end
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module JKFF(q,j,k,clk);
input j,k,clk;
output q;
reg q;
always @(posedge clk)
begin
case({j,k})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
end
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module T_FF(clk,t,q);
input clk;
input t;
output q;
reg q=0;
always @(posedge clk)
begin
case(t)
1'b0:q=q;
1'b1:q=~q;
endcase
end
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module sisomod(clk,clear,si,so);
input clk,si,clear;
output so;
reg so;
reg [3:0] tmp;
always @(posedge clk )
begin
if (clear)
tmp <= 4’b0000;
else
tmp <= tmp << 1;
tmp[0] <= si;
so = tmp[3];
end
endmodule
MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
 module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );
output dout ;
reg dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ,reset, load;
wire clk , reset, load;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp <= 0;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};
end end
endmodule
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 module COUNTER(clk, clr,count);
input clk, clr;
output [3:0]count;
reg [3:0]tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp = 4'b0000;
else
tmp = tmp + 1'b1;
end
assign count = tmp;
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module counter( clk, count );
input clk;
output[3:0] count;
reg[3:0] count;
wire clk;
initial
count = 4'b1111;
always @( negedge clk )
count[0] <= ~count[0];
always @( negedge count[0] )
count[1] <= ~count[1];
always @( negedge count[1] )
count[2] <= ~count[2];
always @( negedge count[2] )
count[3] <= ~count[3];
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
 module halfadder(s,c,a,b); module fa_da(a,b,cin,sum,cout);
input a,b; input a,b,cin;
output s,c; output sum,cout;
assign s=a^b; assign sum=a^b^cin;
assign c=a&b; assign cout=(a&cin)|(b&cin)|(a&b);
endmodule endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module mux(y,s,i);
input [2:0]s;
input[7:0]i;
output y;
assign y= (~s[2] & ~s[1] & ~s[0] & i[1]) | (~s[2] &
~s[1] & s[0] & i[2]) | (~s[2] & s[1] & ~s[0] &
i[3]) | (~s[2] & s[1] & s[0] & i[4]) | (s[2] & ~s[1] &
~s[0] & i[5]) | (~s[2] & s[1] & ~s[0] & i[6]) | (s[2] &
s[1] & ~s[0] & i[7]) | (s[2] & s[1] & s[0] & i[8]);
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module binary_to_gray(g,b);
input [3:0]b;
output[3:0]g;
assign g[3]= b[3];
assign g[2]= b[2]^b[3];
assign g[1]= b[1]^b[2];
assign g[0]= b[0]^b[1];
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module parity(even,odd,d);
input [8:0]d;
output even, odd;
wire e0,e1,e2,e3,f0,f1,h0; d[0] e0
assign e0=d[0]^d[1]; d[1] f0
assign e1=d[2]^d[3]; d[2]
assign e2=d[4]^d[5]; d[3] e1 h0
even
assign e3=d[6]^d[7]; d[4] e2 odd
assign f0=e0^e1; d[5]
assign f1=e2^e3; d[6] f1
assign h0=f0^f1; d[7] e3
assign odd=h0^d[8]; d[8]
assign even=~odd;
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module PriorityEncoder_DataFlow(code,data);
input[7:0]data;
output[2:0]code;
wire [7:0]w;
assign w[0]=(~data[0]);
assign w[1]=(~data[1]);
assign w[2]=(~data[2]);
assign w[3]=(~data[3]);
assign w[4]=(~data[4]);
assign w[5]=(~data[5]);
assign w[6]=(~data[6]);
assign w[7]=(~data[7]);
assign code[0]=(w[7]&w[6]&w[5]&w[4]&w[3]&w[2]&data[1])|
(w[7]&w[6]&w[5]&w[4]&data[3])|(w[7]&w[6]&data[5])|data[7];
assign code[1]=(w[7]&w[6]&w[5]&w[4]&w[3]&data[2])|
(w[7]&w[6]&w[5]&w[4]&data[3])|(w[7]&data[6])|data[7];
assign code[2]=(w[7]&w[6]&w[5]&data[4])|(w[7]&w[6]&data[5])|(w[7]&data[6])|data[7];
endmodule
MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
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MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
 module dflipflopt_b;
reg d;
reg clk;
module dflipflopmod(q, d, clk);
wire q;
output q;
input d;
dflipflopmod uut (.q(q),.d(d), .clk(clk) );
input clk; initial begin
reg q; // Initialize Inputs
always @(posedge clk) d = 0;
q=d; clk = 0;
endmodule end
always #3 clk=~clk;
always #5 d=~d;
endmodule

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

  The following Verilog code is supposed to describe a circuit that has an 8-
bit data input, an 8-bit data output, plus two additional single-bit outputs.
The over_flow output is strictly combinatorial. You may assume that the
operations to produce data_out, carry_out and over_flow are correct (i.e.
the functional specification for these values is correct). However, syntax
errors for these statements do exist.

 Examine the code below and identify any errors that would prevent this
code from compiling and synthesizing properly. These errors may include
syntax errors, logical design errors or needed lines that are missing from
the code. Indicate the modifications you would make to the code to make
it work. Include comments beside these modifications or the portion of
the code that is incorrect. There are 20 errors in the code below.

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module bad_module is (clk,
reset,
[7:0] data_in,
data_out;
carry out,
over_flow )
input clk;
input reset;
input carry_in;
input data_in;
output data_out;
output carry_out;
output over_flow;
reg [7:0] data_out;
reg carry_out, overflow;

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 always @ (posedge clk | posedge reset) ;
if reset
then
data_out = 0;
carry_out = 0;
Else

data_out = (data_in * 2) + carry_in;

carry out = ~& data_in[7,6];

over_flow = data_out(7);

end module

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN

 module bad_module (clk, (1) Removed “is” after module
reset,
data_in, (2) Removed [7:0]
carry_in, (3) Added carry_in
data_out, (4) Changed “;” to “,”
carry_out, (5) Changed “carry out” to “carry_out”
over_flow ) (6) Semicolon at the end of module definition
input clk;
input reset;
input carry_in;
input [7:0] data_in; (7) Added [7:0]
output [7:0] data_out; (8) Added [7:0]
output carry_out;
output over_flow;
reg [7:0] data_out;
reg carry_out;
MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN
 always @ (posedge clk or posedge reset) (9) Changed “|” to “or”
(10)No semicolon for always statement
if (reset) (11) Added Parentheses around “reset”
(12) Removed “then”
begin (13) Added “begin”
data_out = 0;
carry_out = 0;
end (14) Added “end”
else (15) “else” keyword must be lower case
begin (16) Added “begin”
data_out = (data_in * 2) + carry_in;
carry_out = ~& data_in[7:6]; (17) Replace “,” with “:”
end (18) Added “end”
assign over_flow = data_out[7]; (19) Changed “out7” to “out[7]”
endmodule (20) Removed space between “end” & “module”

MODULE-7 ECE2003 – DIGITAL LOGIC DESIGN