UNIT - III

Combinational Logic Design: Half adder - Full adder- Full- subtractor – Parallel Adder- Carry Look
Ahead Adder – BCD Adder – Magnitude Comparator – Encoders and Decoders – Multiplexers – Code
converters – Parity generator, Parity checker- Combinational circuit implementation using multiplexers
and decoders.

Programmable Logic Devices: PROM – EPROM – EEPROM- Programmable Logic Array (PLA) –
Programmable Array Logic (PAL) -Realization of combinational circuits using PLDs.

Adder

Definition:

Half adder:
 The circuit that will add two bits and produce a sum and a carry bit.

Full adder:
 The circuit that will add three bits and produce a sum and a carry bit.
 Adder is a combinational logic circuit, which performs the addition of two binary bits.
For, any adder produces two outputs; sum and carry. Adder circuits can be classified into
two types depending on the number of bits in the input variable.
1. Half adder
2. Full adder
Half Adder
 A logic circuit which performs the addition of two bits is called a half adder. The half adder needs
two inputs augend and addend bits; and two binary output: sum and carry.
 Fig.1.13 shows the block diagram of half adder and Table 1.12 shows the truth table of
half adder. The next step is determining the expression for output variables (sum and
 carry) by using K-map. The two variables map is used to determine the expression
because the half adder is having two input variables.
 Logic diagram
Obtain the logic circuit shown in Fig.1.14 by using the above sum and carry expression

Full adder
 A half adder has only two inputs and there is no provision to add a carry coming from the
lower order bits when multi addition is performed. For this purpose, a full adder is
designed.
 A full adder is a combinational logic circuit that performs the arithmetical sum of three
inputs bits. It consists of three inputs and two outputs.
 Two of the input variables denoted by A and B represent the two significant bits to be
added. The third input Cin represents the carry from the previous lower significant
position.
 Fig. 1.15 shows the block diagram of a full adder and Table 1.13 shows the truth table for
a full adder.
Logic diagram
 The logic diagram is constructed by using logic gates for the sum and carry of a full
adder circuit. Fig.1.16 shows the logic diagram of a full adder.

 From this simplified expression, we obtain the simplified full adder logic circuit as shown
in Fig.1.17
  The full adder can also implemented with two half adders shown in Fig.1.18. The sum
output from the second half adder is the exclusive OR of Cin and the output of first half
adder

SUBTRACTOR:
Definition:

Half Subtractor:

 The circuit that will subtract two bits and produce a barrow and difference.

Full subtractor:

 The circuit that will subtract three bits and produce a barrow and difference.

 Subtractor is a combinational logic circuit. It perform the subtraction operation. For, any
subtractor will produce a difference and borrow. Subtractor is classified based on the number of
bits performed.
1. Half subtractor 2. Full subtractor.

Half Subtractor:
 A half subtractor is a combinational logic circuit that subtracts two bits and produce their
difference and barrow.
 The half subtractor needs two inputs: minuend and subtrahend bits and two output:
barrow and difference. Fig.1.19 shows the block diagram of half subtractor and Table
1.14 shows the truth table of half subtractor.
Logic Diagram:

 The logic diagram is constructed for the above expression by using logic gate and it is
shown in Fig.1.20

Full Subtractor
 A full subtractor is a combinational logic circuit that performs subtraction involving three
bits, namely minuend bit, subtrahend bit and the barrow from the previous stage.
 Fig.1.21 shows the block diagram of a full subtractor and table 1.15 shows the truth table
for a full subtractor.
 Logic Diagram

 Logic diagram is constructed for the above two expressions by using basic gates, as
shown in Fig.1.22.
 The Boolean function for D (difference) can be further simplified of a full subtractor.

 With this simplified Boolean function circuit (Fig.1.24), a full subtractor can be
implemented. The full subtractor can also be implemented with two half subtractors and
one OR gate, as shown in Fig.1.23.
 The difference in output from the second half subtractor is the exclusive OR of Bin and
the output of the first half-subtractor, is same as the difference in the output of a full
subtractor.
 Fig 1.23 Simplified logic diagram for full subtractor

Fig 1.24 Implementation of full subtractor using two half subtractor.

4 bit Binary Parallel adder:

Definition:

Parallel binary adder:

 A circuit, consisting of n full adders, that will add two n bit binary numbers. The output
consists of n sum bits and a carry bit.
Cascade:
 To connect an output of one device to an input of another device, often for the purpose of
expanding the number of bits available for a particular function.
 In most logic circuits, addition of more than one bit is carried out. The addition of multibit
numbers can be accomplishedly using several full adders. The 4 - bit adder using full adder
circuits, is capable of adding two 4 - bit numbers resulting in a 4 - bit sumand a carry output as
shown in Fig.1.25.
 The addend and augend (4 bits) are fed into the 4 bit adder circuits simultaneously and
the additions in each position take place at the same time. This circuit is known as
parallel adder.
 Fig: 4 Bit parallel binary adder

 Let the 4 bit words to are augend be represented by A3 A2 A1 A0 = 1111 and

addend B3 B2 B1 B0 = 0011.
Input carry 1110
Augend = 1111
Addend = 0011
1 0010
↑
carry out 4 bit sum
 In a 4 - bit parallel binary adder circuit, the input to each full adder will be Ai, Bi and Ci,
and the output will be Si and Ci+1, where ‘i’ varies from 0 to 3.
 Also the carry output of the lower stage is connected to the carry input of next higher
order stage. Hence this type of adder is called ripple-carry adder.
 The least significant stage, A0, B0 and C0 (C0 must 0) are added resulting in sum S0 and
carry C1. This carry C1 becomes the carry input of second stage.
 Similarly, in the second stage, A1, B1 and C1 are added resulting in S2 and C2; in third
stage, A2, B2 and C2 are added resulting in S2 and C3 in the fourth stage, A3, B3 and C3
are added resulting in S3 and C4 which is the output carry. Thus, the circuit results in a
sum (S3 S2 S1 S0) and a carry output C4.
 In the parallel adder, each full adder carry input depends on the previous stage output.
The propagation delay (tp) of a full-adder is the time difference between the instant at
which the inputs (Ai, Bi & Ci) are applied and the outputs (Si and Ci+1) are generated.
First stage of FA produced after 1tp
Second stage of FA produced after 2tp
Third stage of FA produced after 3tp
Fourth stage of FA produced after 4tp
 If a full adder is having the propagation delay of 50 ns, the output in the fourth stage will
be generated only after 4tp (4×50 = 200 ns)
 Fig 1.26 Function symbol of 4-bit parallel adder

 One of the methods of speeding up this process is to look ahead for carry addition which
eliminates the ripple - carry delay.
 Fig.1.26 shows function symbol for the parallel adder. The inputs to this IC are two 4 bit
numbers, A3, A2, A1, A0 and B3, B2, B1, B0 and carry Cin into LSB position. The
outputs are the sum bits S3 S2 S1 S0 and the carry Cout,Cout of the MSB position.

Ripple carry adder

 A full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs (Ai, Bi; and Cin) and two outputs (Si and Cout) as illustrated in
Fig.1.27 and the gate implementation of full adder is shown in Fig.1.27.

Fig 1.27 Block diagram of full adder

 A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It is also called as a Parallel adder.
 It can be constructed with full adders connected in cascade with the carry output from
each full adder connected to the carry input of the next full adder in the chain. Fig.1.28
shows the interconnection of four full adder (FA) circuits to provide a 4-bit ripple carry
adder.
 Notice from Fig.1.28 that the input is from the right side because the first cell
traditionally represents the least significant bit (LSB). Bits A0 and B0 in the figure
represent the least significant bits of the numbers to be added. The sum output is
represented by the bits S3− S0.

Fig 1.28 Gate implementation of full adder

 Thus, the sum of the most significant bit is only available after the carry signal has
rippled through the adder from the least significant stage to the most significant stage.
 This can be easily understood if one considers the addition of the two 4-bit words:
11112+00012

Fig 1.29 Block diagram of parallel adder

 In this case, the addition of (1+1 = 102) in the least significant stage causes a carry bit to
be generated. This carry bit will consequently generate another carry bit in the next stage,
and so on, until the final carry-out bit appears at the output.
 This requires the signal to travel (ripple) through all the stages of the adder as illustrated
in Fig.1.29.
 As a result, the final Sum and Carry bits will be valid after a considerable delay. The
carry-out bit of the first stage will be valid after 3 gate delays (1 associated with the XOR
gate and 1 each associated with the AND and OR gates).
 From the schematic of Fig.1.29, one finds that the next carry-out (C2) will be valid after
an additional 3 gate delays (associated with the AND and OR gates) for a total of 6 gate
delays. In general the carry-out of a N-bit adder will be valid after 2N+2 gate delays. The
sum bit will be valid after an additional 2 gate delays after the carry-in signal.
 Thus the sum of the most significant bit 2N-1 will be valid after 2(N-1) + 2 +2 = 2N +2
gate delays. This delay may be in addition to any delays associated with the
interconnections.

Fig 1.30 Logic diagram for 4 bit Ripple carry adder

 The disadvantage of the ripple-carry adder is that it can get very slow when we
needs to add many bits. For fast applications, a better design is required.
Carry look ahead carry adder:

Fig 1.31 Full adder at stage i with Pi and Gi shown

 The carry-look-ahead adder solves this problem by calculating the carry signals in
advance, based on the input signals.
 It is based on the fact that a carry signal will be generated in two cases:
1. when both bits Ai and Bi are 1, or
2. when one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.
Thus, we can write, from Fig.1.31
Cout =Ci+1 = Ai.Bi +(Ai⊕Bi).Ci. (1)
Si = (Ai⊕Bi)⊕Ci. (2)
The “⊕” stands for exclusive OR or XOR. We can write this expression also as
Ci+1 = Gi+Pi.Ci
in which
Gi = Ai.Bi
Pi = (Ai⊕Bi)
 are called the carry generate and carry propagate term, respectively. Let us assume that
the delay through an AND gate is one gate delay and through an XOR gate is two gate
delays. Notice that the Propagate and Generate terms only depend on the input bits and
thus will be valid after two and one gate delays, respectively.
 If we uses the above expression to calculate the carry signals, we need not wait for the
carry to ripple through all the previous stages to find its proper value. Let’s apply this to a
4-bit adder to make it clear.
C1 = G0+P0.C0 (3)
C2 = G1+P1.C1 = G1+P1.G0+P1.P0.C0 (4)
C3 = G2+P2.G1+P2.P1.G0+P2.P1.P0.C0 (5)
C4 = G3+P3.G2+P3.P2.G1+P3 P2.P1.G0+P3 P2.P1.P0.C0 (6)
The Sum signal can be calculated as follows,
Si = Ai⊕Bi⊕Ci = Pi⊕Ci. (7)
 The carry-look ahead adder can be broken up in two modules: (1) the Partial Full Adder,
PFA, which generates Si, Pi and Gi as defined by the above equations and the Carry
Look-ahead Logic, which generates the carry-out bits according to equations 3 to 6.
 The 4-bit adder can then be built by using 4 FAs and the Carry Look-ahead logic block as
shown in Fig.1.32

Fig 1.32 Logic diagram of Carry look ahead carry adder

Fig 1.33 Block diagram of a 16-bit CLA Adder

 The disadvantage of the carry-look ahead adder is that the carry logic is getting
quite complicated for more than 4 bits. For that reason, carry-look-ahead adders
are usually implemented as 4-bit modules and are used in a hierarchical structure
to realize adders that have multiples of 4 bits.
 Fig.1.33 shows the block diagram for a 16-bit CLA adder. The circuit makes use
of the same CLA Logic block as the one used in the 4-bit adder. Notice that each
4-bit adder provides a group Propagate and Generate Signal, which is used by the
 CLA Logic block. The group Propagate PG of a 4-bit adder will have the
following expressions,
PG = P3.P2.P1.P0
GG = G3+P3 G2+P3.P2.G1.+P3.P2.P1.G0

BCD Adder

Definition:

BCD adder:
A BCD adder is a combinational logical circuit which adds two BCD numbers.

 A BCD adder is a circuit that adds two BCD digits in parallel and produces sum
which is also BCD. BCD number uses 10 symbols ( group of 4 bits 0000 to 1001).
BCD adder circuit must be able to do the following and it is shown in Fig.1.41.
Add two 4 bit BCD numbers using straight binary addition.
 If 4 bit sum is equal to or less than 9, the sum is valid BCD number and no
correction needed. If the 4 bit sum is greater than 9, or if a carry is generated from
the sum, the sum an invalid BCD number. Then, the digit 6 (0110) should be
added to the sum to produce the valid BCD symbols.
  Table 1.17 shows the truth table. In this table, the inputs are sum bit from the two BCD
additions and the output Y is indicating the required correction place.
 If Y = 0 (no correction needed) for 0000 to 1001 and Y = 1 (correction needed) for
 1010 to 1111. From this truth table we get the simplified expression by using 4 variable
K- map.

Expression for Y

Logic Circuit

Fig 1.41 Logic diagram of BCD adder

MAGNITUDE COMPARATOR
 The basic function of a comparator is to compare the magnitudes of two quantities to
determine the relationship of those quantities.
 The XNOR gate can be used as a basic comparator because its output is a 1 when two
inputs are equal. If the two input bits are not equal it is 0 if the input bits are equal.

One bit magnitude comparator

 Magnitude comparator is to compare the three results: equal to, less than and greater than.
Fig.1.44 shows the logic diagram for 2 bit comparator.

Number of required inputs = 2 (A,B)

Number of required outputs = 3 (A=B, A<B, A>B)

(w, x, y)
 Fig 1.44 Logic diagram for 1 - bit comparator

2 - Bit Magnitude Comparator

 A two bit comparator compares the magnitude of two bits and the logic diagram
design is as follows. It is shown in Fig.1.45.
 Number of required inputs = 4 (A1 B1 A0 B0)
 Number of required outputs = 3 (w, x, y)
 when w is equal magnitude representation A1 A0 = B1 B0
 x is less than magnitude representation A1 A0 < B1 B0
 y is greater magnitude representation A1 A0 > B1B0
Logic diagram

Fig 1.45 Logic diagram for 4-bit magnitude comparator

DECODER

Definition:

 A digital circuit designed to detect the presence of a particular digital state. It is a

combinational logic circuit that converts binary information from n input lines to a
maximum 2n unique output lines. Discrete quantities of information are represented in
digital system by binary codes.
 A binary code of n bits is capable of representing upto 2n distinct elements of coded
information. A decoder is a combinational logic circuit that converts binary information
from n input lines to a maximum of 2n unique output lines.
 If the n-bit code information has unused combinations, the decoder may have fewer than
2n outputs. Fig.1.47 shows the block diagram of decoder.
 Fig 1.47 Block diagram of decoder
2 to 4 Binary decoder
 Fig.1.48 shows the 2 to 4 decoder. Here 2 represent the input lines and 4 represent output
lines.
 The table 1.20 shows the truth table for a 2 to 4 decoder. If Enable is 1, one and only of
the outputs Y0 to Y3 is active for a given input.
 The Y0 is active when inputs AB = 00, the output Y1 is active when the inputs AB = 01,
similarly the outputs Y2 and Y3 are active when the input AB is 10 and 11 respectively.
If Enable is 0 then all the outputs are 0.
 In general, a decoder may operate with complemented (or uncomplemented outputs. The
enable input may be activated with 0 or with a 1 signal. Some decoders have two (or)
more enable inputs that must satisfy a given logic condition in order to enable the circuit.
A decoder with enable input can function as a demultiplexer.
Table 1.20 Truth table for

Fig 1.48 logic diagram for 2 to 4 decoder

3 to 8 Decoder
 In the 3 to 8 decoder circuit, the 3 inputs are decoded into eight outputs represent the
minterms of the 3 input variables.
 The three inverters provide the complement of the inputs and each one of the eight AND
gates generates one of the minterms.
 The inputs are A, B, C. Fig.1.49 shows the logic diagram and the truth table of 3 to 8
decoder is shown in the Table 1.21 for active low output.

Fig 1.49 Logic diagram os 3 to 8 decoder

ENCODER
Definition of Encoder

 A circuit that generates a binary code at its outputs in response to one or more active
input lines An encoder is a combinational logic circuit, it is a reverse decoder function. It
has 2n (or fever) input lines and n output lines.
 In encoder accepts an active 1.80 Digital Logic Circuits level on one of its inputs
representing a digit such as a decimal (on octal digit and comments it to a coded output).
Fig.1.55 shows the block diagram of a encoder.
Octal to Binary Encoder
 In the octal to binary encoder has eight inputs, one for each octal digit and outputs that generates
the corresponding binary code.
 In encoders it is assumed that only one input has a value of 1 at any given time. Table 1.23 shows
the truth table of octal to binary encoder and Fig.1.56 shows the octal to binary encoder circuit.

From truth table out put A having 1 when the inputs 4, 5, 6 and 7 are appear
so that the equations are written as follows.
A = D4+D5+D6+D7
Similarly, the Boolean expressions for output B and C are written as follows
B = D2+D3+D6+D7
C = D1+D3+D5+D7

Fig 1.56 Logic diagram of octal to binary encoder

Decimal to BCD encoder

 This type of encoder has ten inputs - one for each decimal digit and four outputs corresponding to
the BCD code

 Table 1.24 shown the relation between the decimal and BCD code. A3 is most significant
bit of the BCD code. A3 is always 1 for decimal digit 8 or 9. The expression for bit A3
minterms of the decimal digits can written as.
A3 = 8+9

Bit A2 is always 1 for decimal digit 4,5,6 or 7 can be expressed as on OR function as

follows. A2 = 4+5+6+7

Bit A1 is always 1 for decimal digit 2, 3, 6 or 7 and can be expressed as

A1 = 2+3+6+7
Bit A0 is always 1 for decimal digit 1, 3, 5, 7 or 9 the expression for A0 is
A0 = 1+3+5+7+9
Now, we can draw the decimal to BCD encoder by using the above four expression
Fig.1.57 shows the decimal to BCD encoder.

Fig 1.57 Logic diagram for decimal to BCD encoder

  When a HIGH is appears on one of the decimal digit input lines, the appropriate levels
occur on the four BCD output lines.

CODE CONVERTER:
 Code converter is a combinational logic circuit to convert one form of code to another form of
code. Some of these codes are binary coded decimal, Excess -3 code, Gray code and so on. Many
times it is required to convert one code to another.

Binary to BCD Converter

 A code converter combinational circuit is designed to convert binary to BCD code.

Fig.1.60 shows the logic diagram of Binary to BCD code converter.
 The input code of code converter is binary. The output code of code converter is BCD
code.
 Logic Diagram

Fig 1.60 Logic diagram of Binary to BCD code converter

BCD TO EXCESS -3 CODE CONVERTER

 A code converter combinational circuit is designed to convert BCD code to Excess 3
code. The input code of code converter is BCD code.
 The output code of code converter is Excess-3 code. Fig.1.62 shows the logic diagram of
BCD t excess-3 code converter The unused states are 1010, 1011, 1100, 1101, 1110 and
1111. So place X (Don’t Care Condition) for the corresponding cells.
 Logic Diagram

Fig 1.61 Logic diagram of BCD to Excess-3 code converter

EXCESS-3 CODE TO BCD CODE CONVERTER

 A code converter combinational circuit is designed to convert Excess - 3 code to BCD code. The
input code of code converter is Excess - 3. The output code of code converter is BCD code.
Fig.1.61 shows the logic diagram of excess -3 code to BCD code converter.
 The unused states are 0000, 0001, 0010, 1101, 1110 and 1111. So place X (Don’t Care
Condition) for the corresponding above cells.
Logic Diagram

Fig 1.62 Logic diagram of Excess-3 to BCD code converter

BINARY CODE TO GRAY CODE CONVERTER:
 A code converter combinational circuit is designed to convert binary to gray code.
Fig.1.63 shows the logic diagram of binary to gray code converter.
 The input code of code converter is binary and the output code of code converter
is gray code.
  We get the simplified boolean expression for the code convertor of Binary to Gray code.
G0 = B_A+BA_ = B⊕A
G1 =CB_+C_B =C⊕B
G2 = D_C+DC_ =C⊕D
G3 = D
 By using the above expression we can construct the binary to gray code convertor as shown in
Fig.1.63.
Logic diagram

Fig 1.63 Logic diagram of Binary to gray code converter

GRAY CODE TO BINARY CODE CONVERTER:
 A code converter combinational circuit is designed to convert gray code to binary code.
The input code of code converter is gray. The output code of code converter is binary
code. Fig.1.64 shows the logic diagram of gray to binary code converter.
Logic Diagram

Fig 1.64 Logic diagram of Gray code to Binary code converter

MULTIPLEXER:

Definition of Multiplexer
 A circuit that directs one of several digital signals to a single output depending upon the state of
several select inputs. Boolean Algebra and Combinational Circuits 1.95
 Data inputs The multiplexer inputs that feed a digital signal to the output when selected.
(Maximum of inputs is 2n)
 Select inputs The multiplexer inputs that selects the digital input (Maximum “n” select lines).
 Fig 1.65 Block diagram of Multiplexer

 ‘Multiplex’ means many to one. Multiplexing is the process of transmitting a

large number of information over a single line. A digital multiplexer (MUX) is a
combinational logic circuit that selected information on a single output.
 A multiplexer is also called a data selector. Fig.1.65 shows the block diagram of
multiplexer. Normally, there are 2n input lines and n selection lines and one
output line. The selection of a particular input line is controlled by the set of select
lines. The size of the multiplexer is specified by number 2n input lines and the
single output line.

4 to 1 Multiplexer
 The 4 to 1 multiplexer, the 4 represent the number of inputs and one represent the
output line. The two select lines (2n = 4;n = 2) S1 and S0 to select one of the four
inputs. Table 1.31 shows the truth table of 4 to 1 multiplexer.
 From the truth table, the logical expression for the output in term of data input (I0,
I1, I2, I3) and select lines can be derived as follows and Fig.1.66 shows the logic
diagram of 4 : 1 MUX.
Logic Diagram
PLA (PROGRAMMABLE LOGIC ARRAY):
 In PLAs, instead of using a decoder as in PROMs, a number (k) of AND gates is used
n
where k < 2 , (n is the number of inputs).
 Each of the AND gates can be programmed to generate a product term of the input
variables and does not generate all the minterms as in the ROM.
 The AND and OR gates inside the PLA are initially fabricated with the links (fuses)
among them. The specific Boolean functions are implemented in sum of products form
by opening appropriate links and leaving the desired connections.
 A block diagram of the PLA is shown in the figure. It consists of n inputs, m outputs, and
k product terms.

The product terms constitute a group of k AND gates each of 2n inputs.

 Links are inserted between all n inputs and their complement values to each of the AND
gates. Links are also provided between the outputs of the AND gates and the inputs of the
OR gates.
 Since PLA has m-outputs, the number of OR gates is m.
 The output of each OR gate goes to an XOR gate, where the other input has two sets of
links, one connected to logic 0 and other to logic 1. It allows the output function to be
generated either in the true form or in the complement form.
/
 The output is inverted when the XOR input is connected to 1 (since X ⊕ 1 = X ).
 The output does not change when the XOR input is connected to 0 (since X ⊕ 0 = X).
 Thus, the total number of programmable links is 2n x k + k x m + 2m.
 The size of the PLA is specified by the number of inputs (n), the number of product terms
(k), and the number of outputs (m), (the number of sum terms is equal to the number of
outputs).

Example:
 Implement the combinational circuit having the shown truth table, using PLA.
  Each product term in the expression requires an AND gate. To minimize the cost, it is
necessary to simplify the function to a minimum number of product terms.

The combination that gives a minimum number of product terms is:

’
F1 = AB + AC + BC or F1 = (AB + AC + BC)’
F2 = AB + AC + A’B’C’
This gives only 4 distinct product terms: AB, AC, BC, and A’B’C’.
PAL (PROGRAMMABLE ARRAY LOGIC):
 The PAL device is a PLD with a fixed OR array and a programmable AND array.
 As only AND gates are programmable, the PAL device is easier to program but it is not
as flexible as the PLA.

 The device shown in the figure has 4 inputs and 4 outputs. Each input has a buffer-
inverter gate, and each output is generated by a fixed OR gate.
 The device has 4 sections, each composed of a 3-wide AND-OR array, meaning that
there are 3 programmable AND gates in each section.
 Each AND gate has 10 programmable input connections indicating by 10 vertical lines
intersecting each horizontal line. The horizontal line symbolizes the multiple input
configuration of an AND gate.
 One of the outputs F1 is connected to a buffer-inverter gate and is fed back into the inputs
of the AND gates through programmed connections.

Example:
Implement the following Boolean functions using the PAL device as shown above:

W(A, B, C, D) = Σm(2, 12, 13)

X(A, B, C, D) = Σm(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y(A, B, C, D) = Σm(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z(A, B, C, D) = Σm(1, 2, 8, 12, 13)
Simplifying the 4 functions to a minimum number of terms results in the following Boolean
functions:
W = ABC’ + A’B’CD’
X = A + BCD
Y = A’B + CD + B’D’
Z = ABC’ + A’B’CD + AC’D’ + A’B’C’D =W +AC’D’ + A’B’C’D