UNIT-5

BIASING AND STABILIZATION

Need for Biasing:

 In order to produce distortion free output in amplifier circuits, the supply voltages and
resistances in the circuit must be suitably chosen.
 The voltages and resistances establish a set of DC voltage V ceq and current Icq to
operate the transistor in the active region. These voltage and current values determine
the operating point or Q point for the transistor.
 The process of giving proper supply voltages and resistances for obtaining the desired
Q point is called Biasing.
 The circuits used for getting the desired and proper operating point are known as
biasing circuits.

Transistor biasing:

The process of giving proper supply voltages and resistances for obtaining the desired
zero original collector current and collector to emitter voltage is called biasing. The circuits
used for getting the desired zero signal collector current and collector to emitter voltage are
known as biasing circuits.

Dc Load Line:

Apply KVL to the collector emitter circuit in the following figure.

V cc = I c Rc + V ce In cut off region, I c = 0 ∴ V ce =V cc

In saturation region,V ce = 0 ∴ I c = V cc / Rc

These two points are indicated in the following graph namely A and B. The line joining these
two points is called dc load line.

Zero signal Collector to Emitter voltage and collector current are the operating point
or quiescent point or simply Q point.

In order to get faithful amplification, the operating point must be located at the Centre
between cutoff point and saturation point. The operating point is shifted then output voltage
and current get clipped. Thereby output signal is distorted.

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Stability Factor(S):

The stability factor (S) may be defined as the rate of charge of collector current with
respect to reverse saturation collector current keeping β and V BE constant.

∂ Ic
∴S= when β∧V BE = constant
∂ I co

According to the above expression, smaller is the value of S higher is the stability. So, the
stability should be kept as small as possible. The lowest value of S is unity. S close to unity
then lesser will be the variation of operating point with temperature.

Expression for Stability Factor:

The collector current in CE configuration is given by

I c = (1+ β ) I co + β I B

Differentiating the above Equation w.r.t I c

∂ I co ∂IB
1 = (1+ β ) +β
∂ Ic ∂Ic

1+ β ∂IB
1= +β
S ∂Ic

1+ β ∂IB
=1-β
S ∂Ic

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 1+ β
∴ S= ∂IB
1−β ( )
∂Ic

Stability Factor S’ or Sr:

The stability factor S’ may be defined as the ratio of change of collector current with respect
to V BE keeping I co and β constant.

∂Ic
∴ Stability Factor = S’ = Sr = I co, β = constant
∂ V BE

Stability Factor S’’ or S β:

Stability Factor S’’ may be defined as the ratio of change of collector current with respect to
β keeping I co and V BE constant.

∂Ic
∴ Stability Factor = S’’ = S β = I co, V BE= constant
∂β

Expression for Stability Factor S’’ Or S β:

The collector current in CE configuration is given by

I c = (1+ β ) I co + β I B

Differentiating the above Equation w.r.t I c keeping I co, constant

∂β ∂β ∂β
1 = I co +β + IB
∂Ic ∂Ic ∂Ic

∂β ∂β
1 = ( I co+ I B ) +β
∂Ic ∂Ic

∂β I +I
1-β = co B
∂Ic S''

I co + I B
∴ S’’ = S β = ∂β
1−β [ ]
∂ Ic

Different Methods for Transistor Biasing:

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The following methods are generally used for transistor biasing

1) Fixed bias.

2) Collector to base bias.

3) Self bias or emitter bias or potential divider bias.

1) Fixed bias:

The following figure shows an NPN transistor in CE configuration with fixed bias. In this
method, a resistance RB is connected between positive terminal of the supply V CC and base of
the transistor.

Applying KVL to the base emitter loop

V CC = I B R B + V BE

∂IB ∂I
0= R B + 0 → B =0
∂Ic ∂Ic

1+ β
But stability factor = s = ∂ I B = (1+ β )
1−β ( )
∂Ic

∴S=1+β

This shows that the change of I C w.r.t I Co is very high. Hence the circuit has very poor
stability. Due to this reason, this method is generally not preferable.

2 Collector to base bias:

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 The following figure shows an NPN transistor in CE configuration with collector to
base bias. In this method, a resistance R B is connected between collector and base of a
transistor.

Applying KVL to the base emitter loop.

V CC = ( I B+ I C ) RC + I B RB + V BE

V CC - V BE = I B( R B + RC ) + I C RC

Differentiating the above equation w.r.t I C

∂IB
0= ( R B + RC ) + RC
∂Ic

∂IB −RC
=
∂ I c R B + RC

1+ β
But stability factor = S = ∂I
1−β ( B )
∂Ic

1+ β
∴S= RC
1+ β( )
R B + RC

This value is smaller than (1 + β ) which is obtained for timed bias circuit. Thus there
is an improvement in the stability of Rc is very small than s = 1 + β (i.e) stability is very poor.
Hence, the value of Rc must be quite large for good stabilization.

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3 Self bias or emitter bias or potential divider bias:

A very commonly used biasing arrangement is self-bias. The circuit arrangement is shown
below. In this method, two resistances R1 and R2 are connected across the supply voltage V cc
for providing biasing.

Of I c tends to increase due to increase in I co with temp., the current in R E increases. Hence
the voltage drop across R E increases thereby decreasing the base current. As a result, I cis
maintained almost constant,

Applying thevenin’s theorem to the following circuit diagram.

R2 R1 R2
V th = V CC ( ) and Rth= R B =
R 1+ R 2 R 1+ R 2

Applying kVL to the base emitter loop of thevenin’s equivalent circuit.

V th = I B RB + V BE + I E R E

V th = I B( R B + R E ) + I E R E + V BE

Differentiating the above equation w.r.t I c

∂IB
0= (R B + R E ) + R E + 0
∂Ic

∂IB RE
=
∂ I c RB+ RE

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 1+ β
But stability factor = s = ∂IB
1−β ( )
∂Ic

1+ β
∴S= RE
1+ β( )
RB+ RE

RB
1+ β ( 1+ β )(1+ )
RE
s= RE R +R =
+[ β+ B E ] RB
RB+ RE RE 1+ β +
RE

RB
If is very small thus S =1 which is best for S
RE

Stability Factor (S’’ or S β ) for self bias:

I B + I CO
We know that S’’ = ∂IB
1−β ( )
∂Ic

For self biased circuit,

V th = I B RB + V BE + I E R E

V th - V BE = I B( R B + R E ) + I C R E

∂IB
0= (R B + R E ) + R E
∂Ic

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∂IB −R E
=
∂ I c RB+ RE

I B + I CO
∴S’’ = RE but I B ≫ I CO
1+ β( )
RB+ RE

1+ β
But Stability factor = S = RE
1+ β( )
RB+ RE

IB
∴ S’’ = RE
1+ β( )
RB+ RE

IB
∴ S’’ =
(1+ β )/S

SI B IC
∴ S’’ = but =β
(1+ β ) IB

SI C
∴ S’’ =
β(1+ β)

Bias compensation techniques:

Compensation techniques are used to reduce the change of the operating point.
Sometimes both stabilization as well as compensation techniques are used. Following
techniques are used for compensation.

 Diode compensation technique

 Thermistor compensation technique
 Sensistor compensation technique

Diode compensation technique:

The following circuit diagram represents an NPN transistor in CE configuration with

diode D used for compensation of variation in I co. The diode D and transistor are of the same
material.

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IB = I - Io

We know that I C = (1 + β ) I CO + β I B

I C = (1 + β ) I CO + β ( I - I o)

I C = β I CO + β I - β I o ∵ β is very high value.

∴ I C = β (I ¿ ¿ CO−I o)¿ + β I

According to the above equation, whenever temperature increases, then I o and I co

both are increased proportionately. Resultant I c remains constant.

Thermistor compensation technique:

The following circuit diagram shows a self-biased circuit with thermistor RT . A thermistor RT
having negative temperature coefficient is connected in parallel with R2. The resistance of
thermistor decreases with increase in temperature. As the temperature increases, more current
flows through the thermistor. Resultant I B decreases and I c also decreases. Thus thermistor
acts as to compensate the increase in I c due to temp. Thus the collector current remains
constant.

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Circuit shows thermistor compensation in a self – bias CE amplifier. Thermistor RT has
negative temperature coefficient. Negative temperature coefficient means resistance
decreases exponentially with increase in temperature T. Thermistor RT is used to minimize
the increase in collector current due to variations in I CO, V BEor β with temperature if the
temperature increases. Thermistor resistance decreases. Current flowing through R T
increases. Since the voltage drop across RE increases in the direction, it reverse biases the
transistor Base –Emitter junction which reduces I B and keeping IC constant. Thus RT
compensates the increase in I C . Thus the temperature sensitivity of R T provides compensation
to the increase in collector current I C due to rise in temperature T. The same result is obtained
if the transistor RT is placed in the base circuit across R2 instead of in collector circuit.

Sensistor Compensation:

Working of the Circuit

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Instead of thermistor compensation, compensation can be done by using sensistor. Sensistor
is a temperature sensitive device. Sensistor has positive temperature coefficient. The sensistor
may be placed either in parallel with R 1or in parallel with RE . The sensistor can also be
placed in place of RE rather than in parallel with R E With the increase in temperature. The
resistance of RS increases. So, the resistance of parallel combination (R S|| R1) increases.
Hence voltage drop across R2decreases. Decrease in VR2decreases the net forward emitter
Bias (VBE). Hence Collector current I C decreases. Decrease in IC compensates the increase in
collector current IC due to increase in IC0, β and VBE because of rise in temperature.

Thermal Runaway:
I C =¿ β I B + (1+ β ) I CO

As temperature increases more number of covalent bonds will break. As more number of
covalent bonds will break more number of minority carriers increases. Whenever minority
carriers are increases at that time reverse saturation current increases because reverse
saturation is only depends on minority carriers, so that I CO increases from that one we can say
I C increases. So collector current of BJT increases as temperature increases because reverse
saturation current and that is going to multiply by (1+ β ) times and that will be increase cause
in I C.

Thermal runway is nothing but process of increase. It is going to be cumulative process

within fraction of time the BJT gets damaged so this is going to be called as thermal runway.
Thermal Runway is a self destruction of transistor as temp increases.

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Thermal Runaway in a Transistor
In a semiconductor device, the reverse saturation current changes with the change in
temperature. Moreover, the reverse saturation current doubles for every 10°C rise in
temperature. This may cause considerable practical difficulty in using transistor as an
amplifier. It is because of the fact that if the temperature of the collector-base junction
increases, the leakage current of the transistor also increases and as a result the collector
current increases. This increase in Collector current produces an increase in the power
dissipation at the collector-base junction. This in turn further increases the temperature of the
collector-base junction causing the collector current to further increase. The process may be
cumulative and it is possible that the ratings of the transistor may be exceeded. If it happens,
the device gets burned out. This process is described as Thermal Runaway in a Transistor. In
actual practice, a thermal runaway is avoided by using a stabilization circuit or a heat sink
with the transistor.
Thermal resistance is a heat property and a measurement of a temperature difference by
which an object or material resists a heat flow. Thermal resistance is the reciprocal of thermal
conductance.

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1) Stability factor‘s’ in fixed bias CE amplifier is given by [B]
a) β b) β+1 c) 1/ β+1 d) 1/ β
2) Which transistor bias circuit arrangement has poor stability [C]
A) collector-feedback bias B) voltage-divider bias C) fixed bias D) emitter bias
3) The quiescent point of a transistor biasing circuit implies [C]
a) Zero bias b) No output c) No distortion d) No input signal
4) At saturation, the value of VCE is nearly ________, and IC = ________. [C]
A) Zero, Zero B) VCC, IC (sat) C) zero, I (sat) D) VCC, zero
5) Changes in results in changes in [D]
A) IC B) VCE C) the Q-point D) all of the above
6) Three difference Q points are shown on a load line. The upper Q point represents the [C]
A) Minimum current gain. B) Intermediate current gain.
C) Maximum current gain. D) Cutoff point.
7) If a transistor operates at the middle of the load line, a decrease in the base resistance will
move the Q point [B]
A) Down. B) Up. C) Nowhere. D) Off the load line.
8) If a transistor operates at the middle of the load line, a decrease in the current gain will
move the Q point [A]
A) Down. B) Up. C) Nowhere. D) Off the load line.
9) If the base supply voltage increase, the Q point moves [B]
A) Down. B) Up. C) Nowhere. D) Off the load line.
10) Suppose the base resistor is open. The Q point will be [C]
A) In the middle of the load line. B) At the upper end of the load line.
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C) At the lower end of the load line. D) Off the load line.
11) When the Q point moves along the load line, VCE decreases when the collector current [C]
A) Decreases. B) Stays the same. C) Increases. D) Does none of the above.
12) When there is no base current in a transistor switch, the output voltage from the transistor
is [B]
A) Low. B) High. C) Unchanged. D) unknown.
13) If the emitter resistance decreases, the [A]
A) Q point moves up. B) Collector current decreases.
C) Q point stays where it is. D) Current gain increases.

14) With voltage - divider bias, the base voltage is [A]

A) less than the base supply voltage. B) Equal to the base supply voltage.
C) greater than the base supply voltage. D) greater than the collector supply voltage.
15) Which is the largest current in a PNP transistor? [B]
A) Base current. B) Emitter current. C) Collector current. D) None of these.
16) The currents of a PNP transistor are [B]
A) Usually smaller than NPN currents. B) Opposite NPN currents.
C) Usually larger than NPN currents. D) Negative.

17) The condition to prevent thermal runaway is given by ______________. ( )

18) Stability factor ‘S’ is approximately unity for __________ bias. (SELF)

19) For normal amplification, the Q point should be established in the _______region.
(Active)

20) The straight line through the quiescent operating point having slope corresponding to the
ac load resistance is _________________ (load line)

21) Expression for‘s’ for self bias circuit is _____________ ( )

22) Stability factor for fixed bias is _________ if β =40. (41)

23) Ideally, stability factor should be ____________ to keep operating point stable. (Zero)

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24) The excess heat produced at the collector base junction due to self heating may even burn
and destroy the transistor. This is called ______________________ of the transistor.
(Thermal Runaway)

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