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PLC 1

The document provides an introduction to Programmable Logic Controllers (PLCs), detailing their architecture, including the Central Processing Unit (CPU), input/output systems, and programming devices. It explains the programming process using ladder logic diagrams and outlines various experiments to study digital input/output operations, timer functions, and counter operations using PLCs. Each experiment includes aims, required apparatus, procedures, and post-experimental tasks for practical understanding of PLC functionalities.

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Nidhin Scaria
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0% found this document useful (0 votes)
33 views10 pages

PLC 1

The document provides an introduction to Programmable Logic Controllers (PLCs), detailing their architecture, including the Central Processing Unit (CPU), input/output systems, and programming devices. It explains the programming process using ladder logic diagrams and outlines various experiments to study digital input/output operations, timer functions, and counter operations using PLCs. Each experiment includes aims, required apparatus, procedures, and post-experimental tasks for practical understanding of PLC functionalities.

Uploaded by

Nidhin Scaria
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment No:

PROGRAMMABLE LOGIC CONTROLLER

BASIC INTRODUCTION TO PLC

Programmable logic controllers (PLC's) are nothing but a type of solid state devices
designed to perform logic functions previously accomplished by electromechanical relays mainly
used in industrial equipments. These industrial equipments may range from a small ON-OFF
switch to a heavy machine. Any component in an industry that needs a control can be controlled
by using a PLC. The main advantage of using a PLC is that long and tedious programming can
be eliminated. These PLC's differ not only on the basis of programming but also it has the
advantage of being available in portable sizes and series. The programming for the PLC is done
by using a ladder logic diagram. The ladder logic diagram consists of blocks which are in the
form of ladders.

ARCHITECTURE OF A PLC
The PLC is mainly divided into 3 parts namely the Central Processing Unit (CPU), the input /
Output (I/O) selection and the programming device. A block diagram representing all this is
shown below.

CPU accepts (reads) input data from various sensing devices, executes the stored user program
from memory, and sends appropriate output command to control devices. The I/O system forms
the interface by which field devices are connected to the controller. The purpose of this interface
is to condition the various signals received from or sent to external field devices. The
programming device, or terminal, is used to enter the desired program into the memory of the
processor.
This program is entered using relay ladder logic. The program determines the sequence of
operation and ultimate control of equipment or machinery.
CENTRAL PROCESS UNIT (CPU)
In small PLCs, the processor, solid state memory, I/O modules, and power supply are housed in a
single compact unit. The programming device, usually a handled unit with a keypad and LCD
display, is separate but tethered to the main unit with a cable.

In larger PLCs, the processor and memory are in one unit, the power supply is a second unit, and
the I/O interface (modules) in additional units. The programming device, which may be a
personal computer (PC), is, of course, a separate, the thread item.
THE PROCESSOR
The microprocessor is part of the PLC CPU that receives, analyses, processes, and sends data.
The data, in digital pulse form, is sent and received as shown in figure.
A ROM with the fixed operating system program interfaces to the control section. This fixed
program manages the operating of the PLC. The control section contains a control unit with a
clock, arithmetic / logic unit (ALU) and a few temporary registers. Input scan block, when called
upon to operate, scans the inputs and places the individual input status in RAM. After analysis,
the logic scan program updates the output scan block to the appropriate state.
PROCESSOR MEMORY ORGANISATION
The processor memory space can be divided into two broad categories: The user program and the
data table. The user program is where the programmed logic ladder diagram is entered and
stored. The user program will account for most of the total memory of a given PLC system. It
contains the logic that controls the machine operation. This logic consists of instructions that are
programmed in a ladder logic format. Most instructions require are word memory. The data table
stores the information needed to carry out the user program. This includes such information as
the status of input and output devices, timer and counter values, data storage etc. Contents of
data table can be divided into two categories: Status data and numbers or codes. During each
operating cycle, the processor reads all the input, takes these values, and accordingly to the user
program energizes or de-energizes the outputs. This process is known as scan. The PLC scan
time specification indicates how fast the controller can react to changes in input. Scan time varies
with program content and length. The time require to make a single scan may vary from '1' to
100ms.
PLC PROGRAMMING
The two most common language structures are ladder diagram language and Boolean language.
Here we will be using only the ladder diagram language. The ladder diagram language is
basically a symbolic set of instruction used to create the controller program. These ladder
instructions are arranged to obtain the desired control logic that is to be entered into the memory
of the PLC. The main symbols that are used in a PLC programming are as shown below:
The main function of the logic ladder diagram is to control outputs based on input conditions.
This control is accomplished through the use of what is referred to as a ladder rung. For an
output to be activated or energized at least one left-to right path of the contact must be closed. A
complete closed path is referred to as having logic continuity. When logic continuity exists in at
least one path, the rung condition is said to be true. The rung condition is false if no path has
continuity.
10. a) FAMILIARISATION OF DIGITAL APPLICATIONS
USING PLC

EXPERIMENT 1

AIM
To study the Digital Input/Output operation of PLC.

APPARATUS REQUIRED

1. PLC Kit.
2. PC with PLC software.
3. RS 232 Cable.
4. Patch Chords.
5. Power Chord.

PROCEDURE
1. For creating this program follow PLC Software Working Procedure
2. Switch on the personal computer and the PLC trainer kit.
3. Digital input and output can be checked by using logical gates such as AND, OR, NAND,
NOR, Ex-NOR, Ex-OR and NOT gates.
4. For example: If we need create AND gate, place two input contacts in series and one output
contact in series. The Input address is given by %I00001 to %I00002.
5. The Output address is given by %Q00001.

POST EXPERIMENTAL WORK


1. Draw the ladder diagram for the different logic gates
CONNECTION DIAGRAM

RESULT
EXPERIMENT 2

AIM

To study the On delay and Off delay Timer operation using PLC.

APPARATUS REQUIRED
1. PLC Kit.
2. PC with PLC software.
3. RS 232 Cable.
4. Patch Chords.
5. Power Chord.

PROCEDURE
For On Delay Timer
1. For creating this program follow the PLC Software Working Procedure
2. Create the program is shown below in the fig.
3. In all function block select ONDTR HUNDS and give the address as %I00001 at Input and
%Q00001 at Output,%I00002 at Reset (R),Time delay is given at PV.
4. Click the timer block in programming window and give address as %R0010.
5. After storing the program into PLC run the program.
6. Switch on the first input after the completion of time delay the output will be ON.
7. To reset the Timer turn on the second input.
For Off Delay Timer
1. For creating this program follow the PLC SoftwareWorking Procedure
2. Create the program is shown below in the fig.
3. In all function block select OFDT HUNDS and give the address as %I00001
at Input and %Q00002 at Output, Time delay is given at PV.
4. Click the timer block in programming window and give address as %R0020.
5. After storing the program into PLC run the program.
6. Switch on the First input, then the output will be in ON Condition.
7. If we switched OFF the Input at that time the Timer starts counting after reaching the time
delay the Output goes to OFF condition.

POST EXPERIMENTAL WORK


1. Draw the ladder diagram for the on delay timer and off delay timer and explain how it is
working
CONNECTION DIAGRAM

RESULT
EXPERIMENT 3

AIM
To study the UP and DOWN Counter operation using PLC.

APPARATUS REQUIRED
1. PLC Kit.
2. PC with PLC software.
3. RS 232 Cable.
4. Patch Chords.
5. Power Chord.

PROCEDURE
For Up Counter
1. For creating this program follow the PLC Software Working Procedure.
2. Create the program is shown below in the fig.
3. In all function block select UPCTR and give the address as %I00001 at Input and %Q00001 at
Output,%I00002 at Reset (R),Count value is given at PV.
4. Click the Counter block in programming window and give address as %R0010.
5. Switch ON and OFF the Input for five times then the Output will be ON.
6. To reset the counter turn on the second input.
For Down Counter
1. For creating this program follow the PLC Software Working Procedure.
2. Create the program is shown below in the fig.
3. In all function block select DNCTR and give the address as %I00001 at Input and %Q00002 at
Output,%I00002 at Reset (R),Count value is given at PV.
4. Click the Counter block in programming window and give address as %R0010.
5. Initially Switch ON the Input %I00002 and then the counter value PV assigned to the counter
and then Turn OFF the Input %I00002.
6. At that time the Output get Turned ON.
7. Switch ON and OFF the Input for five times then the Output goes to OFF condition.

POST EXPERIMENTAL WORK


1. With the help of ladder diagram explain the counter operation
CONNECTION DIAGRAM

RESULT

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