1

Introduction
What is a Microprocessor?

Computer's Central Processing Unit (CPU) built on a single Integrated Circuit (IC) is called
a microprocessor.

microprocessor is a programmable, multipurpose, clock -driven, register-based electronic

device that reads binary instructions from a storage device called memory, accepts binary
data as input and processes data according to those instructions and provides results as
output.

The microprocessor contains millions of tiny components like transistors, registers, and
diodes that work together.
Evolution of Microprocessors
We can categorize the microprocessor according to the generations or according to the size of
the microprocessor:
First Generation (4 - bit Microprocessors)

The first-generation microprocessors were introduced in the year 1971-1972 by Intel

Corporation. It was named Intel 4004 since it was a 4-bit processor.

It was a processor on a single chip. It could perform simple arithmetic and logical operations
such as addition, subtraction, Boolean OR and Boolean AND.

I had a control unit capable of performing control functions like fetching an instruction from
storage memory, decoding it, and then generating control pulses to execute it.
Second Generation (8 - bit Microprocessor)

The second-generation microprocessors were introduced in 1973 again by Intel. It was a first
8 - bit microprocessor which could perform arithmetic and logic operations on 8-bit words. It
was Intel 8008, and another improved version was Intel 8088.
Third Generation (16 - bit Microprocessor)

The third-generation microprocessors, introduced in 1978 were represented by Intel's 8086,

Zilog Z800 and 80286, which were 16 - bit processors with a performance like
minicomputers.
Fourth Generation (32 - bit Microprocessors)
Several different companies introduced the 32-bit microprocessors, but the most popular one
is the Intel 80386.
Fifth Generation (64 - bit Microprocessors)

From 1995 to now we are in the fifth generation. After 80856, Intel came out with a new
processor namely Pentium processor followed by Pentium Pro CPU, which allows multiple
CPUs in a single system to achieve multiprocessing.

Other improved 64-bit processors are Celeron, Dual, Quad, Octa Core processors.
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Table: Important Intel Microprocessors

Microprocessor Year of Word Memory Pins Clock Remarks

Invention Length addressing
Capacity

4004 1971 4-bit 1 KB 16 750 KHz First Microprocessor

8085 1976 8-bit 64 KB 40 3-6 MHz Popular8-bit

Microprocessor

8086 1978 16-bit 1MB 40 5-8 MHz Widely used in PC/XT

80286 1982 16-bit 16MB real, 4 GB 68 6-12.5 Widely used in PC/AT

virtual MHz

80386 1985 32-bit 4GB real, 64TB 132 20-33 Contains MMU on chip
virtual 14X14 MHz
PGA

80486 1989 32-bit 4GB real, 64TB 168 25-100 Contains MMU, cache and
virtual 17X17 MHz FPU, 1.2 million transistors
PGA

Pentium 1993 32-bit 4GB real,32-bit 237 60-200 Contains 2 ALUs,2 Caches,
address,64-bit PGA FPU, 3.3 Million
data bus transistors, 3.3 V, 7.5
million transistors

Pentium Pro 1995 32-bit 64GB real, 36-bit 387 150-200 It is a data flow processor.
address bus PGA MHz It contains second level
cache also,3.3 V

Pentium II 1997 32-bit - - 233-400 All features Pentium pro

MHz plus MMX technology,3.3
V, 7.5 million transistors

Pentium III 1999 32-bit 64GB 370 600-1.3 Improved version of

PGA MHz Pentium II; 70 new SIMD
instructions

Pentium 4 2000 32-bit 64GB 423 600-1.3 Improved version of

PGA GHz Pentium III

Itanium 2001 64-bit 64 address lines 423 733 64-bit EPIC Processor
PGA MHz-1.3
GHz
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Where,

o PGA - Pin Grid Array

o MMX – MultiMedia eXtensions
o EPIC - Explicitly Parallel Instruction Computing
o SIMD - Single Instruction Multiple Data
o ALU - Arithmetic and Logic Unit
o MMU - Memory Management Unit
o FPU - Floating Point Unit

Basic Terms used in Microprocessor

Here is a list of some basic terms used in microprocessor:

Instruction Set - The group of commands that the microprocessor can understand is called
Instruction set. It is an interface between hardware and software.

Bus - Set of conductors intended to transmit data, address or control information to different
elements in a microprocessor. A microprocessor will have three types of buses, i.e., data bus,
address bus, and control bus.

IPC (Instructions Per Cycle) - It is a measure of how many instructions a CPU is capable of
executing in a single clock.

Clock Speed - It is the number of operations per second the processor can perform. It can be
expressed in megahertz (MHz) or gigahertz (GHz). It is also called the Clock Rate.

Bandwidth - The number of bits processed in a single instruction is called Bandwidth.

Word Length - The number of bits the processor can process at a time is called the word
length of the processor. 8-bit Microprocessor may process 8 -bit data at a time. The range of
word length is from 4 bits to 64 bits depending upon the type of the microcomputer.

Data Types - The microprocessor supports multiple data type formats like binary, ASCII,
signed and unsigned numbers.
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Unit-I
Block Diagram of a Microcomputer
Block Diagram Representation of Microprocessor based system:
A microprocessor is a programmable electronics chip that has computing and decision-making
capabilities similar to central processing unit of a computer.
Any microprocessor-based systems having limited number of resources are called microcomputers.
Nowadays, microprocessor can be seen in almost all types of electronics devices like mobile phones,
printers, washing machines etc. Microprocessors are also used in advanced applications like radars,
satellites and flights. Due to the rapid advancements in electronic industry and large scale ntegration
of devices results in a significant cost reduction and increase application of microprocessors and their
derivatives.

 Bit: A bit is a single binary digit.

• Word: A word refers to the basic data size or bit size that can be processed by the arithmetic and
logic unit of the processor. A 16-bit binary number is called a word in a 16-bit processor.
• Bus: A bus is a group of wires/lines that carry similar information.
• System Bus: The system bus is a group of wires/lines used for communication between the
microprocessor and peripherals.
• Memory Word: The number of bits that can be stored in a register or memory element is called a
memory word.
• Address Bus: It carries the address, which is a unique binary pattern used to identify a memory
location or an I/O port. For example, an eight-bit address bus has eight lines and thus it can address
28 = 256 different locations. The locations in hexadecimal format can be written as 00H – FFH.
• Data Bus: The data bus is used to transfer data between memory and processor or between I/O
device and processor. For example, an 8-bit processor will generally have an 8-bit data bus and a
16-bit processor will have 16-bit data bus.
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 Control Bus: The control bus carry control signals, which consists of signals for selection of
memory or I/O device from the given address, direction of data transfer and synchronization of data
transfer in case of slow devices.
A typical microprocessor consists of arithmetic and logic unit (ALU) in association with control unit
to process the instruction execution. Almost all the microprocessors are based on the principle of store
program concept.
In store-program concept, programs or instructions are sequentially stored in the memory locations
that are to be executed. To do any task using a microprocessor, it is to be programmed by the user. So,
theprogrammer must have idea about its internal resources, features and supported instructions.
Eachmicroprocessor has a set of instructions, a list which is provided by the microprocessor
manufacturer.
The instruction set of a microprocessor is provided in two forms: binary machine code and
mnemonics.
Microprocessor communicates and operates in binary numbers 0 and 1. The set of instructions in the
formof binary patterns is called a machine language and it is difficult for us to understand. Therefore,
the binarypatterns are given abbreviated names, called mnemonics, which forms the assembly
language. Theconversion of assembly-level language into binary machine-level language is done by
using an applicationcalled assembler.

Introduction to 8086 Microprocessor

8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by
Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that
provides up to 1MB storage. It consists of powerful instruction set, which provides operations
like multiplication and division easily.

It supports two modes of operation, i.e., Maximum mode and Minimum mode. Maximum
mode is suitable for system having multiple processors and Minimum mode is suitable for
system having a single processor.

Features of 8086
The most prominent features of an 8086 microprocessor are as follows −

 It has an instruction queue, which is capable of storing six instruction bytes from the
memory resulting in faster processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus,
and 16-bit external data bus resulting in faster processing.
 It is available in 3 versions based on the frequency of operation −
 8086 → 5MHz
 8086-2 → 8MHz
 (c)8086-1 → 10 MHz
 It uses two stages of pipelining, i.e. fetch Stage and Execute Stage, which improves
performance.
 Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
 Execute stage executes these instructions.
 It has 256 vectored interrupts.
 It consists of 29,000 transistors.
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Architecture of 8086

A Microprocessor is an Integrated Circuit with all the functions of a CPU however, it

cannot be used standalone since unlike a microcontroller it has no memory or peripherals.
8086 does not have a RAM or ROM inside it. However, it has internal registers for storing
intermediate and final results and interfaces with memory located outside it through the
System Bus. In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline
Packaged IC. The size of the internal registers (present within the chip) indicate how much
information the processor can operate on at a time (in this case 16-bit registers) and how it
moves data around internally within the chip, sometimes also referred to as the internal data
bus. 8086 provides the programmer with 14 internal registers, each 16 bits or 2 Bytes wide.
Memory segmentation:
 To increase execution speed and fetching speed, 8086 segments the memory.
 It’s 20-bit address bus can address 1MB of memory, it segments it into 16 64kB
segments.
 8086 works only with four 64KB segments within the whole 1MB memory.

The internal architecture of Intel 8086 is divided into 2 units:

 The Bus Interface Unit (BIU), and
 The Execution Unit (EU).

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It
performs various machine cycles such as memory read, I/O read etc. to transfer data between
memory and I/O devices.
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BIU performs the following functions-

It generates the 20 bit physical address for memory access.
It fetches instructions from the memory.
It transfers data to and from the memory and I/O.
Maintains the 6 byte prefetch instruction queue (supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue and an
Address Generation Circuit.
Instruction Pointer (IP):
It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
IP is incremented after every instruction byte is fetched.
IP gets a new value whenever a branch instruction occurs.
CS is multiplied by 10H to give the 20 bit physical address of the Code Segment.
Address of the next instruction is calculated as CS x 10H + IP.
example:
CS = 4321H IP = 1000H
then CS x 10H = 43210H + offset = 44210H
This is the address of the instruction.
Code Segment register:
CS holds the base address for the Code Segment. All programs are stored in the Code
Segment and accessed via the IP.
Data Segment register:
DS holds the base address for the Data Segment.
Stack Segment register:
SS holds the base address for the Stack Segment.
Extra Segment register:
ES holds the base address for the Extra Segment.
Address Generation Circuit:
The BIU has a Physical Address Generation Circuit.
It generates the 20-bit physical address using Segment and Offset addresses using the
formula:
Physical Address = Segment Address x 10H + Offset Address
6 Byte Pre-fetch Queue:
It is a 6 byte queue (FIFO).
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Fetching the next instruction (by BIU from CS) while executing the current instruction is
called pipelining.
2. The Execution Unit (EU):
The main components of the EU are General purpose registers, the ALU, Special purpose
registers, Instruction Register and Instruction Decoder and the Flag/Status Register.
Fetches instructions from the Queue in BIU, decodes and executes arithmetic and logic
operations using the ALU.
Sends control signals for internal data transfer operations within the microprocessor.
Sends request signals to the BIU to access the external module.
It operates with respect to T-states (clock cycles) and not machine cycles.
8086 has four 16-bit general purpose registers AX, BX, CX and DX. Store intermediate
values during execution. Each of these have two 8-bit parts (higher and lower).
AX register:
It holds operands and results during multiplication and division operations. Also an
accumulator during String operations.
BX register:
It holds the memory address (offset address) in indirect addressing modes.
CX register:
It holds count for instructions like loop, rotate, shift and string operations.
DX register:
It is used with AX to hold 32-bit values during multiplication and division.
Arithmetic Logic Unit (16 bit):
Performs 8 and 16 bit arithmetic and logic operations.
Special purpose registers (16-bit):
Stack Pointer:
Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP,
CALL, RET etc.
Base Pointer:
BP can hold offset address of any location in the stack segment. It is used to access random
locations of the stack.
Source Index:
It holds offset address in Data Segment during string operations.
Destination Index:
It holds offset address in Extra Segment during string operations.
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Instruction Register and Instruction Decoder:

The EU fetches an opcode from the queue into the instruction register. The instruction
decoder decodes it and sends the information to the control circuit for execution.
Flag/Status register (16 bits):

Flag register of 8086

Flag register of 8086 is a 16-bit register where status of the latest Arithmetic operation
performed.

flag register of 8086

As it has 16-bits , it has 16 flags. These 16 flags are classified as

 7 are don’t care flags.

 3 are control flags (accessible to programmers).
 6 are status flags (not accessible to programmers).
It has 9 flags that help change or recognize the state of the microprocessor.
6 Status flags:
 carry flag (CF)
 parity flag (PF)
 auxiliary carry flag (AF)
 zero flag(Z)
 sign flag(S)
 overflow flag (O)

Status flags are updated after every arithmetic and logic operation.
3 Control flags:
 trap flag(TF)
 interrupt flag(IF)
 direction flag(DF)
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These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI,
STI, etc. The Control flags are used to control certain operations.
Conditional Flags (Status flags):
CF:
It stands for carry flag.
If CF = 1 ;in the output if carry is generated from the MSB.
If CF = 0 ; no carry in the output.

PF:It stands for parity flag.

If PF = 1 ;if even parity in the result ( there are even numbers of 1’s ).
If PF = 0 ; odd parity.

SF:This stands for sign flag. In short it copies the value of MSB.
If SF = 1 ; output is -ve, If SF = 0 ; output is +ve.

ZF:This is zero flag. Whenever the output is 0 this flag is 1.

If ZF = 1 ; output is zero. , If ZF = 0 ; output is non zero.
OF:OF stands for overflow flag.This flag represents the result when the system capacity is
exceeded.
If OF = 1 ; output having overflow otherwise Zero.
AF:AF stands for auxiliary flag. As 8-bits form a byte, similarly 4 bits form a nibble. So in
16 bit operations there are 4 nibbles.
If AF = 1 ; there is a carry out from lower nibble of the result.
If AF = 0 ;no carry out of lower nibble.

CF, AF, PF, ZF, OF, SF, these were status flags, and these keep changing after every
arithmetic operation. And these flags are not controlled by the user, these are controlled by
the ALU.
Control flags:
There are three types of control flags, and by default all are zero.
TF:This stands for trap flag. Generally, processors give output after the complete program,
but when TF = 1, output is given after every instruction.

IF:This is interrupt flag.

IF = 1, then enable interrupts, IF = 0, then interrupts are disabled. By default, interrupts are
disabled.
DF:This stands for direction flag. In the case string operation, by default address keeps
incrementing for instruction execution. It means after execution of an instruction, whether the
processor should execute next instruction or previous instruction.
If DF = 0 ; auto incrementing the memory locations
If DF = 1 ; auto decrementing the memory locations
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Pin Diagram/Description of 8086 Microprocessor

Intel 8086 is a 16-bit microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC

supply for its operation.
The 8086 uses 20-line address bus.
It has a 16-line data bus. The 20 lines of the address bus Operate in multiplexed mode.
The 16-low order address bus lineshave been multiplexed with data and 4 high-order address
bus lines havebeen multiplexed with status signals.

AD0-AD15 (2 to 16 &39 )- Address/Data bus.

These are low order address bus. 16 lines are time multiplexed address and data so as to
reduce the number of lines inside the IC.
During T1: They carry lower order 16-bits. In the remaining clock cycles lower order bits of
data.
A16/S3, A17/S4, A18/S5 and A19/S6 (38 to 35) :
Out of 20 address bits, 4 are in the time multiplexed with the status signals.
During time T1, they carry higher order 4-bit address signals and in remaining cycles, they
carry status signals.
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S5 is used as interrupt flag.

S6- is always low.
S7 : It remains always high;

S4 and S3 are used toselect the segment out of the four segments.
S4 S3 Segment
selected
0 0 ES
0 1 SS
1 0 CS
1 1 DS

BHE' / S7(34)-
BHE stands for Bus High Enable. It is an active low signal, decides whether the data bus will
carry 16-bit data or 8-bit data.

BHE' A0 Indication

0 0 Whole Word
0 1 Upper byte from/to odd address
1 0 Lower byte from/to even address
1 1 None

RESET (21) – Whenever this pin is enabled then it resets the processor and other devices
connected to the system by immediately terminating the recent task.
VCC (40) – At this pin, the external power supply of + 5V is provided to the processor.
GND(1 and 20) – These two pins act as the ground.
RD’ (32) – An active low signal at this pin shows that the microprocessor is performing read
operation with either memory or I/O devices.
CLK (19) – A signal at this pin provides the basic timing for processor operations.
NMI (17) – NMI is Non-Maskable Interrupt(Edge triggered interrupt)
These interrupts are basically uncontrollable interrupts generated inside the processor.
INTR (18) – It is Maskable Interrupt.
INTR stands for an interrupt request (level triggered interrupt)
the signal is active high to determine if the processor considered this as an interrupt or not.
TEST ( 23) – It is used in conjunction with the WAIT instruction in multiprocessing
environment.
Test signal is used to test the status of math coprocessor 8087.
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READY (22) – This signal is used by the peripherals to indicate whether the peripheral
device is ready to transmit data or not.
MN/MX’(33)-It indicates in which mode the processor is to operate. When it is High- min-
mode, when it is Low- max-mode
MN/MX’ (33) –This pin shows whether the processor is operating in the minimum mode or
maximum mode.
MN/MX’ – 0 8086 is operating in maximum mode, i.e., multiple processors.
MN/MX’ – +5v operation under minimum mode., i.e., single processor.

Minimum mode Pins

INTA’ (24)– It is an interrupt acknowledge pin. Whenever an INTR signal is generated, then
the microprocessor generates INTA signal, as a response to that interrupt.
ALE (25) – It stands for address latch enable
A positive pulse is generated each time the processor begins any operation.
This signal indicates the availability of a valid address on the address/data lines.

HOLD(31)-Active High signal

When DMA Controller needs to use a address/data bus it sends request to CPU through this
pin.
HLDA(30)-Hold Acknowledgement signal.
When processor receives HOLD signal it issues HLDA to DMA.
DEN’(26)-It stands for Data Enable It is used to enable Transreceiver.
The transreceiver is a device used to separate data from the address/data bus.
DT/R’ (27) – It stands for Data Transmit/Receive signal.
It decides the direction of data flow through the transreceiver.
When it is high, data is transmitted out. otherwise received data.
M/IO’(28)-This signal is used to distinguish between memory and I/O operations.
When it is high, it indicates memory operation and
when it is low indicates the I/O operation.
WR’(29)-It stands for write signal. It is used to write the data into the memory or the output
device depending on the status of M/IO signal.

Maximum mode Pins

QS1 and QS0 (24 & 25)-These are queue status signals to provide the status of instruction
queue. Their conditions are shown in the following table –
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Qs1 QS 0 Status

0 0 No operation

0 1 First byte of opcode from the

queue

1 0 Empty the queue

1 1 Subsequent byte from the

queue

S0’,S1’,s2’(26,27,28)-

S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Opcode Fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive State

LOCK’ (29)-When this signal is active, it indicates to the other processors not to ask the CPU to
leave the system bus. It is activated using the LOCK prefix on any instruction.
RQ’/ GT0‘and RQ’/ GT1‘(30 and 31) : These are the Request/Grant signals used by the external
devices requesting the CPU to release the system bus.
When the signal is received by CPU, then it sends acknowledgment. RQ/GT 0 has a higher priority
than RQ/GT1.
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8086 has two operating Modes:

 Minimum mode
 Maximum mode
Minimum mode:
•In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode
by strapping itsMN/MX pin to logic 1.

•In this mode, all the control signals are given out by the microprocessor chip itself. There is
a single microprocessor in the minimum mode system.

•The remaining components in the system are latches, transreceivers, clock generator,
memory and I/O devices. Some type of chip selection logic may be required for selecting
memory or I/O devices, depending upon the address map of the system.

•Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used
for separating the valid address from the multiplexed address/data signals and are controlled
by the ALE signal generated by 8086.

•Trans receivers are the bidirectional buffers and sometimes they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/data signals. They are controlled by two signals namely, DEN and DT/R.

The DEN signal indicates the direction of data, i.e. from or to the processor. The system
contains memory for the monitor and users program storage.
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•Usually, EPROMs are used for monitor storage, while RAM for users program storage. A
system may contain I/O devices.

Timing diagrams of minimum mode:

BUS CYCLE AND TIME STATES

• A bus cycle or machine cycle defines the sequence of events when the MPU communicates
with an external device, which starts with an address being output on the system bus followed
by a read or write data transfer.

• Types of bus cycles: Memory Read Bus Cycle Memory Write Bus Cycle
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The bus cycle of the 8086 microprocessor consists of at least four clock periods. These four
time states are called T1, T2, T3 and T4. This group of states is called a machine cycle.

The total time required to fetch and execute an instruction is called an instruction cycle. An
instruction cycle consists of one or more machine cycle.

The following figure shows a memory read cycle of the 8086:

• During period T1,

 The 8086 outputs the 20-bit address of the memory location to be accessed on its
multiplexed address/data bus. BHE is also output along with the address during T1.
 At the same time a pulse is also produced at ALE. The trailing edge or the high level
of this pulse is used to latch the address in external circuitry.
 Signal M/IO is set to logic 1 and signal DT/R is set to the 0 logic level and both are
maintained throughout all four periods of the bus cycle.

• Beginning with period T2,

 Status bits S3 through S6 are output on the upper four address bus lines. This status
information is maintained through periods T3 and T4.
 On the other hand, address/data bus lines AD0 through AD7 are put in the high-Z
state during T2. o Late in period T2, RD is switched to logic 0. This indicates to the
memory subsystem that a read cycle is in progress. DEN is switched to logic 0 to
enable external circuitry to allow the data to move from memory onto the
microprocessor's data bus.

• During period T3,

 The memory must provide valid data during T3 and maintain it until after the
processor terminates the read operation. The data read by the 8086 microprocessor
can be carried over all 16 data bus lines.

• During T4,

 The 8086 switches RD to the inactive 1 logic level to terminate the read operation.
DEN returns to its inactive logic level late during T4 to disable the external circuitry.

The following figure shows a memory write cycle of the 8086:

• During period T1,

 The address along with BHE is output and latched with the ALE pulse.
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 M/IO is set to logic 1 to indicate a memory cycle.

 However, this time DT/R is switched to logic 1. This signals external circuits that the
8086 is going to transmit data over the bus.

• Beginning with period T2,

 WR is switched to logic 0 telling the memory subsystem that a write operation is to

follow.
 The 8086 puts the data on the bus late in T2 and maintains the data valid through T4.
Data will be carried over all 16 data bus lines.
 DEN enables the external circuitry to provide a path for data from the processor to the
memory.

Maximum mode:
•In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.

In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
•In the maximum mode, there may be more than one microprocessor in the system
configuration.
•The components in the system are same as in the minimum mode system.
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•The basic function of the bus controller chip IC8288, is to derive control signals like RD and
WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the
processor on the status lines.
•The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven
by CPU.
•It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.
Timing diagrams of maximum mode:
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•IORC, IOWC are I/O read command and I/O write command signals respectively.
These signals enable an IO interface to read or write the data from or to the address port.
•The MRDC, MWTC are memory read command and memory write command signals
respectively and may be used as memory read or write signals.
•All these command signals instructs the memory to accept or send data from or to the bus.
•For both of these write command signals, the advanced signals namely AIOWC and
AMWTC are available.
•Here the only difference between in timing diagram between minimum mode and maximum
mode is the status signals used and the available control and advanced command signals.
•R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on
the ALE and apply a required signal to its DT / R pin during T1.
•In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC
is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.
•The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
•If reader input is not activated before T3, wait state will be inserted between T3 and T4.
RQ/GT0, RQ/GT1 (Request/Grant):
These pins are used by other local bus masters, in maximum mode, to force the processor to
release the local bus at the end of the processor’s current bus cycle. Each of the pins is
bidirectional with RQ0/GT0 having higher priority than RQ1/GT1.

Advantages of max mode of 8086:

It helps to interface more devices like 8087.This interface is also called a closely coupled co-
Processor configuration. In this 8086 is called as the host and 8087 as Co-processor.
It supports multiprocessing, Therefore it helps to increase the efficiency.
The 8087 was the first floating-point co-processor for the 8086 series of microprocessors.
The purpose of the 8087 was to increase calculations for floating point operations, such as
add, sub, multiply, divide, and square root.
Disadvantages of max mode over min mode:
It has more complex circuit than min mode.