CMOS VLSI design

The beginning
2

 Microprocessors are essential to many of the products we use every day such as TVs, cars,
radios, home appliances and of course, computers. Transistors are the main components of
microprocessors.

 At their most basic level, transistors may seem simple. But their development actually required
many years of painstaking research. Before transistors, computers relied on slow, inefficient
vacuum tubes and mechanical switches to process information. In 1958, engineers managed to
put two transistors onto a Silicon crystal and create the first integrated circuit, which
subsequently led to the first microprocessor.

Prepared Friday, May 23, 2025

 History and Evolution
3

 In 1976, Steve Jobs and Steve Wozniak built the Apple II, the first personal computer in a
garage in California.
 Then, in 1981, IBM introduced its first personal computer. The personal computer was such a
revolutionary concept and was expected to have such an impact on society that in 1982, "Time"
magazine dedicated its annual "Man of the Year Issue" to the computer. The other feature of
the microprocessor is its versatility. Whereas previously the integrated circuit had had to be
manufactured to fit a special purpose, now one microprocessor could be manufactured and then
programmed to meet any number of demands. Soon everyday household items such as
microwave ovens, television sets and automobiles with electronic fuel injection incorporated
microprocessors.
 The 1980's saw an expansion in computer use in all three arenas as clones of the IBM PC made
the personal computer even more affordable. The number of personal computers in use more
than doubled from 2 million in 1981 to 5.5 million in 1982. Ten years later, 65 million PCs
were being used. Computers continued their trend toward a smaller size, working their way
down from desktop to laptop computers (which could fit inside a briefcase) to palmtop (able to
fit inside a breast pocket).

Prepared Friday, May 23, 2025

 Why VLSI?
4

 Integration improves the design

 Lower parasitics = higher speed
 Lower power consumption
 Physically smaller
 Integration reduces manufacturing cost - (almost) no manual assembly

Prepared Friday, May 23, 2025

 Introduction
5
Very-large-scale integration (VLSI) is the process of creating an IC by combining thousands
of transistors into a single chip. VLSI began in the 1970s when
complexsemiconductor and communication technologies were being developed.
The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had
a limited set of functions they could perform. An electronic circuit might consist of
a CPU, ROM, RAM and other glue logic. VLSI lets IC makers add all of these into one chip.

By the 1980's, very large scale integration (VLSI) squeezed hundreds of thousands of components
onto a chip. The ability to fit so much onto an area about half the size of a U.S. dime helped
diminish
the size and price of computers. It also increased their power, efficiency and reliability. Marcian
Hoff
invented a device which could replace several of the components of earlier computers, the
microprocessor. The microprocessor is the characteristic of fourth generation computers, capable of
performing all of the functions of a computer's central processing unit. The reduced size, reduced
cost, and increased speed of the microprocessor led to the creation of the first personal computers.
Until now computers had been the almost exclusively the domain of universities, business and
government.
Prepared Friday, May 23, 2025
 Introduction
6

 IC: Integrated Circuits, many transistors on one chip

 VLSI: Very Large Scale Integration, a modern technology of IC design flow
 MOS: Metal-Oxide-Silicon transistor (also called device)
 CMOS: Complementary Metal Oxide Semiconductor

Prepared Friday, May 23, 2025

 Moore’s Law
7

Gordon Moore: co-founder of Intel

Predicted that the number of transistors per chip would grow
exponentially (double every 18 months)
Exponential improvement in technology is a natural trend:
e.g. Steam Engines - Dynamo - Automobile

Prepared Friday, May 23, 2025

 Technology Background
8

 What is a Silicon Chip?

A pattern of interconnected switches and gates on the surface of a crystal

of semiconductor (typically Si)
These switches and gates are made of
areas of n-type silicon
areas of p-type silicon
areas of insulator
lines of conductor (interconnects) joining areas together
Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten
The geometryof these areas is known as the layout of the chip
Connections from the chip to the outside world are made around the edge
of the chip to facilitate connections to other devices

Prepared Friday, May 23, 2025

 Technology Background
9

 Semiconductors and Doping

•Adding trace amounts of certain materials to semiconductors alters the crystal
structure and can change their electrical properties
in particular it can change the number of free electrons or holes
•N-Type
semiconductor has free electrons
dopant is (typically) phosphorus, arsenic, antimony
•P-Type
semiconductor has free holes
dopant is (typically) boron, indium, gallium
Dopants are usually implanted into the semiconductor using Implant Technology,
followed by thermal process to diffuse the dopants

Prepared Friday, May 23, 2025

 Silicon Lattice
10

 Transistors are built on a silicon substrate

 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Prepared Friday, May 23, 2025

 Dopants
11

 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity

 Group V: extra electron (n-type)

 Group III: missing electron, called hole (p-type)

Prepared Friday, May 23, 2025

 VLSI Chip Types
12

 At the engineering level, digital VLSI chips are classified by the approach
used to implement and build the circuit
 Full-custom Design: where every circuit is custom designed for the project
 Extremely tedious

 Time-consuming process

 Application-Specific Integrated Circuits (ASICs): using an extensive suite of CAD

tools that portray the system design in terms of standard digital logic constructs
 Including state diagrams, functions tables, and logic diagram
 Designer does not need any knowledge of the underlying electronics or the physic of the silicon chip
 Major drawback is that all characteristics are set by the architectural design

 Semi-custom Design: between that of a full-custom and ASICs

 Using a group of primitive predefined cells as building blocks, called cell library

Prepared Friday, May 23, 2025

 Integrated Circuits
13

 SSI – Small-Scale Integration (0-102)---1960

 MSI – Medium-Scale Integration (102-103)---1967
 LSI – Large-Scale Integration (103-105)---1972
 VLSI – Very Large-Scale Integration (105-107)---1978
 ULSI – Ultra Large-Scale Integration (>=107)---1989
 GSI _ Giant Scale Integration (>=109)---2000

Prepared Friday, May 23, 2025

 Integrated Circuits
14

 Why Make Ics ?

 Integration improves
 size
 speed
 power
 Integration reduce manufacturing costs
 (almost) no manual assembly

Prepared Friday, May 23, 2025

 IC Evolution (1/3)
15

 SSI – Small Scale Integration (early 1970s)

 contained 1 – 10 logic gates
 MSI – Medium Scale Integration
 logic functions, counters
 LSI – Large Scale Integration
 first microprocessors on the chip
 VLSI – Very Large Scale Integration
 now offers 64-bit microprocessors,
complete with cache memory (L1 and often L2),
floating-point arithmetic unit(s), etc.
 Bipolar technology
 TTL (transistor-transistor logic)
 ECL (emitter-coupled logic)

Prepared Friday, May 23, 2025

 IC Evolution (2/3)
16

 MOS (Metal-oxide-silicon)
 although invented before bipolar transistor,
was initially difficult to manufacture
 nMOS (n-channel MOS) technology developed in 1970s
required fewer masking steps, was denser, and consumed less power than equivalent
bipolar ICs => an MOS IC was cheaper than a bipolar IC and led to investment and growth
of the MOS IC market.
 aluminum gates for replaced by polysilicon by early 1980
 CMOS (Complementary MOS): n-channel and p-channel MOS transistors =>
lower power consumption, simplified fabrication process
 Bi-CMOS - hybrid Bipolar, CMOS (for high speed)
 GaAs - Gallium Arsenide (for high speed)
 Si-Ge - Silicon Germanium (for RF)

Prepared Friday, May 23, 2025

Comparison of available
technology
 Chips
18

 Integrated circuits consist of:

 A small square or rectangular “die”, < 1mm thick
 Small die: 1.5 mm x 1.5 mm => 2.25 mm 2

 Large die: 15 mm x 15 mm => 225 mm2

 Larger die sizes mean:

 More logic, memory

 Less volume
 Less yield

 Dies are made from silicon (substrate)

 Substrate provides mechanical support and electrical common point

Prepared Friday, May 23, 2025

 IC
19

From Howe, Sodini: Microelectronics:An Integrated Approach, Prentice Hall

Prepared Friday, May 23, 2025

 Basic MOS Transistors
➢ Minimum line width
➢ Transistor cross section
➢ Charge inversion channel
➢ Source connected to substrate
➢ Enhancement vs. Depletion mode devices
➢ p-MOS are 2.5 time slower than n-MOS due to
electron and hole mobilities
 nMOS Transistor

• Four terminals: gate, source, drain, body

• Gate – oxide – body stack looks like a capacitor
» Gate and body are conductors
» SiO2 (oxide) is a very good insulator
» Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
SiO2

n+ n+

p bulk Si
 nMOS Operation
• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage:
» P-type body is at low voltage
» Source-body and drain-body diodes are OFF
» No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si
 nMOS Operation
• When the gate is at a high voltage:
» Positive charge on gate of MOS capacitor
» Negative charge attracted to body
» Inverts a channel under gate to n-type
» Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
 pMOS Transistor
• Similar, but doping and voltages reversed
» Body tied to high voltage (VDD)
» Gate low: transistor ON
» Gate high: transistor OFF
» Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si
 Power Supply Voltage
➢ GND = 0 V
➢ In 1980’s, VDD = 5V
➢ VDD has decreased in modern processes due to scaling
» High VDD would damage modern tiny transistors
» Lower VDD saves power (Dynamic power is
propotional to C.VDD2.f.a)
➢ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
 Transistors as Switches
• We can view MOS transistors as electrically controlled
switches
• Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
 Why “CMOS VLSI”?
CMOS circuits have several advantages over NMOS and PMOS circuits, including:

Power consumption: CMOS circuits consume less power than NMOS and PMOS
circuits. CMOS circuits can be operated at lower voltages and currents, which reduces
heat dissipation and extends battery life.

Noise margins: CMOS circuits have better noise margins than NMOS and PMOS
circuits.

Scalability: CMOS circuits have enhanced scalability.

Cost: CMOS circuits are cost-effective in the long term.

Switching speed: CMOS circuits have fast low-to-high and high-to-low output
transitions.

Temperature stability: CMOS circuits have strong temperature stability.

Integration: CMOS circuits have a high degree of integration, with the entire circuit
integrated in the chip.

Simple structure: CMOS circuits have a simple structure.

CMOS: Complementary MOS
➢ Means we are using both N-channel and P-
channel type enhancement mode Field Effect
Transistors (FETs).
➢ Field Effect- NO current from the controlling
electrode into the output
FET is a voltage controlled current device
BJT is a current controlled current device
➢ N/P Channel - doping of the substrate for
increased carriers (electrons or holes)
 Types of CMOS fabrications
 N-WELL PROCESS
 P-WELL PROCESS
 TWIN TUB PROCESS
 Formation of n-well regions

Define nMOS and pMOS active areas

Field and Gate Oxidations (thinox)

Form and Pattern Polysilicon

p+ diffusion

n+ diffusion

Contact cuts

Deposit and pattern metallization

Over glass with cuts for bonding pads

CMOS Fabrication

n-well process
 p-doped Wafer

Oxidation
SiO2

Oxidation

p-substrate

p-substrate
 Photoresist
Photo-resist
Oxidation

p-substrate
 Photolithography
UV
rays

Photo-resist
Oxidation

p-substrate
Removal of soluble photoresist

Photoresist
Oxidation

p-substrate
 Removal of exposed SiO2

Photo-resist
Oxidation

p-substrate
 Removal of remaining
photoresist

Oxidation

p-substrate
N-well formation using diffusion

Oxidation

n-well

p-substrate
Removal of remaining SiO2

n-well

p-substrate
 Gate oxide and Polysilicon Layer

Thin gate Polysilicon layer

oxide

n-well

p-substrate
 Photolithography

UV
rays

Thin gate Polysilicon layer

oxide

n-well

p-substrate
Removal of soluble polysilicon

n-well

p-substrate
 Gate oxide masking

Thick
gate
oxide

n-well

p-substrate
 Photolithography

UV
rays

n-well

p-substrate
Removal of exposed gate oxide

n-well

p-substrate
Ion implantation of n+ dopants

n+ n+ n+

n-well

p-substrate
Ion implantation of p+ dopants
(similar way)

p+ n+ n+ p+ p+ n+

n-well

p-substrate
 Metallization
(uses Aluminum)

p+ n+ n+ p+ p+ n+

n-well

p-substrate
 Removal of excess metal

p+ n+ n+ p+ p+ n+

n-well

p-substrate
Terminals: pMOS and nMOS

B S G D D G S B

p+ n+ n+ p+ p+ n+

n-well

p-substrate
 Drawbacks of N-well &p-well
 In both N-WELL and P-WELL we may got come across two problems.
✓ Body Effect
✓ Latch Up problem

 BODY EFFECT : increase in Substrate vlge the depletion layer increases

twrds substrate. And 4 ltl vgs curr vl b mre at drain.
 LatchUp : formation of ions b/w well n sub.

» To over come this drawback, we are going for “Twin Tub”.

 Body effect in a MOSFET
It is the change in threshold voltage that occurs when the voltage between the source and body
of the transistor is not equal. This effect can impact the conduction and output characteristics of
the MOSFET.

How does body effect occur?

• The substrate of the transistor acts as a second gate.
• The voltage difference between the source and body affects the threshold voltage.
• This voltage difference can cause the threshold voltage to increase or decrease.

Why is body effect important?

• Body effect is important to understand when designing circuits that operate under varying
substrate bias conditions.
• This includes analog and mixed-signal applications.

How to reduce body effect?

• Use a MOSFET with a longer channel.
• Reduce the doping concentration of the substrate.
• Reduce the thickness of the oxide layer.
• Use negative feedback technology.
 Body Bias in MOSFET
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has four terminals:
Source (S), Drain (D), Gate (G), Body (or Bulk) (B)

The body terminal of the MOSFET plays a crucial role in controlling the transistor's
behavior.

Body biasing refers to applying a voltage to the body terminal to modulate the
threshold voltage (Vₜ) of the MOSFET, influencing its switching speed and power
consumption.
Figure: Simplified display of
how the body bias effect can
alter the tON for a PMOS
transistor. Vs remains at
nominal voltage, while
Vb increases (reverse bias) or
decreases (forward bias).
This produces a similar
increase or decrease in tON,
respectively.
Effect of Body Bias on MOSFET Operation
Types of Body Biasing
 Is body bias and body effect are same in MOSFET?

No, while closely related, "body bias" and "body effect" are not exactly the same in a
MOSFET:
➢ "body effect" refers to the phenomenon where the threshold voltage of a MOSFET
changes due to a voltage difference between the source and the body (substrate),
➢ while "body bias" is the intentional act of applying a specific voltage to the body to
deliberately manipulate the threshold voltage and control the transistor's
behavior; essentially, body bias is a technique that leverages the "body effect" to
achieve desired circuit characteristics.

Key points to differentiate:

Body effect:
• A natural phenomenon occurring when the source and body voltages are not
identical, causing a change in the threshold voltage.

• Can be considered a parasitic effect in most cases.

Body bias:
• A deliberate design choice where the body voltage is actively set to a specific level to
control the transistor's operation.

• Used to optimize circuit performance by adjusting the threshold voltage.

 ✓Latch Up problem
Latch-up is a condition in CMOS circuits
that occurs when a parasitic device creates a
low-impedance path between the power
supply rails.
This can cause excessive current flow and
potentially damage the chip.

Causes
•Supply voltages: Supply voltages that exceed the maximum ratings can cause latch-up.
•Transient voltages: Transient voltages on supply rails can cause latch-up.
•Input/output pin voltage: When the input/output pin voltage exceeds either supply rail by more than a diode
drop, latch-up can occur.
•Electrostatic discharge (ESD): ESD events can trigger latch-up due to the large currents and voltages
involved.
•Ionizing radiation: Ionizing radiation, such as that found in space or nuclear environments, can trigger latch-
up.

Effects
•Latch-up can cause circuits to malfunction or consume excessive power.
•Latch-up can permanently damage the device.

Prevention
There are several design techniques that can reduce the susceptibility of CMOS circuits to latch-up. The
Hughes Aircraft company invented an industry-standard technique to prevent CMOS latch-up in 1977.
 Twin-tub Process
* It is made with both n-well and p-well region.
* Epitaxial layer: High purity silicon grown with
accurately determined dopant concentrations
 Comparison table of p-well n-well and twin-tub process of CMOS fabrication
Feature P-Well Process N-Well Process Twin-Tub Process
A fabrication process where A fabrication process where a A process where both P-well
Definition an N-type substrate has a P- P-type substrate has an N-well and N-well are created
well for NMOS transistors. for PMOS transistors. independently.
Can use both N-type and P-
Substrate Type N-type substrate P-type substrate
type wells independently.
Both P-well and N-well
Well Type P-well (for NMOS) N-well (for PMOS)
coexist.
NMOS transistors in the P- PMOS transistors in the N- Allows independent
MOSFET Type Supported well, PMOS transistors in the well, NMOS transistors in the optimization of NMOS and
N-substrate. P-substrate. PMOS transistors.
More complex than P-well Most complex due to the
Simple process but requires
Process Complexity due to additional well presence of both wells but
additional steps for PMOS.
formation. provides better performance.
NMOS performs well, but Provides better performance
PMOS performs better than in
PMOS has lower performance due to independent
Performance P-well, but NMOS may be
due to the use of an N-type optimization of NMOS and
slightly compromised.
substrate. PMOS.
Better control over both
Limited control over PMOS Limited control over NMOS
Threshold Voltage Control NMOS and PMOS threshold
transistor characteristics. transistor characteristics.
voltages.
Lowest risk due to separate
Higher risk due to single well Moderate risk, but still
Latch-up Immunity wells reducing parasitic
structure. possible.
interactions.
Common in CMOS Advanced CMOS
Older CMOS technologies,
Applications fabrication, used in VLSI technologies, high-
low-power applications.
circuits. performance circuits.
 CONT…
 At present the CMOS technologists are using “TWIN TUB” process.
 As It is giving effective result.
 Also it is more efficient.

Drawbacks of cmos
 CMOS is quite good for all the ELECTRONIC Gadgets.
 As they required 0-5V voltage.
 But coming to the ANALOG Equipment's … CMOS is poor to use.
 For that problem we are going to use BICMOS technology.
 BICMOS…
 BICMOS → BJT + CMOS
 As the drawback of CMOS is output load.
 At the output of the circuits we use BJT.
 Entire circuit is designed with CMOS.
 Cross sectional view
Bi-CMOS(n-p-n Transistor (orbit 2 um CMOS)
B F P
I A R
C B O
M R C
O I E
S C S
A S
T
I
O
N n-well BiCMOS fabrication process
steps
Comparison between CMOS
and Bipolar technologies
CMOS Bipolar technologies
 Low static power dissipation  High power dissipation
 High input impedance
 Low input impedance
 High noise margin
 High packing density  Low voltage swing logic
 High delay sensitivity to load  Low packing density
 Low output drive current
 Low delay sensitivity to
 Low gm
 Bidirectional capability load
 A near ideal switching device  High output drive current
 Scalable threshold voltage  High gm
 Essentially unidirectional
 Fabrication Technology
• Silicon of extremely high purity
» chemically purified then grown into large crystals
• Wafers
» crystals are sliced into wafers
» wafer diameter is currently 150mm, 200mm, 300mm
» wafer thickness <1mm
» surface is polished to optical smoothness
• Wafer is then ready for processing
• Each wafer will yield many chips
» chip die size varies from about 5mmx5mm to 15mmx15mm
» A whole wafer is processed at a time
 Fabrication Technology

➢ Different parts of each die will be made P-type or N-

type (small amount of other atoms intentionally
introduced - doping -implant)
➢ Interconnections are made with metal
➢ Insulation used is typically SiO2. SiN is also used.
New materials being investigated (low-k dielectrics)
➢ nMOS Fabrication
➢ CMOS Fabrication
➢ p-well process
➢ n-well process
➢ twin-tub process
 Fabrication Technology

• All the devices on the wafer are made at the same time
• After the circuitry has been placed on the chip
» the chip is over-glassed (with a passivation layer) to protect it
» only those areas which connect to the outside world will be left
uncovered (the pads)
• The wafer finally passes to a test station
» test probes send test signal patterns to the chip and monitor the
output of the chip
• The yield of a process is the percentage of die which
pass this testing
• The wafer is then scribed and separated up into the
individual chips. These are then packaged
• Chips are ‘binned’ according to their performance
 VLSI Design
 In present days all the Electronic Devices are made of
using these VLSI CHIPS.
 These VLSI are designed by CMOS.
 In Earlier they used several types of active devices.

y-chart, design flow

 Complexity and Design
71

 Creating a design team provides a realistic

approach to approaching a VLSI project, as it
allows each person to study small sections of the
system

 Needing hundreds of engineers, scientists, and

technicians

 Needing hierarchy design and many different “Level

Views”

 Everyone of each level depends upon the Computer-

Aided Design (CAD) tools

Figure 1.1 The VLSI design funnel

Prepared Friday, May 23, 2025

 The Process of VLSI Design:
• Consists of many different
representations/Abstractions of the system (chip)
that is being designed.
➢ System Level Design
➢ Architecture / Algorithm Level Design
➢ Digital System Level Design
➢ Logical Level Design
➢ Electrical Level Design
➢ Layout Level Design
➢ Semiconductor Level Design (possibly more)
• Each abstraction/view is itself a Design Hierarchy
of refinements which decompose the design.
Design Abstraction Levels

SYSTEM

MODULE
+

GATE

CIRCUIT

DE VICE
G
S D
n+ n+
 Design Hierarchy (1/2)
75

 System specifications: is defined in both general and

specific terms, such as functions, speed, size, etc.

 Abstract high-level model: contains information on the

behavior of each block and the interaction among the
blocks in the system

 Logic synthesis: To provide the logic design of the

network by specifying the primitive gates and units
needed to build each unit

 Circuit design: where transistors are used as switches and

Boolean variables are treated as vary voltage signals

 Physical design: the network is built on a tiny area on a

slice of silicon

 Manufacturing: a completed design process is moved on

to the manufacturing line Figure 1.2 General overview
of the design hierarchy

Prepared Friday, May 23, 2025

 Design Hierarchy (2/2)
76

 Hierarchical design
 Top-down design
 the initial work is quite abstract and theoretical and
there is no direct connection to silicon until many
steps have been completed
 Acceptable in modern digital system design
 Co-design with combining HW/SW is critical
 Similar to Cell-based Design Flow

 Bottom-up design
 starts at the silicon or circuit level and builds
primitive units such as logic gates, adders, and
registers as the first steps
 Acceptable for small projects
 Similar to Full-custom Design Flow

 An example of a design hierarchy in

Figure 1.3
 an instruction design of a microprocessor

Register_X  A + B Figure 1.3 A simple design

flow for a microprocessor

Prepared Friday, May 23, 2025

 VLSI DESIGN FLOW

FLOW CHART FOR VLSI DESIGN FLOW

➢DESIGN SPECIFICATION
➢DESIGN ENTRY
➢FUNCTIONAL SIMULATION
➢PLANNING PLACEMENT AND ROUTING(PPR)
➢TIMING SIMULATION
➢FUSING/FABRICATION IN TO THE CHIP
FLOW CHART FOR VLSI DESIGN FLOW
 DESIGN SPECIFICATION

➢ The Algorithm to be implemented in detail with mathematical representation.

➢ Number of inputs and outputs in the design and number of bits in each of them.

➢ Number of bits used in the internal arithmetic operation.

➢ Number of clock signals to be used in the design.

➢ Maximum clock frequency to be used.

➢ Area of the chip.

➢ Power dissipation in the chip.

 DESIGN ENTRY

➢TWOTYPES

➢ Schematic Entry

➢ Hardware Description Language

➢Verilog HDL.
➢VHDL.
DESIGN ENTRY
 FUNCTIONAL SIMULATION

➢ Before Design implementation , functional simulation is performed to verify

the logic created is correct or not.

➢ Design methodology determines it performance.

➢ Schematic Flow-It is performed directly after completing design within the

design entry tools.

➢ HDL Flow-It is performed after the design has been entered and synthesized.
FUNCTIONAL SIMULATION
OF T- FLIPFLOP
 PLANNING PLACEMENT AND
ROUTING(PPR)
➢ VLSI physical design or Layout phase

➢ Automated design process using Computer Aided Design(CAD) Tools.

➢ Various phases
➢ Partitioning
➢ Floor planning
➢ Placement
➢ Routing
 PLANNING PLACEMENT AND
ROUTING(PPR)

➢ PARTITIONING:-

Task of dividing a circuit in such a way so that the area of each sub-circuit is well
with in the prescribed range and number of interconnection between sub-circuits is
also minimized.

➢ FLOOR PLANNING:-

Step to determine the shape of each sub circuit module and pin location at their
boundary and find out the approximate location of each module in a rectangular chip.
 PLANNING PLACEMENT AND
ROUTING(PPR)

➢ PLACEMENT:-
It is the problem of determination of best position of each module, when each module
has a fixed shape , area and terminals .

➢ ROUTING:-
It is the method of interconnection of different circuit components, with an aim to
minimize the chip area and also reduction of total wire-length.
➢ Two types
✓ Global Routing
✓ Channel Routing
PARTITIONING &
FLOORPLANNING
PLACEMENT & ROUTING
 TIMING SIMULATION

➢ Constitutes on NET Delays and GATE Delays.

➢ Delays encountered by a signal for traversing from output of one gate to the
input of another gate is called NET Delays.

➢ Delays from input of one gate to the output of same gate due to propagation
time of the gate is called GATE Delays.

➢ It is done with the clock speed.

 FUSING/FABRICATION IN TO THE CHIP

➢ Last step in VLSI Design.

➢ Two different design styles

➢Full custom
➢Semi custom
➢ Cell based design
➢ Array based design
 FUSING/FABRICATION IN TO THE CHIP

➢ FULL CUSTOM:-
The semiconductor chips are ASIC’s which are designed
specifically for a given application or application domain.
➢ SEMI-CUSTOM:-
➢ CELL BASED DESIGN – uses libraries of predesigned cells which are then
placed and wired to complete the design.
➢ ARRAY BASED DESIGN – uses a prefabricated matrix of non-connected
components. FPGA uses programmable logic modules and also
programmable interconnections in which configuration data is loaded
during each application.
μm-based (Micron-based) Design Rules in VLSI
- μm-based design rules use absolute dimensions in
micrometers (μm).
- Define minimum width, spacing, and alignment of
semiconductor components.
- Technology-specific, designed for nodes like 180nm, 90nm,
65nm.

Importance of μm-based Design Rules

Ensures correct fabrication & manufacturability.
Controls device performance, yield, and reliability.
Standardizes layout design for specific fabrication
technologies.
 Key Design Parameters
Each fabrication technology (e.g., 180nm, 90nm, 65nm) has its own set of μ-based
design rules.
Below are some important parameters:

Example (180nm
Design Parameter Description
Technology)
Minimum Gate Length Smallest possible channel
0.18μm
(Lmin) length of a transistor.
Minimum Gate Width Smallest width of a
0.24μm
(Wmin) transistor channel.
Smallest width of metal
Minimum Metal Width 0.25μm
interconnects.
Minimum distance between
Minimum Metal Spacing 0.30μm
two metal wires.
Minimum size of a via or
Contact Size 0.24μm × 0.24μm
contact cut.
Distance between two
Active Area Spacing 0.35μm
active diffusion regions.
Each of these rules ensures that the fabricated devices function correctly without
defects due to process limitations.
For a 90nm Technology, the design rules might look like this:

Feature Minimum Dimension

Gate Length 0.09μm
Gate Width 0.12μm
Poly-Silicon Width 0.1μm
Metal Width 0.13μm
Metal Spacing 0.14μm
Contact Size 0.12μm × 0.12μm
 Rules for Different Layout
Elements
 (a) MOSFET Transistor Rules:
 - Defines minimum channel length (Lmin).
 - Ensures correct source/drain diffusion spacing.

 (b) Interconnect Rules:

 - Metal width & spacing to prevent short circuits.
 - Via/contact size for layer connectivity.

 (c) Well and Substrate Rules:

 - Defines minimum n-well & p-well spacing.
 - Prevents latch-up issues.
 Advantages & Disadvantages
 High precision in layout design.
 Ensures manufacturability for a specific technology.
 Optimized performance for given technology constraints.

 Not scalable; requires redesign for new technology nodes.

 Complex migration from one node to another.
 Manual adjustments needed when transitioning technologies.
 Comparison with λ-based Rules

Feature μ-based Rules λ-based Rules

Uses fixed μm Uses a relative
Definition
values unit (λ)
Scalability Not scalable Easily scalable
Precision High Moderate
Ease of Requires
Easily adaptable
Migration redesign
λ-based (Lambda-based) Design Rules in VLSI
Introduction
- λ-based design rules use a **scalable unit (λ)** instead of fixed
dimensions.
- Define layout constraints in terms of **λ**, making designs
**technology-independent**.
- Easily **scales with different technology nodes** (e.g., 180nm,
90nm, 45nm).

**Scalable** across different fabrication technologies.

**Simplifies layout migration** from one node to another.
**Ensures design consistency** in different process technologies.
 Key Design Parameters
Design Parameter Value in λ Description
Smallest allowable transistor
Minimum Gate Length 2λ
channel length

Minimum Gate Width 3λ Smallest allowable transistor width

Minimum width of metal

Minimum Metal Width 3λ
interconnects
Minimum distance between two
Minimum Metal Spacing 3λ
metal lines

Minimum Contact Size 2λ × 2λ Minimum via/contact dimensions

Minimum Contact-to-Contact Minimum separation between two

2λ
Spacing contacts
Minimum distance between
Minimum Well-to-Well Spacing 6λ
adjacent wells

Minimum Active Region Width 4λ Minimum width for active regions

Minimum spacing between two

Minimum Poly-to-Poly Spacing 2λ
polysilicon lines
Minimum overlap of polysilicon
Minimum Poly Overlap on Active 1λ
over active region
 Rules for Different Layout Elements
 (a) **MOSFET Transistor Rules:**
 - Defines **minimum gate length as 2λ**.
 - Ensures proper source/drain spacing in λ units.

 (b) **Interconnect Rules:**

 - Metal width & spacing defined in λ.
 - Via/contact dimensions follow **multiples of λ**.

 (c) **Well and Substrate Rules:**

 - Defines **minimum well spacing in λ**.
 - Helps in reducing latch-up.
Advantages & Disadvantages
 **Highly scalable** for different process nodes.
 **Simplifies technology migration** without redesign.
 **Standardized design methodology** across industry.

 **Less precise** than absolute μm-based rules.

 **May require additional constraints** for optimization.
VLSI Design Lay-out
 MOS MODELING
 STICK DIAGRAM
 MOS LAYOUT
 Stick Diagram and
Representation
▪ A stick diagram is a stick representation for the layout and represented by
simple lines.
▪ It shows all components with relative placement.
▪ It does not show exact placement, transistor sizes, wire lengths, wire widths,
tub boundaries.

n-diffusion (device well, local interconnect)

Polysilicon (gate electrode, interconnect)
metal (contact, interconnect)
simple contact cut
depletion implant
Buried contact cut
Metal-1
 Mask Layout Encoding for
Different Layers
 N Type diffusion

 P -Type diffusion

 Polysilicon

 Metal 1

 Contact Cut

 Ion implantation

 Buried contact

 VDD or VSS contact

 Stick
Diagram
 Stick diagrams help plan layout quickly

» Need not be to scale

» Draw with color pencils or dry-erase markers

❑ Metal

❑ Polysilicon

❑ Metal Contact

❑ P-Doping

❑ N-Doping
 Stick Diagram & Corresponding
Mask Layout
Layout: Do not forget the
implants for depletion mode
transistors and to write in the
length to width (L:W) ratio for
each transistor
Stick Diagram & Corresponding
Mask Layout  Depletion
 Stick Diagram of NMOS &
PMOS

N-Well Area

P-Well Area
N-MOS (Enhancement &
Depletion)
Complete n-MOS-Stick
Diagram
CMOS Inverter
Layout & Stick Diagram of CMOS
Inverter
Depletion Load Inverter
CMOS-2 Input NAND &
NOR GATE
Stick Diagram of CMOS NAND
Gate-
Euler’s Path
Example:
Example 3-Eular Path:
Example 3-Stick Diagram
Example: z=(DC+A+B)bar
One More Example