SI Analysis overview
24th December 2024
Prepared by SI/PI Analysis Team
Ultimate Technologies Inc.
1F TS-Building, 1-15-3, Minamichitose,
Nagano City, 380-0823, Japan
TEL 026-267-7256 FAX 026-267-7259
www.uti2k.com
1) What is SI simulation?
[1] A system's signal integrity (SI) refers to the quality and reliability of the electrical signals that travel through the
circuit.
[2] Signal integrity is critical in high-speed designs, where signals transition between high and low voltages rapidly,
especially when designing integrated circuits (ICs), IC packages, printed circuit boards (PCBs).
[3] The increase in signal speed and decrease in the size of PCBs and packages make handling signal integrity issues
even more challenging with signal noise and distortion becoming more pronounced.
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SI Service Steps
Initial Preparation
Prepare SI Confirmation Sheet to be sent to UTI/client for verification
Receive SI request from UTI ➢ Identify simulation portions, signal frequencies, signal directions and draw
➢ Include PCB data, Schematic, Stack-up, Specifications, topology.
Simulation models and/or Datasheets ➢ List out related IC details and search respective data sheet, model.
➢ Check related eye mask criteria and/or s-parameter analysis criteria.
➢ Check skew requirements for high-speed signals (for TLCC preparation by UTI).
➢ Questions and requests to client for insufficient simulation details.
Update SI Confirmation Sheet based on reply/information from client/UTI
➢ Update simulation models, datasheets, frequencies and signal criteria.
Simulation
Receive PCB data from designer with TLCC. Prepare simulation files, run simulations and conduct analysis
➢ Check routing for any possible issues (trace W/S matching, ➢ Check pin configuration and set pins for substitute models if any.
proper return path, return vias,etc). ➢ Create Cadence Topo Xplorer, Ansys Electronic Designer simulation circuits
➢ PCB data conversion to Cadence Power SI or Ansys SIWave or HSPICE text script for simulation
data. ➢ Include the extracted PCB s-parameter, related models and components into
➢ Set ports and output PCB S-parameter for target signals. above simulation circuits and simulate.
➢ Check signal performance, possibly conduct initial pre-simulation.
➢ Re-do sim with layout changes, what-if setting, sub models for improvement.
SI Report ➢ Create results images (waveform, eye diagram and/or s-parameter curves).
➢ Include simulation conditions (simulation portion
topology, ICs, models, eye mask/s-parameter
analysis criteria,etc).
➢ Insert results images, any investigation or
improvement done with summary and conclusion,
for the selected interface.
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Typical High Speed SI Simulation Interface and Data Rates
Example Layout and High-Speed Portions
Interface Data Rates /
Frequency
LPDDDR ≅ 6.4Gbps
DDR ≅ 2.4Gbps
MDI
GMSL ≅ 3.5GHz
MIPI
GVIF ≅ 6GHz
PCIe Gen(1~4) 2.5Gbps ~ 16Gbps
USB Gen2 ≅ 10Gb/s
MIPI ≅ 4.5Gbps
SGMII ≅ 2.5Gbps
USXGMII ≅ 10.3125Gbps
RGMII ≅ 250Mbps
MDI (1000 Base-T1) ≅ 600MHz
LPDDR5
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2) Types of Simulation we do and CAD data format used
[1] CAD data is provided in Zuken CR8000(.dsgn) or CR5000(.pcb/.rul) format.
The CAD data is then converted to ODB++, ASCII(.dsgf), or .anf format in order to be used by simulator tools.
[2] CAD convertion to simulator tools for PCB trace characteristics s-parameter extraction done by :-
a) Cadence Power SI [using ODB++ or ASCII(.dsgf) formats] b) Ansys SIWave, HFSS [using ODB++ or .anf formats]
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Types of Simulation we do and CAD data format used
[3] Types of simulation and Tools used for respective simulation
a) Transient simulation for waveform and eye mask analysis using Cadence Topo Xplorer, Ansys Electronic Desktop or Synopsys HSPICE.
Topo Xplorer Circuit Electronic Desktop Circuit HSPICE script
HSPICE simulator
Example Topo Xplorer Simulation Results Example Electronic Desktop Simulation Results Example HSPICE Simulation Results
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Types of Simulation we do and CAD data format used
b) S-parameter analysis using Ansys Electronic Desktop.
Electronic Desktop Circuit Example Insertion Loss result Example Return Loss result
c) Impedance calculation using Ansys Q2D d) Parasitic capacitance calculation using Ansys Q3D.
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3) Design cycle-based simulation and Design pre-requisite for simulation
Design cycle-based simulation Design pre-requisite for simulation
Pre-simulation
▪ to determine quality of signal, especially new ▪ Impedance matching with proper trace W/S based on stackup.
interface, prior to complete board layout.
▪ TLCC length matching to satisfy interface skew requirement.
▪ Fulfil specific routing requirement from client if any.
Analysis
o check results based on voltage,timing and s- ▪ Provide design with proper reference ground plane as a return
parameter criteria. path.
o make layout changes, use what-if setting, sub
models and re-do simulation if needed.
Post simulation
▪ to obtain final layout results and/or confirm
improvement after changes based on pre-
simulation analysis.
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4) What types of SI Simulation Results we get ?
1. Time-Domain Results
➢ Waveforms:
1. Voltage or current over time for signals at various points in the circuit.
2. Useful for identifying signal distortions such as ringing, overshoot, undershoot, or unevenness.
➢ Eye Diagrams:
1. A visual representation of signal integrity over multiple bit periods, showing signal timing and amplitude margins.
2. Metrics derived include:
a. Eye height
b. Eye width
c. Slew rate
➢ Timing and Waveform Verification:
1. Quantifies timing variations, including total jitter (TJ), Aperture width etc
Waveform Results Eye diagram Results Timing and Waveform verification Results
TEYE_pcb_tx
40mV
-40mV
TEYE_pcb_tx=0.90UI
Driver and Receiver side Waveform
tJ 9
4) What types of SI Simulation Results we get ?
2. Frequency-Domain Results
➢ S-Parameters:
◼ Scattering parameters describe how signals behave in frequency space, including reflections, transmissions and crosstalk.
◼ Analyse signal loss, impedance mismatch, and frequency-dependent behaviour.
1. Insertion Loss and Return Loss:
• Insertion loss (S21, Sdd21): Measures signal attenuation through the system
• Return loss (S11, Sdd11): Measures signal energy reflected back due to impedance mismatches.
2. Near-End Crosstalk (NEXT), Far-End Crosstalk (FEXT):
• NEXT: Coupling of signals between adjacent lines measured at the transmitter end
• FEXT: Coupling measured at the far end of the victim line.
3. Mode Conversion limits:
• Loss due to the conversion of signal energy between different propagation modes.
4. Intra-Lane Cross Coupling:
• The coupling between the two wires is defined as the difference of s-parameters Scc21 and Sdd21 or Scc12 and Sdd12.
Insertion Loss Common mode FEXT Mode Conversion limits
Insertion Loss
Return Loss Return Loss Common mode NEXT Intra Lane Crosstalk
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5) What are examples of good & not good SI Simulation Results ?
1. Time-Domain Analysis
A. Not Good Results:
➢ Waveforms & Eye Diagram:
1. Significant overshoot, undershoot or ringing.
2. Slow rise or fall times leading to timing violations.
3. Closed or nearly closed eye due to excessive noise, jitter, or signal attenuation.
4. Poor noise margins (small eye height) or insufficient timing margins (narrow eye width).
Example: Eye diagram with high jitter.
B. Good Results:
➢ Waveforms & Eye Diagram:
• Clean signal transitions without excessive overshoot, undershoot or ringing.
• Signal reaches the desired voltage levels with optimal settling time.
• A wide-open "eye" with large eye height (good noise margin) and eye width (low jitter).
Example: Eye diagram for a High-speed signal with clear openings and no excessive jitter.
Good Results
Not Good Results
3,4 1 VinLimit(L)
1
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5) What are examples of good & not good SI Simulation Results ?
2. Frequency-Domain Analysis
A. Not Good Results:
➢ S-Parameters:
1. Steep fall in insertion loss (S21) within the frequency band of interest, leading to attenuation of high-speed signals.
2. High return loss indicating significant reflections and poor impedance matching.
3. Excessive crosstalk causing noise on adjacent channels.
Example: S21 dropping below -10 dB in the operational range, causing signal attenuation.
B. Good Results:
➢ S-Parameters:
• High insertion loss: Sufficient signal power reaches the receiver.
• Low return loss: Indicates minimal reflections due to impedance matching.
• Low Near-End Crosstalk (NEXT) and Far-End Crosstalk (FEXT): Minimal noise coupling between adjacent lines.
Examples:
a. Flat insertion loss curve across the frequency band of interest.
b. Gradual roll-off beyond the operational frequency range.
c. Return loss within acceptable design limits (e.g., <-12 dB for MIPI with data rate>1.5Gbps).
Insertion Loss Return Loss NEXT, FEXT
Not 1
Good Results 1
2
3
2
Good Results
c
a b a c
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6) What do we do when SI Simulation Results are not good ?
(before vs after Layout Improvement & Results example)
1. Identify the Cause of Issues
A. Review the specific results and pinpoint where and why the design is failing:
➢ Waveform Distortions (Ringing, Overshoot, Undershoot): Caused by impedance mismatches, long transmission lines, or
poor termination.
➢ Closed Eye Diagrams: Indicate excessive jitter, noise, or signal loss.
➢ High Return Loss or Reflections: Caused by impedance discontinuities.
➢ Crosstalk (NEXT, FEXT): Arises from closely spaced traces or poor routing.
➢ Insertion Loss or Attenuation: May stem from excessive trace length.
2. Correct Impedance Matching
A. Ensure the impedance of transmission lines matches the source and load:
➢ Adjust trace widths or stack-up design to maintain controlled impedance.
➢ Use proper termination resistors (e.g., series or parallel termination) to reduce reflections.
3. Address Crosstalk
A. Increase Trace Spacing: To reduce coupling between adjacent traces, especially for high-speed signals.
B. Use Ground Planes and add Ground Gaurds: Provide shielding and reduce noise coupling between layers by adding return
path.
4. Minimize Jitter and Reduce Signal Attenuation
A. Ensure proper termination to minimize signal reflections that can cause timing variations.
B. Minimize trace lengths for high-frequency signals to reduce loss.
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6) What do we do when SI Simulation Results are not good ?
(before vs after Layout Improvement & Results example)
MIPI S-parameter Original Layout Improved Layout
At L6 ~ L5 At L5 ~ L4 At L6 ~ L5 At L5 ~ L4
At L3 ~ L2 At L3 ~ L2
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1. MIPI signal trace overlap with other MIPI Layout has been improved with no overlapping
signal vias. MIPI signal vias/trace with Power plane, GND
2. MIPI signal vias overlap with GND/Power plane and other signal via/trace.
plane.
3. MIPI signal vias overlap with another signal
3
trace/plane.
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6) What do we do when SI Simulation Results are not good ?
(before vs after Layout Improvement & Results example)
Comparison results between Original layout and Improved layout
Original Layout Improved Layout
Comment:
With original layout, the insertion
loss result passes the limit line.
While, with improved layout, the
response of all pairs becomes more
consistent and they pass with
: CSI2-CLK[P/N] : CSI2-CLK[P/N] better margin.
: CSI2-CLK[P/N] : CSI2-CLK[P/N]
: CSI2-DATA[P/N] : CSI2-DATA[P/N]
: CSI2-DATA[P/N]2 : CSI2-DATA[P/N]2
Comment:
With original layout, the return loss
result for signals marginally passes the
limit line. While, with improved layout,
the response of all pairs becomes more
consistent and they pass with better
: CSI2-CLK[P/N] : CSI2-CLK[P/N]
margin.
: CSI2-CLK[P/N] : CSI2-CLK[P/N]
: CSI2-DATA[P/N] : CSI2-DATA[P/N]
: CSI2-DATA[P/N]2 : CSI2-DATA[P/N]2
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6) What do we do when SI Simulation Results are not good ?
(before vs after Layout Improvement & Results example)
MIPI S-parameter L10 D0[P/N] L9
CN700 Clk[P/N] 1
D1[P/N]
2
2
Original Layout Modified Layout Original Layout Modified Layout
Original layout Modified Layout
1. In the original layout there is no void under the inductor pads and
their reference layer is at L9. The impedance at pads are around
34ohm and this causes impedance mismatch with the overall trace
impedance(84.6ohm typ). Hence, we void layers L7,8,9 and make
the reference for Inductor pad at L6. The impedance reaches a
saturation value of around 72ohm. This gives better impedance
matching and improves the return loss.
2. Increased the via clearance at L10~L6 at both Connector end and
IC end to improve return loss.
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6) What do we do when SI Simulation Results are not good ?
(before vs after Layout Improvement & Results example)
LVDS S-parameter L1+L2 L1+L2
Capacitor pad 1 & 2
Capacitor pad 1 & 2 Refer L3 Ground
Refer L2 Ground
With original design before improvement, S21 fails to satisfy the limit line at around 2.3GHz and 2.8 GHz.
After improvement design , S21 improves and satisfies the limit line with some margin.
For S11, both before and after improvement design satisfy the limit line. We can observe better S11 from around 2GHz onwards for after improvement design.
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6) What do we do when SI Simulation Results are not good ?
(before vs after Layout Improvement & Results example)
DDR4 Waveform
Topology
VTT
R1
IC1
DDR3L_ODT_60_1P35_M#310
V1 IC2 V2 IC3 V3 IC4 V4 IC5 V5 IC6
Simulation Probe (pin)
V : Voltage
R1 = 39ohm (Original) R1 = 22ohm (What-if case)
Result : Eye Diagram, V2 (Single-ended) Result : Eye Diagram, V2 (Single-ended)
Vin Limit (H) Vin Limit (H)
=1.44V =1.44V
Vin Limit (L)
=-0.3V
Vin Limit (L)
=-0.3V
With original termination of R1=39ohm, the signals fail to satisfy the eyemask but manages to satisfy the eye mask with R1=22ohm.
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