LAB REPORT
Department Of Electrical And Electronics Engineering
Course Title: Communication Systems Lab
Course Code: EEE2302
Summer 2025
Experiment No: 03
Experiment name:
Study of gate level minimization using K-map
Submitted To:
circuit and verification with actual value.
MD Nizam Uddin Tanim
Lecturer
Submitted By:
Name: Mohammad Samin Saqlain
ID: 241016005
Section: 01
Group: 02
Date of Submission: 27 June 2025
Objective:
Objective of this experiment is to study and understand the process of gate level minimization
using Karnaugh map.
Theory:
A Karnaugh map provides a systematic method for simplifying Boolean expressions and,
if properly used, will produce the simplest SOP or POS expression possible, known as
the minimum expression.
For an SOP expression in standard form, a 1 is placed on the Karnaugh map for each
product term in the expression. Each 1 is placed in a cell corresponding to the value of
a product term.
Karnaugh maps can be used for expressions with two, three, four, and five variables, but we
will discuss only 4-variable situations to illustrate the principles [1].
Let, the 4-variables be A, B, C and D. The required K-map for these variables:
AB/CD 00 01 11 10
00 m0 m1 m3 m2
01 m4 m5 m7 m6
11 m12 m13 m15 m14
10 m8 m9 m11 m10
Apparatus:
• Trainer board
• Wires
• IC 7404, 7408 and 7432
Procedure:
1. Reviewed the provided SOP function.
2. Plotted the values in the K-map.
3. Simplified the K-map and obtained the function.
4. Constructed the circuit in the trainer board as per the simplified logic.
5. Verified the logic by switching the data switches.
Calculation:
Given function,
F = ∑ m3, m4, m5, m6, m7, m12, m13
AB/CD 00 01 11 10
00 0 0 1 0
01 1 1 1 1
11 1 1 0 0
10 0 0 0 0
The Boolean expression of the given function = A’BC’D’ + ABC’D’ + A’BC’D + ABC’D +
A’B’CD + A’BCD + A’BCD’
The total gate input cost = 28 + 14 + 13 = 55
From the red grouping, common values = BC’
From the yellow grouping, common values = A’CD
From the dark grouping, common values = A’B
Therefore, the simplified Boolean expression = A’B + BC’ + A’CD
The total gate input cost = 7 + 4 + 3 = 14
Diagram:
Picture of the circuit:
Results:
The output table of the circuit:
A B C D Output
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0
The output of the circuit matched the initial logic function perfectly.
Precaution:
1. Using the correct ICs
2. Checking for loose connection
Discussion:
After completing our experiment, we were successful in implementing Karnaugh map to
simplify a given logic function.
After plotting the given function into the k-map, the Boolean expression obtained had a total gate
input cost of 55. So, after simplifying the expression using the k-map, a simpler expression was
obtained with the total gate input cost on 14.
From the output table it was confirmed that the simpler expression was able to give the exact
same output as the initial given Boolean logic expression.
Therefore, we concluded the implementation and verification of Karnaugh map in gate
minimization and achieved our objective.
Reference:
• [1] Thomas L. Floyd, “Boolean algebra and Logic simplification,” in Digital
Fundamentals, 11th edition, ch. 4, sec. 4.8-9, pp 219-222.
Data sheet:
