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UNIVERSAL SHIFT REGISTER
OPERATION:
Mode control Operation
S0 S1
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
RING COUNTER
In this diagram, we can see that the clock pulse (CLK) is applied to all the flip-flop
simultaneously. Therefore, it is a Synchronous Counter.
Also, here we use Overriding input (ORI) to each flip-flop. Preset (PR) and Clear (CLR) are used
as ORI.
When PR is 0, then the output is 1. And when CLR is 0, then the output is 0. Both PR and CLR
are active low signal that is always works in value 0.
Working –
Here, ORI is connected to Preset (PR) in FF-0 and it is connected to Clear (CLR) in FF-1, FF-2,
and FF-3. Thus, output Q = 1 is generated at FF-0 and rest of the flip-flop generate output Q = 0.
This output Q = 1 at FF-0 is known as Pre-set 1 which is used to form the ring in the Ring
Counter.
This Preseted 1 is generated by making ORI low and that time Clock (CLK) becomes don’t care.
After that ORI made to high and apply low clock pulse signal as the Clock (CLK) is negative
edge triggered. After that, at each clock pulse the preseted 1 is shifted to the next flip-flop and
thus form Ring.
From the above table, we can say that there are 4 states in 4-bit Ring Counter.
4 states are:
1000
0100
0010
0001
TWISTED RING COUNTER (JOHNSON COUNTER)
Applications of Shift Registers
Following are the applications of shift registers:
Shift register is used as Parallel to serial converter, which converts the parallel data
into serial data. It is utilized at the transmitter section after Analog to Digital
Converter ADC block.
Shift register is used as Serial to parallel converter, which converts the serial data into
parallel data. It is utilized at the receiver section before Digital to Analog
Converter DAC block.
Shift register along with some additional gates generate the sequence of zeros and ones.
Hence, it is used as sequence generator.
Shift registers are also used as counters. There are two types of counters based on the
type of output from right most D flip-flop is connected to the serial input. Those are
Ring counter and Johnson Ring counter.
DIGITAL COUNTERS
In digital logic and computing, a counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in relationship to a clock. It
basically counts the number of input clock pulses. Each pulse applied to the clock
input increments or decrements the number in the counter so that it goes through a prescribed
sequence of states upon the application of input pulses. The prescribed sequence can be a binary
sequence or any other sequence. The modulus (or Mod) of a counter is the number of different
states it is allowed to have. Counter modulus is normally 2N , where N is the number of flip flops
(unless controlled by a feedback circuit which limits the number of possible states ,an example
being the decimal counter). For example a 3 bit binary counter has 8 unique states (i.e 000,
001,010,011,100,101,110 and 111), so its modulus (Mod) is 8 (=23).
Counters are very widely used in almost all computers and other digital electronic
systems. There are two major categories of counters: asynchronous counters (ripple counters)
and synchronous counters.
Synchronous counters are faster as all the flip flops are triggered by a common clock signal. On
the other hand, in asynchronous counters the external clock (main clock) triggers only the first
flip flop. The output of first flip flop serves as clock for second flip flop, output of second flip
flop serves as clock for third flip flop and so on (that’s why it is also called a ripple counter), and
hence it is slower.
Asynchronous Counters
Triggering type Clock for next FF Counter type
Negative edge Q’ Down counter
Negative edge Q Up counter
Positive edge Q’ Up counter
Positive edge Q Down counter
3 bit binary (Mod 8) asynchronous up counter
[State diagram 3 bit ripple up counter]
Let’s use positive edge triggered JK flip flops.
3 bit binary (Mod 8) asynchronous down counter
Let’s use positive edge triggered T flip flops
4 bit binary (Mod 16) asynchronous up counter
Let’s use positive edge triggered D flip flops
3 bit binary (Mod 8) asynchronous UP/DOWN counter
Let’s use negative edge triggered T flip flops.
Here, if M=0, this will work as 3 bit up counter and when M=1, it will work as 3 bit down
counter.
Asynchronous BCD counter (Decade counter)
[State diagram BCD ripple counter]
A typical use of the CLR inputs is illustrated in the BCD Up Counter. The counter outputs
Q1 and Q3 are connected to the inputs of a NAND gate, the output of which is taken to
the CLR inputs of all four flip-flops. When Q1 and Q3 are both at logic 1, the output terminal
of the limit detection NAND gate (LD1) will become logic 0 and reset all the flip-flop outputs
to logic 0.
Because the first time Q1 and Q3 are both at logic 1 during a 0 to 1510 count is at a count of ten
(10102), this will cause the counter to count from 0 to 910 and then reset to 0, omitting 1010 to
1510.
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