Department of Computer Engineering
Academic Year: 2023-2024
Course Name and Code: MIC (22415) Class: CO4I
Name of Course Teacher: Ms. Anjali Gharat
Topic: Chapter 1(8086 -16 bit Microprocessor )
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1 List features of 8086 microprocessor. 4M
1) It has a 16 bit data bus
2) 8086 has a 20 bit address lines can access up to.(220= 1MBmemory locations.
3) It can support up to 64K I/O ports.
4) It provides 16-bit registers. AX,BX,CX,DX,CS,SS,DS,ES,BP,SP,SI,DI,IP & FLAG REGISTER.
5) It has multiplexed address and data bus AD0- AD15 and A16 – A19.
6) 8086 is designed to operate in two modes, Minimum and Maximum.
7) It can prefetches up to 6 instruction bytes from memory and queues them in order to
speed up instruction execution.
8) Interrupts:-8086 has 256 vectored interrupts.
9) Provides separate instructions for string manipulation.
10) Operating clock frequencies 5MHz, 8MHz, 10MHz.
2 Draw the neat labelled functional block diagram of 8086. 6M
3 Write the function of BIU and EU. 4M
FUNCTIONS OF BUS INTERFACE UNIT:
1. Communication with External devices and peripheral including memory via bus.
2. Fetch the instruction or data from memory.
3. Read data from the port.
4. Write the data to memory and port.
5.Calculation of physical address for accessing the data to and from memory
6. Supports instruction queuing
FUNCTIONS OF EXECUTION UNIT:
1.To tell BIU to fetch the instructions or data from memory
2. To decode the instructions.
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3. To generate different internal and external controls signal.
4. To execute the instructions.
5.To perform Arithmetic and Logic Operations
4 Name the general purpose registers of 8086 giving brief description of each.
1 AX (Accumulator) – Used to store the result for arithmetic / logical operations
2. BX – Base – used to hold the offset address or data in indirect addressing mode.
3. CX – acts as a counter for repeating or looping instructions.
4. DX –Used with AX to hold 32 bit values during multiplication and division.
5. BP – Base Pointer BP can hold offset address of any location in the stack segment.
6. SP –Stack Pointer – Contains the offset of the top of the stack.
7. SI – Source Index – Used in string movement instructions. Holds offset address of source
data in Data segment
8.DI – Destination Index –Used to hold offset address of Extra segment
9. IP – Instruction Pointer – Contains 16 bit offset address of instruction
5 Describe instruction queue in detail/ Explain the concept of pipelining OR
What is pipelining? How it improves the processing speed.
In 8086, pipelining is the technique of overlapping instruction fetch and execution
mechanism.
To speed up program execution, the BIU fetches as many as six instruction bytes ahead
of time from memory. The size of instruction prefetching queue in 8086 is 6 bytes.
While executing one instruction other instruction can be fetched. Thus it avoids the
waiting time for execution unit to receive other instruction.
BIU stores the fetched instructions in a 6 level deep FIFO . The BIU can be fetching
instructions bytes while the EU is decoding an instruction or executing an instruction which
does not require use of the buses.
When the EU is ready for its next instruction, it simply reads the instruction from the
queue in the BIU.
This is much faster than sending out an address to the system memory and waiting for
memory to send back the next instruction byte or bytes.
This improves overall speed of the processor
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Advantages:
1. Increased Instruction Throughput
2. Improved Efficiency of the Execution Unit (EU)
6 Describe memory segmentation in 8086 and list its advantages.
Memory Segmentation: Segmentation is the process in which the main memory of the
computer is logically divided into different segments and each segment has its own base
address. It is basically used to enhance the speed of execution of the computer system, so
that the processor is able to fetch and execute the data from the memory easily and fast.
The memory in an 8086 microprocessor is organized as a segmented memory. The physical
memory is divided into 4 segments namely, - Data segment, Code Segment, Stack Segment
and Extra Segment.
Description:
Data segment is used to hold data, Code segment for the executable program, Extra
segment also holds data specifically in strings and stack segment is used to store stack
data.
Each segment is 64Kbytes & addressed by one segment register. i.e CS,DS,ES or SS
The 16 bit segment register holds the starting address of the segment.
The offset address to this segment address is specified as a 16-bit displacement (offset)
between 0000 to FFFFH. Hence maximum size of any segment is 216=64K locations.
Since the memory size of 8086 is 1Mbytes, total 16 segments are possible with each
having 64Kbytes.
The offset address values are from 0000H to FFFFH so the physical address range from
00000H to FFFFFH.
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Advantages of the Segmentation The main advantages of segmentation are as follows:
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different segments. • Code
related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation allows the use
of 16 bit registers to give an addressing capability of 1 Megabytes. Without segmentation,
it would require 20 bit registers.
• It is possible to enhance the memory size of code data or stack segments beyond 64 KB
by allotting more than one segment for each area.
7 Define Logical and Effective address. Describe how 20 bit Physical address is generated in
8086. If CS = 348AH and IP = 4214H, calculate the Physical Address.
Logical Address
• Logical address are also known as virtual address. It is generated by CPU during program
execution.
• Logical addresses provide a way for the CPU to access different locations in memory
without needing to know the physical organization of the memory
Effective Address or Offset Address:
The offset for a memory operand is called the operand's effective address or EA. It is an
unassigned 16 bit number that expresses the operand's distance in bytes from the
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beginning of the segment in which it resides.
Generation of 20 bit physical address in 8086:-
1. Segment registers carry 16 bit data, which is also known as base address.
2. BIU appends four 0 bits to LSB of the base address. This address becomes 20- bit
Address.
3. Any base/pointer or index register carries 16 bit offset.
4. Offset address is added into 20-bit base address which finally forms 20 bit physical
address of memory location
if CS 348AH and IP = 4214H,
Physical address=Segment base address*10+Offset (Effective) address
=CS*10 + IP
=348AH*10H+4214H
= 38AB4 H
ii) Assume DS= 2632H, SI=4567H calculate physical address.
DS : 26320H ……...0 added by BIU
+ SI : 4567H
---------------
2A887H
8 Describe register organization of 8086 microprocessor
Register Organization of 8086
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1. AX (Accumulator) - Accumulator register consists of two 8-bit registers AL and AH,
which can be combined together and used as a 16- bit register AX. AL in this case contains
the low-order byte of the word, and AH contains the high-order byte. Accumulator can be
used for I/O operations, rotate and string manipulation.
2. BX –This register is mainly used as a base register. It holds the starting base location of a
memory region within a data segment. It is used as offset storage for forming physical
address in case of certain addressing mode
3. CX – It is used as default counter or count register in case of string and loop
instructions..
4. DX – Data register can be used as a port number in I/O operations and implicit operand
or destination in case of few instructions. In integer 32-bit multiply and divide instruction
the DX register contains high-order word of the initial or resulting number.
5. CS – Code Segment – holds base address for all executable instructions in a program
Segment registers: To complete 1Mbyte memory is divided into 16 logical segments. The
complete 1Mbyte memory segmentation is as shown in above figure. Each segment
contains 64Kbyte of memory. There are four segment registers.
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP)
and base pointer (BP) registers is located in the stack segment.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program
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data. By default, the processor assumes that all data referenced by general registers (AX,
BX, CX, DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions. It points to the data
segment memory where the data is resided.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data.
Pointers and index registers
The pointers contain within the particular segments. The pointers IP, BP, SP usually contain
offsets within the code, data and stack segments respectively.
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string manipulation
instructions
9 Draw and explain flag register format of 8086.
9. Pin diagram and pin functions of 8086:
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Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V
DC supply for its operation. The 8086 uses 20-line address bus. It has a 16-line data bus.
The 20 lines of the address bus operate in multiplexed mode. The 16-low order address
bus lines have been multiplexed with data and 4 high-order address bus lines have been
multiplexed with status signals.
AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with
data. When AD lines are used to transmit memory address the symbol A is used instead of
AD, for example A0-A15. When data are transmitted over AD lines the symbol D is used in
place of AD, for example D0-D7, D8-D15 or D0-D15.
A16-A19: High order address bus. These are multiplexed with status signals.
S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to
passive state (1, 1, 1 during T3 or Tw (when ready is inactive). These are used by the 8288
bus controller for generating all the memory and I/O operation) access control signals. Any
change in S2, S1, and S0 during T4 indicates the beginning of a bus cycle
BHE’/S7:
Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most
significant half of data bus, D8-D15.
8-bit device connected to upper half of the data bus use BHE (Active Low) signal.
It is multiplexed with status signal S7.
S7 signal is available during T2, T3 and T4
RD’: This is used for read operation. It is an output signal. It is active when low.
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READY: This is the acknowledgement from the memory or slow device that they have
completed the data transfer. The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the microprocessor. The signal is
active high (1).
INTR: Interrupt Request. This is triggered input. This is sampled during the last clock cycles
of each instruction for determining the availability of the request. If any interrupt request
is found pending, the processor enters the interrupt acknowledge cycle. This can be
internally masked after resetting the interrupt enable flag. This signal is active high (1) and
has been synchronized internally.
NMI: Non maskable interrupt. This is an edge triggered input which results in a type II
interrupt. A subroutine is then vectored through an interrupt vector lookup table which is
located in the system memory. NMI is non-maskable internally by software. A transition
made from low (0) to high (1) initiates the interrupt at the end of the current instruction.
This input has been synchronized internally
INTA: Interrupt acknowledge. It is active low (0) during T2, T3 and Tw of each interrupt
acknowledge cycle.
MN/MX’: Minimum/Maximum. This pin signal indicates what mode the processor will
operate in.
RQ’/GT0′: These are the Request/Grant signals used by the other processors requesting
the CPU to release the system bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
LOCK’:
It’s an active low pin. It indicates that other system bus masters have not been allowed
to gain control of the system bus while LOCK’ is active low (0). The LOCK signal will be
active until the completion of the next instruction.
When this signal is active, it indicates to the other processors not to ask the CPU to leave
the system bus. It is activated using the LOCK prefix on any instruction
RESET: This pin requires the microprocessor to terminate its present activity immediately.
The signal must be active high (1) for at least four clock cycles.
TEST’: This examined by a ‘WAIT’ instruction. If the TEST pin goes low (0), execution will
continue, else the processor remains in an idle state. The input is internally synchronized
during each of the clock cycle on leading edge of the clock.
CLK: Clock Input. The clock input provides the basic timing for processing operation and
bus control activity. It’s an asymmetric square wave with a 33% duty cycle.
Vcc: Power Supply (+5V D.C.)
GND: Ground
DT/R: Data Transmit/Receive. This pin is required in minimum systems that want to use an
8286 or 8287 data bus transceiver. The direction of data flow is controlled through the
transceiver. DEN: Data enable. This pin is provided as an output enable for the 8286/8287
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in a minimum system which uses transceiver.
DEN is active low (0) during each memory and input-output access and for INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is
an active high (1). The microprocessor receiving the HOLD request will issue HLDA (high) as
an acknowledgement in the middle of a T4 or T1 clock cycle.
ALE: Address Latch Enable. ALE is provided by the microprocessor to latch the address into
the 8282 or 8283 address latch. It is an active high (1) pulse during T1 of any bus cycle. ALE
signal is never floated, is always integer.
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